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DaladierTypewritten textLIBROS UNIVERISTARIOS Y SOLUCIONARIOS DE MUCHOS DE ESTOS LIBROS
LOS SOLUCIONARIOS CONTIENEN TODOS LOS EJERCICIOS DEL LIBRORESUELTOS Y EXPLICADOSDE FORMA CLARA
VISITANOS PARADESARGALOS GRATIS.
1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 1 2000 by Prentice-Hall, Inc.
1-1.
1-4.
1-7.
1-9.a) 7562/8 = 945 + 2/8 2
945/8 = 118 +1/8 1118/8 = 14 + 6/8 614/8 = 1 + 6/8 6
1/8 = 1/8 1
0.45 8 = 3.6 30.60 8 = 4.8 40.80 8 = 6.4 6
0.20x8 = 3.2 3(7562.45)10 = (16612.3463)8
b) (1938.257)10 = (792.41CA)16c) (175.175)10 = (10101111.001011)2
Decimal, Binary, Octal and Hexadecimal Numbers from (16)10 to (31)10Dec 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31Bin 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111Oct 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37Hex 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Decimal Binary Octal Hexadecimal369.3125 101110001.0101 561.24 171.5189.625 10111101.101 275.5 BD.A214.625 11010110.101 326.5 D6.A
62407.625 1111001111000111.101 171707.5 F3C7.A
1101001( )2 26 25 23 20+ + + 105= =10001011.011( )2 27 23 21 20 2 2 2 3+ + + + + 139.375= =10011010( )2 27 24 23 21+ + + 154= =
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2
Problem Solutions Chapter 1
1-11.a) (673.6)8 = (110 111 011.110)2
= (1BB.C)16b) (E7C.B)16 = (1110 0111 1100.1011)2
= (7174.54)8c) (310.2)4 = (11 01 00.10)2
= (64.4)8
1-15.a) (BEE)r = (2699)10
By the quadratic equation: r = 15 or r 16.27ANSWER: r = 15b) (365)r = (194)10
By the quadratic equation: r = -9 or 7ANSWER: r = 7
1-17.(694)10 = (0110 1001 0100)BCD(835)10 = (1000 0011 0101)BCD
10110 1001 0100
+1000 +0011 +01011111 1100 1001
+0110 +0110 +00000001 0101 1 0010 1001
1-20.a) (0100 1000 0110 0111)BCD = (4867)10
= (1001100000011)2b) (0011 0111 1000.0111 0101)BCD = (378.75)10
= (101111010.11)2
1-23.a) (101101101)2b) (0011 0110 0101)BCDc) 0011 0011 0011 0110 0011 0101ASCII
1-25. BCD Digits with Odd and Even Parity
0 1 2 3 4 5 6 7 8 9Odd 1 0000 0 0001 0 0010 1 0011 0 0100 1 0101 1 0110 0 0111 0 1000 1 1001Even 0 0000 1 0001 1 0010 0 0011 1 0100 0 0101 0 0110 1 0111 1 1000 0 1001
11 r2 14+ r1 14 r0+ 2699=11 r2 14+ r 2685 0=
3 r2 6+ r1 5+ r0 194=
3 r2 6+ r 189 0=
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 2 2000 by Prentice-Hall, Inc.
2-1. a)
b)
c)
2-2.a) X Y + XY + XY = X + Y
= (XY+ X Y ) + (X Y + XY) = X(Y + Y) + Y(X + X) + = X + Y
Verification of DeMorgans Theorem
X Y Z XYZ XYZ X+Y+Z0 0 0 0 1 10 0 1 0 1 10 1 0 0 1 10 1 1 0 1 11 0 0 0 1 11 0 1 0 1 11 1 0 0 1 11 1 1 1 0 0
The Second Distributive Law
X Y Z YZ X+YZ X+Y X+Z (X+Y)(X+Z)0 0 0 0 0 0 0 00 0 1 0 0 0 1 00 1 0 0 0 1 0 00 1 1 1 1 1 1 11 0 0 0 1 1 1 11 0 1 0 1 1 1 11 1 0 0 1 1 1 11 1 1 1 1 1 1 1
X Y Z XY YZ XZ XY+YZ+XZ XY YZ XZ XY+YZ+XZ0 0 0 0 0 0 0 0 0 0 00 0 1 0 1 0 1 0 0 1 10 1 0 1 0 0 1 0 1 0 10 1 1 1 0 0 1 0 0 1 11 0 0 0 0 1 1 1 0 0 11 0 1 0 1 0 1 1 0 0 11 1 0 0 0 1 1 0 1 0 11 1 1 0 0 0 0 0 0 0 0
XYZ X Y Z+ +=
X YZ+ X Y+( ) X Z+( )=
XY YZ XZ+ + XY YZ XZ+ +=
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2
Problem Solutions Chapter 2
b) A B+ B C + AB + B C = 1= (A B+ AB) + (B C + B C)= B(A + A) + B(C + C)= B + B= 1
c) Y + X Z + X Y = X + Y + Z= Y + X Y + X Z = (Y + X)(Y + Y) + X Z = Y + X + X Z= Y + (X + X)(X + Z)= X + Y + Z
d) X Y + Y Z + XZ + XY + Y Z = X Y + XZ + Y Z= X Y + Y Z(X + X) + XZ + XY + Y Z= X Y + X Y Z + X Y Z + XZ + XY + Y Z= X Y (1 + Z) + X Y Z +XZ + XY + Y Z= X Y + XZ(1 + Y) + XY + Y Z= X Y + XZ + XY (Z + Z)+ Y Z= X Y + XZ + XY Z +Y Z (1 + X)= X Y + XZ(1 + Y) + Y Z = X Y + XZ + Y Z
2-7.a) X Y + XYZ + XY = X + XYZ = (X + XY)(X + Z)
= (X + X)(X + Y)(X + Z) = (X + Y)(X + Z) = X + YZ b) X + Y(Z + X Z) = X + YZ + X Y Z = X + (YZ + X)(YZ + YZ) = X + Y(X + YZ)
= X + XY + YZ = (X + X)(X + Y) + YZ = X + Y + YZ = X + Y c) WX(Z + YZ) + X(W + W YZ) = WXZ + WXYZ + WX + WXYZ
= WX + WXZ + WXZ = WX + WX = Xd)
=
=
= A + C + A(BCD)= A + C + BCD= A + C + C(BD)= A + C + BD
2-9.a)b)c)d)
AB AB+( ) CD CD+( ) AC+ABCD ABCD ABCD ABCD A C+ + + + +A C ABCD+ +
F A B+( ) A B+( )=F V W+( )X Y+( )Z=F W X+ Y Z+( ) Y Z+( )+[ ] W X+ YZ YZ+ +[ ]=F ABC A B+( )C A B C+( )+ +=
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3
Problem Solutions Chapter 2
2-10.
a) Sum of Minterms: XYZ + XYZ + XYZ + XYZ Product of Maxterms: (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z)
b) Sum of Minterms: A B C + A B C + A B C + A B CProduct of Maxterms: (A + B + C)(A + B + C)(A + B + C)(A + B + C)
c) Sum of Minterms: W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z+ W X Y Z
Product of Maxterms: (W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)(W + X + Y + Z)
2-12.a) (AB + C)(B + CD) = AB + BC + ABCD = AB + BC s.o.p.
= B(A + C) p.o.s.b) X + X ((X + Y)(Y + Z)) = (X + X)(X + (X + Y)(Y + Z))
= (X + X + Y)(X + Y + Z) = X + Y + Z s.o.p. and p.o.s.c) (A + BC + CD)(B + EF) = (A + B + C)(A + B + D)(A + C + D)(B + E)(B + F) p.o.s.
(A + BC + CD)(B + EF) = A(B + EF) + BC(B + EF) + CD(B + EF)= AB + AEF + BCEF + BCD + CDEF s.o.p.
2-15.
Truth Tables a, b, c
X Y Z a A B C b W X Y Z c0 0 0 0 0 0 0 1 0 0 0 0 00 0 1 0 0 0 1 1 0 0 0 1 00 1 0 0 0 1 0 0 0 0 1 0 10 1 1 1 0 1 1 1 0 0 1 1 01 0 0 0 1 0 0 0 0 1 0 0 01 0 1 1 1 0 1 0 0 1 0 1 01 1 0 1 1 1 0 0 0 1 1 0 11 1 1 1 1 1 1 1 0 1 1 1 0
1 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1
X
Y
ZA
B
C
a) b) c)
X Z + XY A + CB B + C
A
B
C
111
1 11
1 1 1 11
11
11
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4
Problem Solutions Chapter 2
2-18.
2-19.Using K-maps:a) Prime = XZ, WX, X Z, W Z b) Prime = CD, AC, B D, ABD, B C c) Prime = AB, AC, AD, BC, BD, CD
Essential = XZ, X Z Essential = AC, B D, ABD Essential = AC, BC, BD
2-22.Using K-maps:a) s.o.p. CD + AC + B D b) s.o.p.A C + B D + A D c) s.o.p.B D + ABD + (ABC or ACD)
p.o.s.(C + D)(A + D)(A + B + C) p.o.s.(C + D)(A + D)(A + B + C) p.o.s.(A + B)(B + D)(B + C + D)
2-25.
2-28.
WX
Y
Z
AB
C
D
a) b) c)
X
Y
Z
m 3 5 6 7, , ,( ) m 3 4 5 7 9 13 14 15, , , , , , ,( ) m 0 2 6 7 8 10 13 15, , , , , , ,( )
111
1111
1
1 11
1 111 1
1
11
1
Primes = AB, AC, BC, A B CEssential = AB, AC, BCF = AB + AC + BC
Primes = X Z, XZ, WXY, WXY, W Y Z, WYZEssential = X ZF = X Z + WXY + WXY
Primes = AB, C, AD, BDEssential = C, AD F = C + AD + (BD or AB)
WX
Y
Z
AB
C
D
a) b) c)
A
B
C
11
1
11 1
11
11 1
1 1 111
XX X
X
X X
X XX
X X
AB
ABC
DC
DAB
C DABDC
AB
AB
CDC
D
AB
CD
AB
DC
4-input NANDfrom 2-input NANDsand NOTs
a)
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5
Problem Solutions Chapter 2
2-30.
2-34.
2-37.
2-39.4 0.5 = 2 ns
2-44.
P-Logic N-LogicX Y NAND NOR X Y NAND NOR X Y NAND NORL L H H 0 0 1 1 1 1 0 0L H H L 0 1 1 0 1 0 0 1H L H L 1 0 1 0 0 1 0 1H H L L 1 1 0 0 0 0 1 1
AB
C
D
ABAB
CD
CD
b)
AB
C
D
a) b)
WX
Y
ZF A B C+ +( ) A C+( ) A D+( )= F W X+( ) W X+( ) Y Z+( ) Y Z+( )=
1 11 1 1 1
1
11
ACAD
11
BA
C 1Y ZYZ A
W XWX
X Y XY XY+=
Dual (X Y ) Dual XY XY+( )=X Y+( ) X Y+( )=
XY XY+ X Y+( ) X Y+( )=X Y+( ) X Y+( )=
16 inputs16 inputs
6 inputs
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 3 2000 by Prentice-Hall, Inc.
3-2.
3-3.
3-6.
T1
T2
T3
T4
A
BC
DX
Y
T1 = BC, T2 = ADT3 = 1 , T4 = D + BCX = T3T4
= D + BCY = T2T4
= AD(D + BC) = A BCD
X
Y
Z
11 1
XZ
YZ
XZ + ZY
X Y Z T1 T2 T3 T4 T5 F0 0 0 1 1 1 1 1 00 0 1 1 1 1 0 0 10 1 0 1 1 0 1 1 00 1 1 1 1 0 1 1 01 0 0 1 0 1 1 1 01 0 1 1 0 1 1 0 11 1 0 0 1 1 1 1 01 1 1 0 1 1 0 0 1
T1
T2
T3
T4
T5F
X
YZ
F
X Y T1 T2 T3 F0 0 1 0 0 10 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1
T1T2
T3F
X
Y
ASB
M
ASB
M
ASB
M F
G
YX
XZ
ZY
M
A
S
B
T1
M = AS + BS
T1 = ZY + ZY
F = YX + T1X = YX + X(ZY + ZY)= XY + XYZ + XYZ
G = T1X + ZX = XZ + X(Z + Y)(Z + Y)= XZ + X(YZ + Y Z) = XZ + XYZ + X Y Z
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2
Problem Solutions Chapter 3
3-11.
3-13.
3-15.
3-20.
AB
C
D
111 1 1 1
F = AB + AC
A C A B A B A D A B D B C D A B C A C D A C D A C D A B C A B C A B D A B C D
a b c d e f g
AB
C
D
AB
C
D
AB
C
D
AB
C
D
AB
C
D
AB
C
D
AB
C
D
11
11
11
1 1
11
1 11 1
1 1
1 11 1
1
11
11
1
11
1
1
11
11
1
1
1
1
1 1
1 1
1
1
1 11
1
1
b = B + C D + CD c = B + C + D d = BCD + A + B D + BC + CD
e = B D + CD f = A + BD + BC + C D g = A + CD + BC + BC
X X X XX X
X X X XX X
X X X XX X
X X X XX X
X X X XX X
X X X XX X
X X X XX X
a = A + C + BD + B D
V = D0 + D1 + D2 + D3A0 = D1 + D0 D2A1 = D0 D1
D3 D2 D1 D0 A1 A0 V0 0 0 0 X X 0X X X 1 0 0 1X X 1 0 0 1 1X 1 0 0 1 0 11 0 0 0 1 1 1 D0
D1
D2
D3
11 1 1 1
D0D1
D2
D3
A0 A1
X 1 1 1X
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3
Problem Solutions Chapter 3
3-25.
3-29.
3-35.
3-38.
3-41.
8/1 MUXD(0-7) Y0A(0-2)
8/1 MUXD(0-6) Y0
A(0-2)
D(0-7)
D(8-14)
D(7)
A(0-2)
A(3)3 OR gates
4/1 MUX
0123
A0
Y
A1A B C D F A B C D F0 0 0 0 0
D
1 0 0 0 0 CD0 0 0 1 1 1 0 0 1 00 0 1 0 0 1 0 1 0 00 0 1 1 1 1 0 1 1 10 1 0 0 1 C D 1 1 0 0 1 +V0 1 0 1 0 1 1 0 1 10 1 1 0 0 1 1 1 0 10 1 1 1 0 1 1 1 1 1
AB
+V
FDC
DCD
C1 T3 T2+ T1C0 T2+ A0B0C0 A0 B0++ A0 B0+( )C0 A0B0+ A0B0 C0+( ) A0 B0+( )= = = = =C1 A0B0 A0C0 B0C0+ +=
S0 C0 T4 C0 T1T2 C0 A0B0 A0 B0+( ) C0 A0 B0+( ) A0 B0+( ) C0 A0B0 A0B0+= = = = =
S0 A0 B0 C0 =
1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 10 1 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
+43 = 0101011-17 = 1101111-43 = 1010101+17 = 0010001
43 0101011+(17) + 1101111
10011010= 26 = 0011010
43 1010101+ 17 + 0010001
= 26 = 1100110
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4
Problem Solutions Chapter 3
3-45.
3-49.
3-52.
3-55.
3-58.
S A B C4 S3 S2 S1 S0a) 0 0111 0110 0 1 1 0 1b) 0 0100 0101 0 1 0 0 1c) 1 1100 1010 1 0 0 1 0d) 1 0101 1010 0 1 0 1 1e) 1 0000 0010 0 1 1 1 0
78430258 98989899 09580089 99999999
BCD
Gates: 8Literals: 9
A B C D E F G H0 0 0 0 0 1 0 0 11 0 0 0 1 1 0 0 02 0 0 1 0 0 1 1 13 0 0 1 1 0 1 1 04 0 1 0 0 0 1 0 15 0 1 0 1 0 1 0 06 0 1 1 0 0 0 1 17 0 1 1 1 0 0 1 08 1 0 0 0 0 0 0 19 1 0 0 1 0 0 0 0
H D=G C=F BC BC+=E ABC=
EXCESS-3
Gates: 4Literals: 4
A B C D E F G H0 0 0 1 1 1 1 0 01 0 1 0 0 1 0 1 12 0 1 0 1 1 0 1 03 0 1 1 0 1 0 0 14 0 1 1 1 1 0 0 05 1 0 0 0 0 1 1 16 1 0 0 1 0 1 1 07 1 0 1 0 0 1 0 18 1 0 1 1 0 1 0 09 1 1 0 0 0 0 1 1
H D=G C=F B=E A=
X1
X2
X3
X4
FN1
N2
N3 N4
N5
N6
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5
Problem Solutions Chapter 3
3-62.
3-66.
3-69.
3-72.
From 3-2: F = X Z + Z YUsing Nand Gates:...
signal T: std_logic_vector(0 to 2);begin g0: NOT1 port map (Y, T(0)); g1: NAND2 port map (X, Z, T(1)); g2: NAND2 port map (Z, T(0), T(2)); g3: NAND2 port map (T(1), T(2), F); end
X1
X2
X3
X4
FN1
N2
N3 N4
N5
N6
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6
Problem Solutions Chapter 3
3-76.
3-80.
//Fucntion F from problem 3-2 = X Z + Z Y
module cicuit_3_76(X, Y, Z, F); input X, Y, Z; output F;
assign F = (X & Z) | (Z & ~Y);endmodule
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 4 2000 by Prentice-Hall, Inc.
4-3. (All simulations performed using Xilinx Foundation Series software.)
4-4.
4-5.
4-6.
DR
S
Q
QC
R
SQ
Q
C
C
J
K
Y
QReset
J=0 , K=1Complement
J=1 , K=1Set
J=1 , K=0No ChangeJ=0 , K=0
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2
Problem Solutions Chapter 4
4-10.
4-12.
4-17.
J K Q(t)Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
S R Q(t)Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X
D Q(t)Q(t+1)0 0 00 1 01 0 11 1 1
T Q(t)Q(t+1)0 0 00 1 11 0 11 1 0
Q t 1+( ) S RQ+=Q t 1+( ) JQ KQ+=
Q t 1+( ) D= Q t 1+( ) T Q=
JA = B KA = BXJB = X KB = AX + AX
A(t+1) = JAA + KAA = BA+ BA +XAB(t+1) = JBB + KBB = X B + ABX + ABX
000
001 010
011100
101
110
111
X = 1
X = 0
000
001 010
011
100 101
110111
Present state Input Next state
A B C X A B B0000000011111111
0000111100001111
0011001100110011
0101010101010101
1001011010010110
0000000011111111
0000111100001111
State diagram is the combination of the above two diagrams.
Present state Input Next state Output
A B X A B Y00001111
00110011
01010101
00110011
10010110
01101001
0 1
2 3
1/1 0/0
1/00/1
0/01/1
0/11/0
Format: X/Y
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3
Problem Solutions Chapter 4
4-19.
4-20.
4-24.
4-25.
Present state Input Next state
A B X A B00001111
00110011
01010101
01001110
00100111
A
B
X
A
B
X
DA DB
DA = AB + AX + BX DB = AX + BX
111 1
111 1
0 1
10/1
x1/x00/0x1/x
00/110/0
Present state Inputs Next state Output
Q(t) X Y Q(t+1) Z00001111
00110011
01010101
00101010
0X1X1X0X
Format: XY/Z (x = unspecified)
Present state Input Next state Output
A B X A B Y00001111
00110011
01010101
00011011
10110001
11000000
A
B
X
A
B
X
11 11
11
11
DA DB
DA = AX + BX DB = BX + A X
A
B
X
11
Y
Y = A B
Present state Input Next state
A J K A00001111
00110011
01010101
00111010
A
J
K
11 1
1
DA
DA = AJ+ AK
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4
Problem Solutions Chapter 4
4-30.
4-33.
4-36.
Present state Input Next state FF Inputs
A B X A B JA KA JB KB00001111
00110011
01010101
00011011
10110001
0001XXXX
XXXX1100
10XX00XX
XX00XX10
JA = BX
KA = B X + B X
JB = A XKB = A X
Present state Inputs Next state FF Inputs
A B E X A B JA KA JB KB0000000011111111
0000111100001111
0011001100110011
0101010101010101
0010000111011110
0011110000111100
00100001XXXXXXXX
XXXXXXXX00100001
0011XXXX0011XXXX
XXXX0011XXXX0011
JA = E(BX + B X)
KA = E(BX + B X)
JB = E
KB = E
Present state Input Next state FF Inputs
A B X A B TA TB00001111
00110011
01010101
00101110
01010110
00100001
01100101
TB = ABX + ABX + BX
TA = ABX + ABX
T
C
T
CX
A
B
Clock
B
A
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5
Problem Solutions Chapter 4
4-37
4-40.
4-45.
library IEEE;use IEEE.std_logic_1164.all;
entity mux_4to1 isport (
S: in STD_LOGIC_VECTOR (1 downto 0);D: in STD_LOGIC_VECTOR (3 downto
0);Y: out STD_LOGIC
);end mux_4to1;
-- (continued in the next column)
architecture mux_4to1_arch of mux_4to1 isbegin
process (S, D)begin case S is
when "00" => Y Y Y Y null;
end case;
end process; end mux_4to1_arch;
library IEEE;use IEEE.std_logic_1164.all;entity jkff is port ( J,K,CLK: in STD_LOGIC; Q: out STD_LOGIC );end jkff;architecture jkff_arch of jkff issignal q_out: std_logic;begin
state_register: process (CLK)begin if CLK'event and CLK='0' then --CLK falling edge
-- (continued in the next column)
case J is when '0' => if K = '1' then q_out if K = '0' then q_out
6
Problem Solutions Chapter 4
4-47.module JK_FF (J, K, CLK, Q) ;input J, K, CLK ;output Q;reg Q;// (continued in the next column)
always @(negedge CLK)case (J)
0'b0: Q
1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 5 2000 by Prentice-Hall, Inc.
5-3.
5-6.
5-8.
5-10.
5-17.
5-21.
1000, 0100, 1010, 1101 0110, 1011, 1101, 1110
Shifts: 0 1 2 3 4A 0110 1011 0101 0010 1001B 0011 0001 0000 0000 0000C 0 0 1 1 0
Replace each AND gate in Figure 5-6 with an AND gate with one additional input and connect this input to the following:S1 + S0
This will force the outputs of all the AND gates to zero, and, on the next clock edge, the register will be cleared if S1is 0 and S0 is logic one.
Also, replace each direct shift input with this equation: S1S0 This will stop the shift operation from interfering with theload parallel data operation.
a) 1000, 0100, 0010, 0001, 1000b) # States = n
Q0 = Q0EQ1 = (Q0Q1 + Q0Q1)EQ2 = (Q0Q1Q2 + Q1Q2 + Q0Q2)EQ3 = (Q2Q3 + Q1Q3 + Q0Q3 + Q0Q1Q2Q3)E
Clock
J
KC
J
KC
J
KC
J
KC
Q0
Q1
Q2
Q3
SE
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2
Problem Solutions Chapter 5
5-24.
5-26.
TQ8 = (Q1Q8 + Q1Q2Q4)ETQ4 = Q1Q2ETQ2 = Q1Q8ETQ1 = EY = Q1Q8
T
C
T
C
T
C
T
C
E
Y
Q8
Q1
Q2
Q4
Clock
Present state Next state FF Inputs
A B C A B C JA KA JB KB JC KC001
011
010
100
01X
XX1
1X0
X1X
000011
001100
010101
000110
011000
101010
0001XX
XXXX01
01XX00
XX01XX
1X1X1X
X1X1X1
JC = BKB = C
a) b)JB = C
KC = 1
JA = BCKA = C
JC = 1KB = CJB = AC
KC = 1
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3
Problem Solutions Chapter 5
5-29. (All simulations performed using Xilinx Foundation Series software.)
5-33.
library IEEE;use IEEE.std_logic_1164.all;
entity reg_4_bit is port ( CLEAR, CLK: in STD_LOGIC; D: in STD_LOGIC_VECTOR (3 downto 0); Q: out STD_LOGIC_VECTOR (3 downto 0) );end reg_4_bit;
architecture reg_4_bit_arch of reg_4_bit isbegin
process (CLK, CLEAR)begin if CLEAR ='0' then --asynchronous RESET active Low Q
4
Problem Solutions Chapter 5
5-35.
5-39.
module register_4_bit (D, CLK, CLR, Q) ;input [3:0] D ;input CLK, CLR ;output [3:0] Q ;reg [3:0] Q ;always @(posedge CLK or negedge CLR)begin
if (~CLR) //asynchronous RESET active lowQ = 4'b0000;
else //use CLK rising edgeQ = D;
endendmodule
module jk_1_bit (J, K, CLK, CLR, Q) ;input J, K, CLK, CLR ;output Q ;reg Q;always @(negedge CLK or posedge CLR)begin if (CLR) Q
5
Problem Solutions Chapter 5
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79
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 6 2000 by Prentice-Hall, Inc.
6-1.
6-3.
6-9.
6-15.
6-18.
a) A = 13, D = 32 b) A = 18, D = 64 c) A = 25, D = 32 d) A = 32, D = 8
(633)10 = (10 0111 1001)2, (2731)10 = (0000 1010 1010 1011)2
a) 32 b) 20,15 c) 5, 5to32
PTERM INPUTS OUTPUTSX Y Z A B C D
Y Z 1 1 1 1 1 1X Y 2 1 1 1 X Y 3 0 1 1 1 1
X Y Z 4 1 0 0 1 1
PTERM INPUTSA B C D
A 1 1 - BC 2 1 1 BD 3 1- - 1BC 4 0 1 BD 5 0 - 1
BC D 6 1 0 0CD 7 1 1C D 8 0 0
- -
D 9 0- -
- -
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 7 2000 by Prentice-Hall, Inc.
7-1.
7-3.Errata: Interchange statements Transfer R1 to R2 and Clear R2 synchronously with the clock.
7-6.
7-9.
R1 R2
Load Load
ClockC3
LOAD
Q0 Q1 Q2 Q3
C
R1
D0 D1 D2 D3
LOAD
Q0 Q1 Q2 Q3
C
R2
D0 D1 D2 D3
C2C1C0
Clock
Load
Q(0-3)CO
CTR 4
CountD(0-3)C(0-3)
CO
ADD 4CIA(0-3)B(0-3)
Q(0-3)REG 4
D(0-3)
0
CLK
C2
C1C1 R1
R2a)
b)Q(0-3)
REG 4D(0-3)
R1
C(0-3)CO
ADD 4CIA(0-3)B(0-3) Q(0-3)
REG 4D(0-3)
R2
L
L
C1
C2
Clock
0101 11101100 01010100 0100 AND1101 1111 OR1001 1011 XOR
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2
Problem Solutions Chapter 7
7-11.
7-14.
7-19.
7-22.
7-24.
7-26.
sl 1001 1010 sr 0010 0110
R0
a) Destination R1, R2
c) The minimum number of buses needed for operation of the transfersis three since transfer Cb requires three different sources.
MUX
R1 R2 R3 R4
MUX
MUX
d)
C = C8V = C8 C7Z =
N = F7
F7 F6 F5 F4 F3 F2 F1 F0+ + + + + + +
CiX
YFA
CI + 1
X = A S1 + A S0Y = B S1 S0 + B S1 Gi
Ai
S1S0
S0S1Bi
Bi
0D0
D1
D2
D3
Bi
a) XOR = 00, NAND = 01, NOR = 10 XNOR = 11 Out = S1 A B + S0 A B + S1 A B + S0 A B + S1 S0 A Bb) The above is a simplest result.
(a) 1011 (b) 1010 (c) 0001 (d) 1100
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3
Problem Solutions Chapter 7
7-28.
7-31.
(a) R5 = 0000 0100 (d) R5 = 0001 0010(b) R6 = 1111 1110 (e) R4 = 0001 0101(c) R5 = 0000 0000 (f) R3 = 0000 0000
R5 R4 R5 R5 DataInR6 R2 R4 1+ + R4 R4 ConstantR5 srR0 R3 R0 R0
Clock AA BA MB OF/EX:A OF/EX:B FS EX/WB:F EX/WB:DI MD RW DA R[DA]1 2 3 0 2 0 6 0 02 03 5 3 7 0 0 00 06 18 FF 0 1 1 4 0 0 1 07 00 01 0C 0 1 4 FF5 0 3 0 00 02 02 08 0 1 7 0C6 0 0 0 00 03 00 02 0 1 1 087 0 0 0 00 00 00 00 0 0 0 028 00 00 0C 00 Data 1 1 4 9 00 0 1 5 Data10 00The contents of registers that change for a given clock cycle are shown in the next clock cycle. Values are given in hexadecimal.
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 8 2000 by Prentice-Hall, Inc.
8-1.
8-2.
8-5.
0 1
S0 00
X2
Z1 = 0Z2 = 0
0
1
S1 01
X1
Z1 = 0Z2 = 1
0 1X2
0 1
S2 10
X1
Z1 = 1Z2 = 0
Inputs: X2,X1
A: 0 1 1 0 1 1B: 1 1 1 1 0 0C: 0 1 0 1 0 1
State: ST1 ST1 ST2 ST3 ST1 ST2 ST3Z: 0 0 1 1 0 0
0
1
STD
X
STE Z
10 X
0
1
STB
X
STC Z
0 1X
STA
0 1X
Reset
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2
Problem Solutions Chapter 8
8-8.
8-9.
8-12.
ST1(t + 1) = ST1A + ST2BC + ST3, ST2(t + 1) = ST1A, ST3(t + 1)= ST2(B + C),
Z = ST2B + ST3For the D flip-flops, DSTi = STi(t + 1) and STi = Q(STi).Reset initializes the flip-flops: ST1 = 1, ST2 = ST3 = 0.
DECODER
21
0123
20
422
STASTBSTCSTDSTE
DCR
DCR
DCR
XY2
Y1
Y0DY2
DY1
DY0
DY2DY1
DY0
Z
Y2 Y1 Y0
STA 0 0 0STB STCSTDSTE
0 0 10 1 00 1 11 0 0
State Assignment
Reset
100110 (38) 110101 ( 53) 100110 000000 100110 000000 100110100110 11111011110 (2014)
100110 110101 000000 Init PP 100110 Add 100110 After Add 0100110 After Shift 00100110 After Shift 100110 Add 10111110 After Add 010111110 After Shift 0010111110 After Shift 100110 Add 1100011110 After Add 01100011110 After Shift 100110 Add 11111011110 After Add 011111011110 After Shift
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3
Problem Solutions Chapter 8
8-17.CLKL L
LR
IN
AR BR
CR
MUX0 1S
Zero
Bit 15A(15:0) B(15:0)
LA LB
LC
R is a synchronous reset.
A(14:0)||0 B(14:0)||0
CLK
CLK
0 1G
ResetA
B
CLC
LB
LA
DCR
DCR
DCR
G
LA LB
LC
Reset
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4
Problem Solutions Chapter 8
8-20.library IEEE;use IEEE.std_logic_1164.all;entity asm_820 is
port (A, B, C, CLK, RESET: in STD_LOGIC;Z: out STD_LOGIC
);end asm_820;architecture asm_820_arch of asm_820 is
type state_type is (ST1, ST2, ST3);signal state, next_state : state_type;
beginstate_register: process (CLK, RESET)begin
if RESET='1' then --asynchronous RESET active Highstate
Problem Solutions Chapter 8
5
8-21. Errata: A, B, C should be ST1, ST2, ST3.
8-28.
8-32.
module asm_821 (CLK, RESET, A, B, C, Z) ;input CLK, RESET, A, B, C ;output Z ;reg [1:0] state, next_state;parameter ST1=2'b00, ST2=2'b01, ST3=2'b10, ST4=2'b11;reg Z;
always @(posedge CLK or posedge RESET)begin if (RESET) //asynchronous RESET active High state
6
Problem Solutions Chapter 8
8-39. Errata: Problem 8-39(d): C 0 should be C = 0.
8-47.
ADDR NXT MS MC IL PI PL TD TA TB MB FS MD RW MM MWa) 17 NXT NXA NLI NLP NLP DR SA SB Register F = A B FnUt WR NW
17 001 0 0 0 0 0 0 0 0 00101 0 1 0 0DR = 3, SA = 1, SB = 2b) CNT NLI NLP NLP DR SA Register F = lsr A FnUt WR NW
000 0 0 0 0 0 0 0 0 10100 0 1 0 0DR = 5, SA = 5c) 21 BNZ NXA NLI NLP NLP
21 111 0 0 0 0 0 0 0 0 00000 0 0 0 0
d) CNT NLI NLP NLP DR SA Register F = A FnUt WR NW 000 0 0 0 0 0 0 0 0 00000 1 1 0 0
DR = 6, SA = 6 Note: For R6 + 0, C = 0.
Pipeline Fill 3 cycles Execution Write-Backs 22 cycles Final Register Load 1 cycleTOTAL 26 cycles or 26 5 = 130 ns
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 9 2000 by Prentice-Hall, Inc.
9-2.
9-3.
9-6.
9-9.
9-11.
LD R1, ALD R2, BLD R3, CLD R4, DADD R3, R1, R3ADD R1, R1, R2MUL R2, R2, R4MUL R1, R3, R1SUB R1, R1, R2ST Y, R1
MOV T1, AADD T1, CMOV T2, BMUL T2, DMOV T3, AADD T3, BMUL T3, T1SUB T3, T2MOV Y, T3
LD AADD CST T1LD BMUL DST T2LD AADD BMUL T1SUB T2ST Y
a) b) c)
A B+( ) A C+( ) B D( ) AB CA+ BD +=A)
PUSH A PUSH B ADD PUSH A PUSH C ADDA B A+B A C A+C
A A+B A A+BA+B
MUL PUSH B PUSH D MUL SUB(A+B)x(A+C) B D BxD (A+B)x(A+C) - BxD
(A+B)x(A+C) B (A+B)x(A+C)(A+B)x(A+C)
B,C)
a) X = 200 208 1 = 9 b) X = 1111 1111 1111 0111
address field = 0
a) 3 Register Fields x 5 bits/Field = 15 bits. 32 bits - 15 bits = 17 bit. 217 = 131,072b) 256 = 8 bits. 2 Register Fields x 5 bits/Field = 10 bits. 32 bits - 8 bits - 10 bits = 14 Memory Bits
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2
Problem Solutions Chapter 9
9-13.
9-17.
9-20.
9-22.
9-24.
Read and Write of the FIFO work in the following manner:Write: Read:M WC[ ] DATA DST M RC[ ]
ASC ASC 1+ ASC ASC 1WC WC 1+ RC RC 1+
WC RC ASC
WR 1 0 1
WR 2 0 2
RD 2 1 1
RD 2 2 0
a) ADD R0, R4 b) , R0 = E8, C = 0ADC R1, R5 , R1 = 33, C = 1ADC R2, R6 , R2 = 40, C = 1ADC R3, R7 , R3 = 3D, C = 0
R0 8C 5C+R1 35 FE 0+ +R2 D7 68 1+ +R3 2B 11 1+ +
ResultOPP Register CSHR 0101 1101 1SHL 1011 1010 1
SHRA 1101 1101 1SHLA 1011 1010 1ROR 0101 1101 1 ROL 1011 1010 1
RORC 1101 1101 0 ROLC 1011 1010 1
Smallest Number = 0.5 2255
Largest Number = (1 226) 2+255
E e (e)2+8 15 1111+7 14 1110+6 13 1101+5 12 1100+4 11 1011+3 10 1010+2 9 1001+1 8 10000 7 01111 6 01102 5 01013 4 01004 3 00115 2 00106 1 00017 0 0000
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3
Problem Solutions Chapter 9
9-27.
9-29.
9-31.
9-34.
TEST R, (0001)16 (AND Immediate 1 with Register R)BNZ ADRS (Branch to ADRS if Z = 0)
a) A = 0011 0101 53B = 0011 0100 - 52
A B = 0000 0001 1b) C (borrow) = 0, Z = 0c) BH, BHE, BNE
PC SP TOSa) Initially 2000 2735 3250b) After Call 2147 2734 2002c) After Return 2002 2735 3250
External Interrupts:1) Hard Disk2) Mouse3) Keyboard4) Modem5) Printer
Internal Interrupts:1) Overflow2) Divide by zero3) Invalid opcode4) Memory stack overflow5) Protection violation
A software interrupt provides a way to call the interrupt routines normally associated with external or internal interrupts by inserting an instruction into the code. Privileged system calls for example must be executed through interrupts in order to switch from user to system mode. Procedure calls do not allow this change.
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1
Problem Solutions to Problems Marked With a * in Logic Computer Design Fundamentals, Ed. 2
C H A P T E R 1 0 2000 by Prentice-Hall, Inc.
10-1.
10-4.
10-10.
10-12.
a) , b)c) d) PC and SP are the value at the time of the instruction fetch.
PC M SP[ ] SP SP 1+ R6 0F0F16R2 M 255 R3+[ ] M 255 R3+[ ] R2, M SP[ ] PC 2+ SP SP 1 PC M M PC 2 00F016+ +[ ][ ],,
Register: R3, Register Indirect: 3, Immediate: 200210, Direct: 100010, Indexed: 100310, Indexed Indirect: 100310, Relative: 300310, Relative Indirect: 300310
Sym RT MC MM/LSMR/ PS
DSA/MS SB MA MB MD
FS/NA MO
a) SHRA0 0 0 0 09 0D 0 0 0 10 01 (Set MSTS) 0 0 0 09 0 0 0 0 00 F2 3 0 0 6 00 0 0 0 SHRA6 03 0 0 0 0F 0F 0 0 0 15 04 0 0 0 09 00 0 0 0 06 F5 3 0 1 6 00 0 0 0 SHRA3 06 2 1 4 0F 00 0 0 0 00 D
b) RLC0 0 0 0 09 0D 0 0 0 10 01 (Set MSTS) 0 0 0 09 0 0 0 0 00 F2 3 0 0 6 00 0 0 0 RLC6 03 0 0 0 0F 0F 0 0 0 1B D4 0 0 0 09 00 0 0 0 06 F5 3 0 1 6 00 0 0 0 RLC2 06 2 1 4 0F 00 0 0 0 00 D
c) BV0 3 0 0 4 00 0 0 0 BRA 01 2 1 5 00 00 0 0 0 00 0
R9 SDR9 R9z : CAR SHRA6DD DD 15( ) DD 15:1( )R9 R9 1z : CAR SHRA3DD DD CAR WB0 ROM( ),R9 SDR9 R9z : CAR RLC6DD DD 14:0( ) C C DD 15( ),R9 R9 1z : CAR RLC2DD DD CAR WB0 ROM( ),V: CAR BRACAR INT0(ROM)
MWB0 is the write back routine for the Multiply Operation.
Sym RT MC MM/LSMR/PS
DSA/MS SB MA MB MD
FS/NA MO
MUL0 0 0 0 09 10 0 2 0 10 01 0 0 0 0A 0F 0 0 0 10 02 0 0 0 0F 00 0 0 0 10 03 0 0 0 0D 0D 0 0 0 17 D4 3 0 1 3 00 0 0 0 MUL6 05 0 0 0 0F 0A 0 0 0 02 D6 0 0 0 0F 0F 0 0 0 17 D7 0 0 0 09 00 0 0 0 06 F8 3 0 0 6 00 0 0 0 MWB0 09 3 0 0 0 00 0 0 0 MUL3 0
R9 16R10 DDDD R0SD rorc SD( )C : CAR MUL6DD DD R10+DD rorc DD( )R9 R9 1z : CAR MWB0CAR MUL3
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2
Problem Solutions Chapter 10
10-17.
10-21.
10-23.
10-28.
Cycle 1: PC = 10FCycle 2: PC
-1 = 110, IR = 4418 2F0116Cycle 3: PC
-2 = 110, RW = 1, DA = 01, MD = 0, BS = 0, PS = X, MW = 0, FS = 02, SH = 01, MA = 0, MB = 1BUS A = 0000 001F, BUS B = 0000 2F01
Cycle 4: RW = 1, DA = 01, MD = 0, D0 = 0000 2F20, D1 = XXXX XXXX, D2 = 0000 00000Cycle 5: R1 = 0000 2F20
IF DOF EX WBIF DOF EX WB
IF DOF EX WB
MOV R7, R6SUB R8, R8, R6ADD R8, R8, R7
1 2 3 4 5 6
a) b)MOV R7, R6SUB R8, R8, R6
ADD R8, R8, R7NOP
SUB R7, R7, R6
AND R8, R7
NOPBNZ R7, 000FNOP
OR R5, R7
NOP
a) LD R1, INDEXLD R2, ADDRESSADD R3, R2, R1LD R4, R3SBI R4, R4, 1ST R3, R4
Time = 10 RISC Clock Cycles
b) IF = 2 CISC Clock Cycles1OF = 4 CISC Clock CyclesEX = 1 CISC Clock CyclesWB = 2 CISC Clock CyclesINT = 1 CISC Clock Cycles
Time = 10 CISC Clock CyclesTime = 30 RISC Clock Cycles
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EL SOLUCIONARIOCH11-1.1-4.1-7.1-9.1-11.1-15.1-17.1-20.1-23.1-25.
CH22-1.2-2.2-7.2-9.2-10.2-12.2-15.2-18.2-19.2-22.2-25.2-28.2-30.2-34.2-37.2-39.2-44.
CH33-2.3-3.3-6.3-11.3-13.3-15.3-20.3-25.3-29.3-35.3-38.3-41.3-45.3-49.3-52.3-55.3-58.3-62.3-66.3-69.3-72.3-76.3-80.
CH44-3.4-4.4-5.4-6.4-10.4-12.4-17.4-19.4-20.4-24.4-25.4-30.4-33.4-36.4-374-40.4-45.4-47.
CH55-3.5-6.5-8.5-10.5-17.5-21.5-24.5-26.5-29.5-33.5-35.5-39.
CH66-1.6-3.6-9.6-15.6-18.
CH77-1.7-3.7-6.7-9.7-11.7-14.7-19.7-22.7-24.7-26.7-28.7-31.
CH88-1.8-2.8-5.8-8.8-9.8-12.8-17.8-20.8-21.8-28.8-32.8-39.8-47.
CH99-2.9-3.9-6.9-9.9-11.9-13.9-17.9-20.9-22.9-24.9-27.9-29.9-31.9-34.
CH1010-1.10-4.10-10.10-12.10-17.10-21.10-23.10-28.