Top Banner
Chapter 2 – Combinational Logic and Computer Design Fundamentals Charles Kime & Thomas Kaminski ゥ 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Logic Circuits Part 2 – Circuit Optimization
49

Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Apr 03, 2018

Download

Documents

truonghanh
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Page 1: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Chapter 2 – CombinationalLogic Circuits

Part 2 – Circuit Optimization

Logic and Computer Design Fundamentals

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.(Hyperlinks are active in View Show mode)

Chapter 2 – CombinationalLogic Circuits

Part 2 – Circuit Optimization

Page 2: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Overview Part 1 – Gate Circuits and Boolean Equations

• Binary Logic and Gates• Boolean Algebra• Standard Forms

Part 2 – Circuit Optimization• Two-Level Optimization• Map Manipulation• Practical Optimization (Espresso) (optional)• Multi-Level Circuit Optimization

Part 3 – Additional Gates and Circuits• Other Gate Types• Exclusive-OR Operator and Gates• High-Impedance Outputs

Chapter 2 - Part 2 2

Part 1 – Gate Circuits and Boolean Equations• Binary Logic and Gates• Boolean Algebra• Standard Forms

Part 2 – Circuit Optimization• Two-Level Optimization• Map Manipulation• Practical Optimization (Espresso) (optional)• Multi-Level Circuit Optimization

Part 3 – Additional Gates and Circuits• Other Gate Types• Exclusive-OR Operator and Gates• High-Impedance Outputs

Page 3: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Boolean Function Optimization Minimizing the gate input (or literal) cost of a (a

set of) Boolean equation(s) reduces circuit cost. We choose gate input cost. Boolean Algebra and graphical techniques are

tools to minimize cost criteria values. Some important questions:

• When do we stop trying to reduce the cost?• Do we know when we have a minimum cost?

Treat optimum or near-optimum cost functionsfor two-level (SOP and POS) circuits first.

Introduce a graphical technique using Karnaughmaps (K-maps, for short)

Chapter 2 - Part 2 3

Minimizing the gate input (or literal) cost of a (aset of) Boolean equation(s) reduces circuit cost.

We choose gate input cost. Boolean Algebra and graphical techniques are

tools to minimize cost criteria values. Some important questions:

• When do we stop trying to reduce the cost?• Do we know when we have a minimum cost?

Treat optimum or near-optimum cost functionsfor two-level (SOP and POS) circuits first.

Introduce a graphical technique using Karnaughmaps (K-maps, for short)

Page 4: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Karnaugh Maps (K-map)

A K-map is a collection of squares• Each square represents a minterm• The collection of squares is a graphical representation

of a Boolean function• Adjacent squares differ in the value of one variable• Alternative algebraic expressions for the same function

are derived by recognizing patterns of squares The K-map can be viewed as

• A reorganized version of the truth table• A topologically-warped Venn diagram as used to

visualize sets in algebra of sets

Chapter 2 - Part 2 4

A K-map is a collection of squares• Each square represents a minterm• The collection of squares is a graphical representation

of a Boolean function• Adjacent squares differ in the value of one variable• Alternative algebraic expressions for the same function

are derived by recognizing patterns of squares The K-map can be viewed as

• A reorganized version of the truth table• A topologically-warped Venn diagram as used to

visualize sets in algebra of sets

Page 5: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Some Uses of K-Maps Provide a means for:

• Finding optimum or near optimum SOP and POS standard forms, and two-level AND/OR and OR/AND circuit

implementationsfor functions with small numbers ofvariables

• Visualizing concepts related to manipulatingBoolean expressions, and

• Demonstrating concepts used by computer-aided design programs to simplify largecircuits

Chapter 2 - Part 2 5

Provide a means for:• Finding optimum or near optimum

SOP and POS standard forms, and two-level AND/OR and OR/AND circuit

implementationsfor functions with small numbers ofvariables

• Visualizing concepts related to manipulatingBoolean expressions, and

• Demonstrating concepts used by computer-aided design programs to simplify largecircuits

Page 6: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Two Variable Maps A 2-variable Karnaugh Map:

• Note that minterm m0 andminterm m1 are “adjacent”and differ in the value of thevariable y

• Similarly, minterm m0 andminterm m2 differ in the x variable.

• Also, m1 and m3 differ in the x variable aswell.

• Finally, m2 and m3 differ in the value of thevariable y

y = 0 y = 1

x = 0 m0 = m1 =

x = 1 m2 = m3 =yx yx

yx yx

Chapter 2 - Part 2 6

A 2-variable Karnaugh Map:• Note that minterm m0 and

minterm m1 are “adjacent”and differ in the value of thevariable y

• Similarly, minterm m0 andminterm m2 differ in the x variable.

• Also, m1 and m3 differ in the x variable aswell.

• Finally, m2 and m3 differ in the value of thevariable y

x = 1 m2 = m3 =yx yx

Page 7: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

K-Map and Truth Tables The K-Map is just a different form of the truth table. Example – Two variable function:

• We choose a,b,c and d from the set {0,1} toimplement a particular function, F(x,y).

Function Table K-MapInput Function

Chapter 2 - Part 2 7

InputValues(x,y)

FunctionValueF(x,y)

0 0 a0 1 b1 0 c1 1 d

y = 0 y = 1x = 0 a bx = 1 c d

Page 8: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

K-Map Function Representation

Example: F(x,y) = x

For function F(x,y), the two adjacent cellscontaining 1’s can be combined using theMinimization Theorem:

F = x y = 0 y = 1

x = 0 0 0

x = 1 1 1

Chapter 2 - Part 2 8

Example: F(x,y) = x

For function F(x,y), the two adjacent cellscontaining 1’s can be combined using theMinimization Theorem:

xyxyx)y,x(F

Page 9: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

K-Map Function Representation

Example: G(x,y) = x + y

For G(x,y), two pairs of adjacent cells containing1’s can be combined using the MinimizationTheorem:

G = x+y y = 0 y = 1

x = 0 0 1

x = 1 1 1

Chapter 2 - Part 2 9

Example: G(x,y) = x + y

For G(x,y), two pairs of adjacent cells containing1’s can be combined using the MinimizationTheorem:

yxyxxyyxyx)y,x(GDuplicate xy

Page 10: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three Variable Maps

A three-variable K-map:

Where each minterm corresponds to the productterms:

Note that if the binary value for an index differs in onebit position, the minterms are adjacent on the K-Map

yz=00 yz=01 yz=11 yz=10

x=0 m0 m1 m3 m2

x=1 m4 m5 m7 m6

Chapter 2 - Part 2 10

A three-variable K-map:

Where each minterm corresponds to the productterms:

Note that if the binary value for an index differs in onebit position, the minterms are adjacent on the K-Map

yz=00 yz=01 yz=11 yz=10

x=0

x=1

zyx zyx zyx zyxzyx zyx zyx zyx

Page 11: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Alternative Map Labeling

Map use largely involves:• Entering values into the map, and• Reading off product terms from the

map. Alternate labelings are useful:

Chapter 2 - Part 2 11

Map use largely involves:• Entering values into the map, and• Reading off product terms from the

map. Alternate labelings are useful:

y

zx

10 2

4

3

5 67

xy

zz

yy z

z

10 2

4

3

5 67

x0

1

00 01 11 10

x

Page 12: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Example Functions By convention, we represent the minterms of F by a "1"

in the map and leave the minterms of blank Example:

Example:

Learn the locations of the 8indices based on the variableorder shown (x, most significantand z, least significant) on themap boundaries

y

x10 2

4

3

5 67

111

1(2,3,4,5)z)y,F(x, m

F

Chapter 2 - Part 2 12

By convention, we represent the minterms of F by a "1"in the map and leave the minterms of blank

Example:

Example:

Learn the locations of the 8indices based on the variableorder shown (x, most significantand z, least significant) on themap boundaries

x 5 611z

x

y10 2

4

3

5 671 111

z

(3,4,6,7)c)b,G(a, m

Page 13: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Combining Squares By combining squares, we reduce number of

literals in a product term, reducing the literal cost,thereby reducing the other two cost criteria

On a 3-variable K-Map:• One square represents a minterm with three

variables• Two adjacent squares represent a product term

with two variables• Four “adjacent” terms represent a product term

with one variable• Eight “adjacent” terms is the function of all ones (no

variables) = 1.Chapter 2 - Part 2 13

By combining squares, we reduce number ofliterals in a product term, reducing the literal cost,thereby reducing the other two cost criteria

On a 3-variable K-Map:• One square represents a minterm with three

variables• Two adjacent squares represent a product term

with two variables• Four “adjacent” terms represent a product term

with one variable• Eight “adjacent” terms is the function of all ones (no

variables) = 1.

Page 14: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Example: Combining Squares

Example: Let

Applying the Minimization Theorem threetimes:

Thus the four terms that form a 2 × 2 squarecorrespond to the term "y".

x

y10 2

4

3

5 671 111

z

m(2,3,6,7)F

Chapter 2 - Part 2 14

Example: Let

Applying the Minimization Theorem threetimes:

Thus the four terms that form a 2 × 2 squarecorrespond to the term "y".

yzyyz

zyxzyxzyxzyx)z,y,x(F

Page 15: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three-Variable Maps

Reduced literal product terms for SOP standardforms correspond to rectangles on K-mapscontaining cell counts that are powers of 2.

Rectangles of 2 cells represent 2 adjacentminterms; of 4 cells represent 4 minterms thatform a “pairwise adjacent” ring.

Rectangles can contain non-adjacent cells asillustrated by the “pairwise adjacent” ringabove.

Chapter 2 - Part 2 15

Reduced literal product terms for SOP standardforms correspond to rectangles on K-mapscontaining cell counts that are powers of 2.

Rectangles of 2 cells represent 2 adjacentminterms; of 4 cells represent 4 minterms thatform a “pairwise adjacent” ring.

Rectangles can contain non-adjacent cells asillustrated by the “pairwise adjacent” ringabove.

Page 16: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three-Variable Maps

Topological warps of 3-variable K-mapsthat show all adjacencies: Venn Diagram Cylinder

X40

Chapter 2 - Part 2 16

Y Z

X

1376 5

4

2

0

Page 17: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three-Variable Maps

Example Shapes of 2-cell Rectangles:

Read off the product terms for therectangles shown

y0 1 3 2

5 64 7

Chapter 2 - Part 2 17

Example Shapes of 2-cell Rectangles:

Read off the product terms for therectangles shown

5 64 7xz

Page 18: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three-Variable Maps

Example Shapes of 4-cell Rectangles:

Read off the product terms for therectangles shown

y0 1 3 2

5 64 7

Chapter 2 - Part 2 18

Example Shapes of 4-cell Rectangles:

Read off the product terms for therectangles shown

5 64 7xz

Page 19: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three Variable Maps

yz yx

K-Maps can be used to simplify Boolean functions bysystematic methods. Terms are selected to cover the“1s”in the map.

Example: Simplify )(1,2,3,5,7z)y,F(x, m

Chapter 2 - Part 2 19

z)y,F(x,

y

11

x

z

1 1

1

z

z

yx

Page 20: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Three-Variable Map Simplification Use a K-map to find an optimum SOP

equation for ,7)(0,1,2,4,6Z)Y,F(X, m

Chapter 2 - Part 2 20

Page 21: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Four Variable Maps

Map and location of minterms:

0 1 3 2

5 64 7

Y

Chapter 2 - Part 2 21

8 9 1011

12 13 1415

5 64 7

X

Z

WVariable Order

Page 22: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Four Variable Terms

Four variable maps can have rectanglescorresponding to:

• A single 1 = 4 variables, (i.e. Minterm)• Two 1s = 3 variables,• Four 1s = 2 variables• Eight 1s = 1 variable,• Sixteen 1s = zero variables (i.e.Constant "1")

Chapter 2 - Part 2 22

Four variable maps can have rectanglescorresponding to:

• A single 1 = 4 variables, (i.e. Minterm)• Two 1s = 3 variables,• Four 1s = 2 variables• Eight 1s = 1 variable,• Sixteen 1s = zero variables (i.e.Constant "1")

Page 23: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Four-Variable Maps

Example Shapes of Rectangles:

0 1 3 2

5 64 7

Y

Chapter 2 - Part 2 23

8 9 1011

12 13 1415

5 64 7

X

Z

W

Page 24: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Four-Variable Maps

Example Shapes of Rectangles:Y

0 1 3 2

5 64 7

Chapter 2 - Part 2 24

X

Z

8 9 1011

12 13 1415

5 64 7

W

Page 25: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Four-Variable Map Simplification )8,10,13,152,4,5,6,7,(0,Z)Y,X,F(W, m

Chapter 2 - Part 2 25

Page 26: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

3,14,15

Four-Variable Map Simplification )(3,4,5,7,9,1Z)Y,X,F(W, m

Chapter 2 - Part 2 26

Page 27: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

2.5 POS

Using the complement of the function asSOP , with the zeros Max terms, thencomplemented again.

Using the complement of the function asSOP , with the zeros Max terms, thencomplemented again.

Chapter 2 - Part 2 27

Page 28: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Systematic Simplification

A Prime Implicant is a product term obtained by combiningthe maximum possible number of adjacent squares in the mapinto a rectangle with the number of squares a power of 2.

A prime implicant is called an Essential Prime Implicant if it isthe only prime implicant that covers (includes) one or moreminterms.

Chapter 2 - Part 2 28

A Prime Implicant is a product term obtained by combiningthe maximum possible number of adjacent squares in the mapinto a rectangle with the number of squares a power of 2.

A prime implicant is called an Essential Prime Implicant if it isthe only prime implicant that covers (includes) one or moreminterms.

Page 29: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

DB1 11

Example of Prime Implicants

Find ALL Prime ImplicantsESSENTIAL Prime Implicants

CCD

DB1 1

C

1

Chapter 2 - Part 2 29CB

1 11 1

B

D

A

1 1

1 1

BD BD

Minterms covered by single prime implicant

1 11 1

B

D

A

1 1

1 1

AD

BA

Page 30: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Prime Implicant Practice

Find all prime implicants for:13,14,15),10,11,12,(0,2,3,8,9D)C,B,F(A, m

Chapter 2 - Part 2 30

Page 31: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Another Example

Find all prime implicants for:

• Hint: There are seven prime implicants!15),12,13,14,(0,2,3,4,7D)C,B,G(A, m

Chapter 2 - Part 2 31

Page 32: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Five Variable or More K-Maps For five variable problems, we use two adjacent K-maps.

It becomes harder to visualize adjacent minterms forselecting PIs. You can extend the problem to sixvariables by using four K-Maps.

YV = 0 V = 1

Y

Chapter 2 - Part 2 32

For five variable problems, we use two adjacent K-maps.It becomes harder to visualize adjacent minterms forselecting PIs. You can extend the problem to sixvariables by using four K-Maps.

X

Y

Z

W

X

Z

W

Y

Page 33: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Sometimes a function table or map contains entries forwhich it is known:• the input values for the minterm will never occur, or• The output value for the minterm is not used

In these cases, the output value need not be defined Instead, the output value is defined as a “don't care” By placing “don't cares” ( an “x” entry) in the function table

or map, the cost of the logic circuit may be lowered. Example 1: A logic function having the binary codes for the

BCD digits as its inputs. Only the codes for 0 through 9 areused. The six codes, 1010 through 1111 never occur, so theoutput values for these codes are “x” to represent “don’tcares.”

Don't Cares in K-Maps

Chapter 2 - Part 2 33

Sometimes a function table or map contains entries forwhich it is known:• the input values for the minterm will never occur, or• The output value for the minterm is not used

In these cases, the output value need not be defined Instead, the output value is defined as a “don't care” By placing “don't cares” ( an “x” entry) in the function table

or map, the cost of the logic circuit may be lowered. Example 1: A logic function having the binary codes for the

BCD digits as its inputs. Only the codes for 0 through 9 areused. The six codes, 1010 through 1111 never occur, so theoutput values for these codes are “x” to represent “don’tcares.”

Page 34: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Example: BCD The map below gives a function F1(w,x,y,z).With the don't cares used for the 6 non-BCD

combinations:F1 (w,x,y,z) = w + x z + x y This is much lower in cost than F2 where

the “don't cares” were treated as "0s."0 0 0 0

y

Chapter 2 - Part 2 34

The map below gives a function F1(w,x,y,z).With the don't cares used for the 6 non-BCD

combinations:F1 (w,x,y,z) = w + x z + x y This is much lower in cost than F2 where

the “don't cares” were treated as "0s."

z

w

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

1

11

1

X X X

X X

X

0 0 0 0

0x

yxwyxwzxwz)y,x,F2(w,

Page 35: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Product of Sums Example

Find the optimum POS solution:

• Hint: Use and complement it to get theresult.

,13,14,15)(3,9,11,12D)C,B,F(A, m (1,4,6)d

F

Chapter 2 - Part 2 35

Find the optimum POS solution:

• Hint: Use and complement it to get theresult.

Page 36: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Optimization Algorithm

Find all prime implicants. Include all essential prime implicants in the

solution Select a minimum cost set of non-essential

prime implicants to cover all minterms not yetcovered:• Obtaining an optimum solution: See Reading

Supplement - More on Optimization• Obtaining a good simplified solution: Use the

Selection Rule

Chapter 2 - Part 2 36

Find all prime implicants. Include all essential prime implicants in the

solution Select a minimum cost set of non-essential

prime implicants to cover all minterms not yetcovered:• Obtaining an optimum solution: See Reading

Supplement - More on Optimization• Obtaining a good simplified solution: Use the

Selection Rule

Page 37: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Prime Implicant Selection Rule

Minimize the overlap among primeimplicants as much as possible. Inparticular, in the final solution, makesure that each prime implicant selectedincludes at least one minterm notincluded in any other prime implicantselected.

Chapter 2 - Part 2 37

Minimize the overlap among primeimplicants as much as possible. Inparticular, in the final solution, makesure that each prime implicant selectedincludes at least one minterm notincluded in any other prime implicantselected.

Page 38: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Selection Rule Example

Simplify F(A, B, C, D) given on the K-map.

1

C

1 11

C

1

EssentialSelected

Chapter 2 - Part 2 38

1

1

1

1 1

1B

D

A

1

1

1

1

1 1

1B

D

A

1

Minterms covered by essential prime implicants

Page 39: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Selection Rule Example with Don't Cares

Simplify F(A, B, C, D) given on the K-map.Selected

x1

C

x1

CEssential

Chapter 2 - Part 2 39

Minterms covered by essential prime implicants

1

1

x

x x

xB

D

A

1

1 1

1

x

x x

xB

D

A

1

1

Page 40: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

2.7 Multiple-Level Optimization

Multiple-level circuits - circuits that arenot two-level (with or without inputand/or output inverters)

Multiple-level circuits can have reducedgate input cost compared to two-level(SOP and POS) circuits

Multiple-level optimization is performedby applying transformations to circuitsrepresented by equations whileevaluating cost

Chapter 2 - Part 2 40

Multiple-level circuits - circuits that arenot two-level (with or without inputand/or output inverters)

Multiple-level circuits can have reducedgate input cost compared to two-level(SOP and POS) circuits

Multiple-level optimization is performedby applying transformations to circuitsrepresented by equations whileevaluating cost

Page 41: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformations

Factoring - finding a factored form fromSOP or POS expression• Algebraic - No use of axioms specific to

Boolean algebra such as complements oridempotence

• Boolean - Uses axioms unique to Booleanalgebra

Decomposition - expression of a functionas a set of new functions

Chapter 2 - Part 2 41

Factoring - finding a factored form fromSOP or POS expression• Algebraic - No use of axioms specific to

Boolean algebra such as complements oridempotence

• Boolean - Uses axioms unique to Booleanalgebra

Decomposition - expression of a functionas a set of new functions

Page 42: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformations (continued)

Substitution of G into F - expressionfunction F as a function of G and some orall of its original variables

Elimination - Inverse of substitution Extraction - decomposition applied to

multiple functions simultaneously

Chapter 2 - Part 2 42

Substitution of G into F - expressionfunction F as a function of G and some orall of its original variables

Elimination - Inverse of substitution Extraction - decomposition applied to

multiple functions simultaneously

Page 43: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples

Algebraic FactoringF = + B + ABC + AC G = 16• Factoring:

F = ( + B ) + A (BC + C ) G = 16• Factoring again:

F = ( B + ) + AC (B + ) G = 12• Factoring again:

F = ( + AC) (B + ) G = 10

DCAA

A

C D

CC D D

Chapter 2 - Part 2 43

Algebraic FactoringF = + B + ABC + AC G = 16• Factoring:

F = ( + B ) + A (BC + C ) G = 16• Factoring again:

F = ( B + ) + AC (B + ) G = 12• Factoring again:

F = ( + AC) (B + ) G = 10AC D

A C D D

Page 44: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples

Decomposition• The terms B + and + AC can be defined

as new functions E and H respectively,decomposing F:

F = E H, E = B + , and H = + AC G = 10 This series of transformations has reduced G from

16 to 10, a substantial savings. The resultingcircuit has three levels plus input inverters.

ACD

D AC

Chapter 2 - Part 2 44

Decomposition• The terms B + and + AC can be defined

as new functions E and H respectively,decomposing F:

F = E H, E = B + , and H = + AC G = 10 This series of transformations has reduced G from

16 to 10, a substantial savings. The resultingcircuit has three levels plus input inverters.

ACD

Page 45: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples

Substitution of E into F• Returning to F just before the final factoring step:

F = ( B + ) + AC (B + ) G = 12• Defining E = B + , and substituting in F:

F = E + ACE G = 10• This substitution has resulted in the same cost as the

decomposition

A C DD

A CD

Chapter 2 - Part 2 45

Substitution of E into F• Returning to F just before the final factoring step:

F = ( B + ) + AC (B + ) G = 12• Defining E = B + , and substituting in F:

F = E + ACE G = 10• This substitution has resulted in the same cost as the

decomposition

A C

Page 46: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples

Elimination• Beginning with a new set of functions:

X = B + CY = A + BZ = X + C Y G = 10• Eliminating X and Y from Z:

Z = (B + C) + C (A + B) G = 10• “Flattening” (Converting to SOP expression):

Z = B + C + AC + BC G = 12• This has increased the cost, but has provided an new

SOP expression for two-level optimization.

A

Chapter 2 - Part 2 46

Elimination• Beginning with a new set of functions:

X = B + CY = A + BZ = X + C Y G = 10• Eliminating X and Y from Z:

Z = (B + C) + C (A + B) G = 10• “Flattening” (Converting to SOP expression):

Z = B + C + AC + BC G = 12• This has increased the cost, but has provided an new

SOP expression for two-level optimization.

A

A

A

A

Page 47: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples

Two-level Optimization• The result of 2-level optimization is:

Z = B + C G = 4 This example illustrates that:

• Optimization can begin with any set of equations,not just with minterms or a truth table

• Increasing gate input count G temporarily during aseries of transformations can result in a finalsolution with a smaller G

A

Chapter 2 - Part 2 47

Two-level Optimization• The result of 2-level optimization is:

Z = B + C G = 4 This example illustrates that:

• Optimization can begin with any set of equations,not just with minterms or a truth table

• Increasing gate input count G temporarily during aseries of transformations can result in a finalsolution with a smaller G

Page 48: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Transformation Examples Extraction

• Beginning with two functions:E = + BDH = C + BCD G = 16• Finding a common factor and defining it as a

function:F = + BD• We perform extraction by expressing E and H as

the three functions:F = + BD, E = F, H = CF G = 10• The reduced cost G results from the sharing of logic

between the two output functions

BA AB

DD

Chapter 2 - Part 2 48

Extraction• Beginning with two functions:

E = + BDH = C + BCD G = 16• Finding a common factor and defining it as a

function:F = + BD• We perform extraction by expressing E and H as

the three functions:F = + BD, E = F, H = CF G = 10• The reduced cost G results from the sharing of logic

between the two output functions

A

BD

BD

Page 49: Logic and Computer Design Fundamentals - Prince …info.psu.edu.sa/psu/cis/kalmustafa/CS_151/Lecture Sildes...Overview ð Part 1 Gate Circuits and Boolean Equations "Binary Logic and

Terms of Use All (or portions) of this material © 2008 by Pearson

Education, Inc. Permission is given to incorporate this material or

adaptations thereof into classroom presentations andhandouts to instructors in courses adopting the latestedition of Logic and Computer Design Fundamentalsas the course textbook.

These materials or adaptations thereof are not to besold or otherwise offered for consideration.

This Terms of Use slide or page is to be included withinthe original materials or any adaptations thereof.

Chapter 2 - Part 2 49

All (or portions) of this material © 2008 by PearsonEducation, Inc.

Permission is given to incorporate this material oradaptations thereof into classroom presentations andhandouts to instructors in courses adopting the latestedition of Logic and Computer Design Fundamentalsas the course textbook.

These materials or adaptations thereof are not to besold or otherwise offered for consideration.

This Terms of Use slide or page is to be included withinthe original materials or any adaptations thereof.