Rev. 0.1 12/13 Copyright © 2013 by Silicon Laboratories AN803 AN803 L OCK AND S ETTLING T IME C ONSIDERATIONS FOR Si5324/27/ 69/74 A NY -F REQUENCY J ITTER A TTENUATING C LOCK IC S 1. Introduction As outlined in the Product Bulletin*, issued in January 2013, Silicon Labs has made a change to the Si5324/27/69/ 74 family to improve the frequency locking time. However, in some instances, the time required to clear the Loss- of-Lock (LOL) alarm may be longer in some operating configurations on the new devices. The purpose of this application note is to define the differences between LOL Clear Time and frequency locking time, how they may have been affected by the change, and how to optimize the LOL time in relation to the frequency settling time. 2. Lock Indication vs. Frequency Settling Time A phase lock loop (PLL) is a feedback system that strives to set the output frequency equal to that of the input frequency, as determined by the divide-by ratio. There are several states that a PLL can be in: unlocked, an in-between state (such as acquiring lock state), and finally a locked state. Also various terms can be used to describe the time for a PLL to acquire a locked status, such as acquisition time, lock time and settling time. There are also several ways to measure lock, phase vs. frequency, plus the degree of resolution it is measured to, eg., to within 5 ppm or 5 ppb of the final value. All of these variations impact the final result. There are conditions in which a PLL is unquestionably locked. There are also conditions which a PLL is unquestionably unlocked. However, there are several other states, such as acquiring lock, tracking an input change, locked but wandering, locked but unstable, etc. Whereas a lock condition can have various degrees of being locked, such as an analog function, the Loss of Lock output is digital: the PLL is locked or the PLL is unlocked. The Si53xx family LOL algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. A retriggerable one-shot is set each time a potential phase cycle slip condition is detected. If no potential phase cycle slip occurs for the retrigger time, the LOL output is set low, indicating the PLL is in lock. 3. Product Update’s Effect on PLL Parametrics During the acquisition phase a lock detect circuit can oscillate between reporting a locked and unlocked condition as the PLL transitions from slightly high to slightly low in frequency, as shown in Figure 1. Silicon Labs has recently introduced a modification to stabilize LOL by forcing it to a logic high state, which will result in a decrease in frequency settling time. This improvement is required in low loop BW applications only, which include the Si5324, Si5327, Si5369, and Si5374. Figure 2 shows the improved LOL condition due to the modification. Note: * Product Bulletin 1301281: Si5324/27/69/74 Improved Lock Time, issued on 28-Jan-2013, is available and automati- cally distributed to registered users of www.silabs.com.
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Rev. 0.1 12/13 Copyright © 2013 by Silicon Laboratories AN803
AN803
LOCK AND SETTLING TIME CONSIDERATIONS FOR Si5324/27/69/74 ANY-FREQUENCY JITTER ATTENUATING CLOCK ICS
1. Introduction
As outlined in the Product Bulletin*, issued in January 2013, Silicon Labs has made a change to the Si5324/27/69/74 family to improve the frequency locking time. However, in some instances, the time required to clear the Loss-of-Lock (LOL) alarm may be longer in some operating configurations on the new devices. The purpose of thisapplication note is to define the differences between LOL Clear Time and frequency locking time, how they mayhave been affected by the change, and how to optimize the LOL time in relation to the frequency settling time.
2. Lock Indication vs. Frequency Settling Time
A phase lock loop (PLL) is a feedback system that strives to set the output frequency equal to that of the inputfrequency, as determined by the divide-by ratio.
There are several states that a PLL can be in: unlocked, an in-between state (such as acquiring lock state), andfinally a locked state. Also various terms can be used to describe the time for a PLL to acquire a locked status,such as acquisition time, lock time and settling time. There are also several ways to measure lock, phase vs.frequency, plus the degree of resolution it is measured to, eg., to within 5 ppm or 5 ppb of the final value. All ofthese variations impact the final result.
There are conditions in which a PLL is unquestionably locked. There are also conditions which a PLL isunquestionably unlocked. However, there are several other states, such as acquiring lock, tracking an inputchange, locked but wandering, locked but unstable, etc. Whereas a lock condition can have various degrees ofbeing locked, such as an analog function, the Loss of Lock output is digital: the PLL is locked or the PLL isunlocked. The Si53xx family LOL algorithm works by continuously monitoring the phase of the input clock inrelation to the phase of the feedback clock. A retriggerable one-shot is set each time a potential phase cycle slipcondition is detected. If no potential phase cycle slip occurs for the retrigger time, the LOL output is set low,indicating the PLL is in lock.
3. Product Update’s Effect on PLL Parametrics
During the acquisition phase a lock detect circuit can oscillate between reporting a locked and unlocked conditionas the PLL transitions from slightly high to slightly low in frequency, as shown in Figure 1. Silicon Labs has recentlyintroduced a modification to stabilize LOL by forcing it to a logic high state, which will result in a decrease infrequency settling time. This improvement is required in low loop BW applications only, which include the Si5324,Si5327, Si5369, and Si5374. Figure 2 shows the improved LOL condition due to the modification.
Note: * Product Bulletin 1301281: Si5324/27/69/74 Improved Lock Time, issued on 28-Jan-2013, is available and automati-cally distributed to registered users of www.silabs.com.
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Figure 1. Extended LOL, Low Loop BW
Figure 2. Improved LOL Time
Lock time would normally be much longer for a low loop BW setting, such as 4 Hz, and on the order of severalseconds to minutes. However, this length is intolerable in some applications, which require a minimal lock time.The Si53xx family includes a fast lock feature which helps provide a fast lock time for low loop BW applications.The Fastlock feature sets the PLL loop BW to a maximum value during the initial acquisition cycle, or an ICALcommand, and reverts back to the low loop BW once the LOL is released. The higher loop BW, as set by the fastlock feature, will also be active once the Si5324/69/74 has entered Digital Hold (provided that Digital Hold Valid isvalid) to aid relocking times, and once again it reverts back to a low loop BW when the PLL relocks.
As a result, lock times actually decreased, as seen when comparing Figure 1 and Figure 2. However, in someapplications, there will be an increase in LOL Clear Time which is unwarranted (see Figure 3 and Figure 4). Thereis an easy modification that can be used to revert back to pre-modification performance.
4. Impact of System Level Changes
At the system level, LOL can be used to determine a locked condition before a system is allowed to pass traffic. Forsome frequency plans, the LOL time has decreased, as shown in Figure 1 and Figure 2, which should not causeany issues. For the frequency plans with an increased LOL time, passing diagnostic testing will require a longerperiod of time.
An example of the LOL measurement is shown in Figure 3 and Figure 4. Figure 3 shows the LOL time for anSi5324 in a 19.440 MHz to 155.520 MHz application with the lowest loop BW setting before the modification.Figure 4 shows the LOL time after the modification. We see an increase in LOL time from 3.8 seconds to13 seconds. However, when the frequency settling time is measured, as in Figure 5, we see the performance hasimproved from 2.5 seconds to under 1 second.The overall or real lock time performance has improved. In thisexample, it is safe to make adjustments that revert LOL times back to the pre-modification performance.
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Figure 3. LOL Time Before Modification
Figure 4. LOL Time After Modification
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Figure 5. Modification Frequency Improvement
‐25
‐20
‐15
‐10
‐5
0
5
10
15
20
25
0 1 2 3 4 5ppm
Time in Seconds
Frequency Settling Time
Series1
Series2
Pre‐Modification
Post Modification
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5. Optimizing LOL Clear Time Using the LOCKT Register Setting
The LOL active high state time can be modified by making adjustments to the LOCKT function. Decreasing theLOCKT time will also decrease the LOL active high time, however it does not change the frequency settling time. Inthe above example, LOCKT was modified from 53 ms to 13 ms and LOCKT was restored back to 3.7 seconds asshown in Figure 7. If LOCKT is set too low in value then it can cause an early release of fast lock resulting inextended lock times. Table 1 show the LOL time versus LOCKT. In this example, the frequency settling time wasabout 1 second and modifying the LOCKT to 6.6 ms would be a conservative setting. Note these figures areprovided for informational purposes only and actual results will differ depending on the frequency plan.
Table 1. LOL Time vs. LOCKT Setting, 19.440 to 155.520 MHz
LOCKT Register SettingRegister 19[2:0]
LOCKT Setting LOL Time(in seconds)
Frequency Settling Time
(in seconds)
0x0 100 ms 25.2 1
0x1 53.3 ms 12.9 1
0x2 26.5 ms 6.3 1
0x3 13.3 ms 3.7 1
0x4 6.6 ms 2.2 1
0x5 3.3 ms 1.4 1
0x6 1.66 ms 1.0 1
0x7 0.83 ms 0.83 1
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6. Modifying LOCKT
LOCKT can easily be modified by using DSLLsim. After starting up the latest revision of DSPLLsim, select “EnterFile”, select “Read from register map test file” and enter the current frequency plan, select the “Input Clocks” taband modify LOCKT as shown in Figure 6. Resave the register file. LOCKT can also be modified by changing thevalues in register 19 [2:0]. See the appropriate data sheet for more details.
Figure 6. LOCKT Modification Location, Select “Input Clocks” Tab in DSPLLsim
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Figure 7. LOL Time is Restored Back to Less than 4 Seconds with a LOCKT Modification
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7. Verifying the NVM Revision
In some cases, it will be helpful to query the Si53xx to determine which NVM version is loaded. The purpose of thisquery is to identify the device’s vintage and from this the appropriate LOCKT setting can be selected for use in theregister plan. Register 185 contains which NVM revision is used and this applies for all Si5324s, Si5374s, Si5368sand Si5374s. Table 2 contains the NVM revision pre- and post-Product Bulletin 1301281.
Contact applications engineering with a detailed frequency plan if there are any concerns with the LOLimprovement and for recommendations as to LOCKT modifications.
Table 2. NVM Revision Pre- and Post-Modification, Register 185
Device NVM before 5/1/2013 as well as
three new part numbers1
Si5324E-C-GMSi5374C-A-BLSi5374C-A-GL
NVM on or after 5/1/2013
Si5324, Register 185 13h 16h
Si5327, Register 185 13h 16h
Si5369, Register 185 13h 16h
Si5374, Register 185 14h 16h
Notes:1. These three specific new part numbers were created for applications which require pre-modification
performance.
DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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