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LME49720
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LME49720
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Note: 1% metal film resistors, 5% polypropylene capacitors
• Changed RθJA values for D and P packages from 145 °C/W to 107.9 °C/W (D) and from 102 °C/W to 72.9 °C/W (P)in the Thermal Information table............................................................................................................................................. 4
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.(2) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For enusred
specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability andspecifications.
(4) Amplifier output connected to GND, any number of amplifiers within a package.
7 Specifications
7.1 Absolute Maximum Ratingssee (1) (2) (3)
MIN MAX UNITPower Supply Voltage (VS = V+ – V–) 36 VInput Voltage (V–) – 0.7V (V+) + 0.7 VOutput Short Circuit (4) ContinuousPower Dissipation Internally LimitedJunction Temperature 150 °CTemperature Range TMIN ≤ TA ≤ TMAX –40 85 °CSupply Voltage Range ±2.5V ≤ VS ≤
± 17V V
Storage Temperature −65 150 °C
(1) Human body model, 100pF discharged through a 1.5kΩ resistor.
7.2 ESD RatingsVALUE UNIT
V(ESD) Electrostatic dischargeHuman-body model (HBM) (1) All pins 2000
VMachine Model (MM), per EIAJ IC-121-1981Application and Implementation
Pins 1, 4, 7 and 8 200Pins 2, 3, 5 and 6 100
7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNITV+,V– Supply voltage ±2.5 ±17 VTA Operating free-air temperature –40 85 °CTJ Operating junction temperature –40 150 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.
(2) Thermal performance of a TO-99 package will depend strongly on mounting condition and there is no standard mounting configurationon a JEDEC PCB for that package type.
(1) Tested limits are ensured to AOQL (Average Outgoing Quality Level).(2) Typical specifications are specified at +25ºC and represent the most likely parametric norm.(3) PSRR is measured as follows: VOS is measured at two supply voltages, ±5V and ±15V. PSRR = | 20log(ΔVOS/ΔVS) |.
7.5 Electrical CharacteristicsThe following specifications apply for VS = ±15V, RL = 2kΩ, fIN = 1kHz, and TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
All parameters are measured according to the conditions described in the Specifications section.
8.1 Distortion MeasurementsThe vanishingly low residual distortion produced by LME49720 is below the capabilities of all commerciallyavailable equipment. This makes distortion measurements just slightly more difficult than simply connecting adistortion meter to the amplifier’s inputs and outputs. The solution, however, is quite simple: an additionalresistor. Adding this resistor extends the resolution of the distortion measurement equipment.
The LME49720’s low residual distortion is an input referred internal error. As shown in Figure 109, adding the10Ω resistor connected between the amplifier’s inverting and non-inverting inputs changes the amplifier’s noisegain. The result is that the error signal (distortion) is amplified by a factor of 101. Although the amplifier’s closed-loop gain is unaltered, the feedback available to correct distortion errors is reduced by 101, which means thatmeasurement resolution increases by 101. To ensure minimum effects on distortion measurements, keep thevalue of R1 low as shown in Figure 109.
This technique is verified by duplicating the measurements with high closed loop gain and/or making themeasurements at high frequencies. Doing so produces distortion components that are within the measurementequipment’s capabilities. This datasheet’s THD+N and IMD values were generated using the above describedcircuit connected to an Audio Precision System Two Cascade.
Complete shielding is required to prevent induced pick up from external sources. Always check with oscilloscope forpower line noise.Total Gain: 115 dB @F = 1 kHzInput Referred Noise Voltage: En = V0/560,000 (V)
9.1 OverviewThe LME49720 audio operational amplifier delivers superior audio signal amplification for outstanding audioperformance.
To ensure that the most challenging loads are driven without compromise, the LME49720 has a high slew rate of±20V/μs and an output current capability of ±26mA. Further, dynamic range is maximized by an output stage thatdrives 2kΩ loads to within 1V of either power supply voltage and to within 1.4V when driving 600Ω loads.
The LME49720's outstanding CMRR (120dB), PSRR (120dB), and VOS (0.1mV) give the amplifier excellentoperational amplifier DC performance.
The LME49720 has a wide supply range of ±2.5V to ±17V. Over this supply range the LME49720’s input circuitrymaintains excellent common-mode and power supply rejection, as well as maintaining its low input bias current.The LME49720 is unity gain stable. This Audio Operational Amplifier achieves outstanding AC performance whiledriving complex loads with values as high as 100pF.
The LME49720 is available in 8–lead narrow body SOIC, 8–lead PDIP, and 8–lead TO-99. Demonstrationboards are available for each package.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Capacitive LoadThe LME49720 is a high speed op amp with excellent phase margin and stability. Capacitive loads up to 100pFwill cause little change in the phase characteristics of the amplifiers and are therefore allowable.
Capacitive loads greater than 100pF must be isolated from the output. The most straightforward way to do this isto put a resistor in series with the output. This resistor will also prevent excess power dissipation if the output isaccidentally shorted.
9.3.2 Balance Cable DriverWith high peak-to-peak differential output voltage and plenty of low distortion drive current, the LME49720 makesan excellent balanced cable driver. Combining the single-to-differential configuration with a balanced cable driverresults in a high performance single-ended input to balanced line driver solution.
Although the LME49720 can drive capacitive loads up to 100pF, cable loads exceeding 100pF can causeinstability. For such applications, series resistors are needed on the outputs before the capacitive load.
9.4 Device Functional ModesThis device does not have operation mode.
10 Application and Implementation
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
10.1 Application InformationThese typical connection diagrams highlight the required external components and system level connections forproper operation of the device. Any design variation can be supported by TI through schematic and layoutreviews. Visit e2e.ti.com for design assistance and join the audio amplifier discussion forum for additionalinformation
10.2 Typical Applications
10.2.1 Single Ended Converter
VO = V1–V2
Figure 111. Balanced To Single Ended Converter
10.2.1.1 Design RequirementsFor this design example, use the parameters listed in Table 1.
Temperature and applied DC voltage influence the actual capacitance of high-K materials. Table 2 shows therelationship between the different types of high-K materials and their associated tolerances, temperaturecoefficients, and temperature ranges. Notice that a capacitor made with X5R material can lose up to 15% of itscapacitance within its working temperature range.
Select high-K ceramic capacitors according to the following rules:1. Use capacitors made of materials with temperature coefficients of X5R, X7R, or better.2. Use capacitors with DC voltage ratings of at least twice the application voltage.3. Choose a capacitance value at least twice the nominal value calculated for the application.
Multiply the nominal value by a factor of 2 for safety. If a 10-µF capacitor is required, use 20µF.
The preceding rules and recommendations apply to capacitors used in connection with this device. TheLME49720 cannot meet its performance specifications if the rules and recommendations are not followed.
Table 2. Typical Tolerance and Temperature Coefficient of Capacitance by MaterialMaterial COG/NPO X7R X5R
Temperature Range, ºC –55/125ºC –55/125ºC –30/85 ºC
10.2.1.3 Application CurvesFor application curves, see the figures listed in Table 3.
Table 3. Table of GraphsDESCRIPTION FIGURE NUMBERTHD+N vs Output Power See Figure 1THD+N vs Frequency See Figure 13Crosstalk vs Frequency See Figure 36PSRR vs Frequency See Figure 58
11 Power Supply RecommendationsThe LME49720 is designed to operate a power supply from ±2.5V to ±17V. Therefore, the output voltage rangeof the power supply must be within this range. The current capability of upper power must not exceed themaximum current limit of the power switch.
11.1 Power Supply Decoupling CapacitorsThe LME49720 requires adequate power supply decoupling to ensure a low total harmonic distortion (THD).Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, within 2 mm of the V+ and V-pins. This choice of capacitor and placement helps with higher frequency transients, spikes, or digital hash on theline. In addition to the 0.1 µF ceramic capacitor, it is recommended to place a 2.2 µF to 10 µF capacitor on theV+ and V- pins. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply,thus helping to prevent any droop in the supply voltage.
12.1.1 Component PlacementPlace all the external components close to the device. Placing the decoupling capacitors as close as possible tothe device is important for low total harmonic distortion (THD). Any resistance or inductance in the trace betweenthe device and the capacitor can cause a loss in efficiency.
13.2 ココミミュュニニテティィ・・リリソソーーススThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
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LME49720MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L49720MA
LME49720NA/NOPB ACTIVE PDIP P 8 40 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LME49720NA
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.
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.010 [0.25] C A B
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PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
.0028 MAX[0.07]ALL AROUND
.0028 MIN[0.07]ALL AROUND
(.213)[5.4]
6X (.050 )[1.27]
8X (.061 )[1.55]
8X (.024)[0.6]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILS
EXPOSEDMETAL
OPENINGSOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASKDEFINED
EXPOSEDMETAL
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEEDETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )[1.55]
8X (.024)[0.6]
6X (.050 )[1.27]
(.213)[5.4]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
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