EE213 L05 Wires.1 Pingqiang, ShanghaiTech, 2017 EE213 Digital Integrated Circuits II Lecture 05: Wires ShanghaiTech University School of Information Science and Technology Prof. Pingqiang Zhou http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr17/Digital-IC-2.html
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EE213 L05 Wires.1 Pingqiang, ShanghaiTech, 2017
EE213Digital Integrated Circuits II
Lecture 05: Wires
ShanghaiTech UniversitySchool of Information Science and Technology
(a) Finger-shaped network (b) Network with multiple supply pins
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Resistance and the Power Distribution Problem
Source: Cadence
• Requires fast and accurate peak current prediction• Heavily influenced by packaging technology
Before After
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INTERCONNECT
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Capacitance of Wire Interconnect
Fan-Out
Simplified Model
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Wire Capacitance: Parallel Plate
WLt
Cdi
dipp
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Wire Capacitance: Fringe Capacitance
Cwire Cpp +Cfringe ditdiWL+ 2di
log(tdi / H )L
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Fringing vs. Parallel Plate
(from [Bakoglu89])
2dilog(tdi /H )
L
ditdiWL
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Interwire Capacitance
interwire
fringe
W W
W
H
H
H
tdi
tdi
tdi
Cwire = Cpp + Cfringe + Cinterwire
= (di/tdi)WL + (2di)L/log(tdi/H) + (di/tdi)HL
pppp
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Wiring Capacitances
Field Active Poly Al1 Al2 Al3 Al4
Poly 88
54
Al1 30 41 57
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 38
12 12 12 14 19 27 52
fringe in aF/m
par. plate in aF/m2
Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/m for minimally-spaced wires
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Impact of Interwire Capacitance
From: Bakoglu89
Ctotal = Cinterwire + Cground
+ Cparallel-plate
At smaller feature size, the interwire cap.
dominates!
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Crosstalk
A capacitor does not like to change its voltage instantaneously.
A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends
to switch too.
Called capacitive coupling or crosstalk.
Crosstalk effects Noise on non-switching wires
Increased delay on switching wires
A BCadjCgnd Cgnd
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Crosstalk Delay
Effective Cadj depends on behavior of neighbors
A BCadjCgnd Cgnd
B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2
R. Ho, K. W. Mai and M. A. Horowitz, "The future of wires," in Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, Apr 2001.
Cc
Delay and power increase
Miller effect
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Crosstalk Noise
Crosstalk causes noise on nonswitching wires
If victim is floating: model as capacitive voltage divider
A BCadjCgnd Cgnd
Cadj
Cgnd-v
Aggressor
Victim
DVaggressor
DVvictim
adj
gnd-v adaggresvictim o
js r
CV
C CV D
+D
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Driven Victims
Usually victim is driven by a gate that fights noise Noise depends on relative resistances
If sizes are same, Raggressor = 2-4 x Rvictim
A BCadjCgnd Cgnd
R. Ho, K. W. Mai and M. A. Horowitz, "The future of wires," in Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, Apr 2001.
Cadj
Cgnd-v
Aggressor
Victim
DVaggressor
DVvictim
Raggressor
Rvictim
Cgnd-a
DVvictim Cadj
Cgnd-v +Cadj
1
1+ kDVaggressor
aggressor gnd-aggresso a adj
gndvict -im victim j
r
v ad
C C
CR
Rk
C +
+
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Coupling Waveforms
Simulated coupling for Cadj = Cgnd
Aggressor (driven by a unit inverter)
Victim (undriven): 50%
Victim (half size driver): 16%
Victim (equal size driver): 8%
Victim (double size driver): 4%
t (ps)
0 200 400 600 800 1000 1200 1400 1800 2000
0
0.3
0.6
0.9
1.2
1.5
1.8
DVvictim
Cadj
Cgnd-v
Aggressor
Victim
DVaggressor
DVvictim
Raggressor
Rvictim
Cgnd-a
DVvictim Cadj
Cgnd-v +Cadj
1
1+ kDVaggressor
aggressor gnd-aggresso a adj
gndvict -im victim j
r
v ad
C C
CR
Rk
C +
+
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Noise Implications
So what if we have noise? If the noise is less than the noise margin, nothing happens
Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes
- But glitches cause extra delay
- Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can produce the wrong answer
Crosstalk Reduction Techniques?
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Wire Spacing
Spacing
Extra space
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Wire Spacing
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Power Supply Shielding
Add VDD and VSS “shields” between signal wires
Power supply lines isolate the wires and eliminate crosstalk effects caused by adjacent wire transitions
GND
GND
Shieldingwire
Substrate(GND)
Shieldinglayer
VDD
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Buffer Insertion
Buffer insertion is a traditional timing technique that can aid in noise tolerance as well Reduces the parallel length of interconnects and redistributes the
capacitive coupling between two newly created wires