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LINEARITY ENHANCEMENT TECHNIQUES FOR

WIDEBAND RF FRONT-END RECEIVERS

by

Kihwa Choi

A dissertation submitted in partial fulfillment of the

requirements

for the degree of

Doctor of Philosophy

in

Electrical and Computer Engineering

Carnegie Mellon University

Pittsburgh, PennsylvaniaJune 2009


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Keywords: RF front-end, receiver, low-noise amplifier, active balun, folded mixer, gain,

linearity, noise figure, scattering parameters, intermodulation distortion, second-order input

intercept point, third-order input intercept point, linearity enhancement techniques, Volterra

series, Taylor series, Volterra kernel, frequency-dependent nonlinearity coefficients,

derivative superposition, wideband derivative superposition, self-biasing current reuse

technique, DC offset, impedance matching network.

Copyright

Kihwa Choi, 2009

All rights reserved.


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To my wife, daughter, and son for their patience and support


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ACKNOWLEDGEMENTS

This thesis would have been impossible without support of many people. I would like

to express my sincere gratitude to them, though their invaluable support deserves much

more than this short note of appreciation.

It is difficult to overstate my gratitude to my advisor Prof. Tamal Mukherjee and

Jeyanandh Paramesh. Their enthusiastic and inspirational leadership in research helped

me stay on the right track from the moment I changed research topic. Their extensive

technical support was definitely far beyond their duty as a thesis advisor. Until then, Prof.

C. Patrick Yue guided me to learn how to do research on RF circuit design. Also, I would

like to express my gratitude to Prof. L. Richard Carley and Prof. Ramesh Harjani. It was

great honor to have them as my thesis committee. Their constructive suggestions made

the thesis sound great in many aspects and made the missing essential parts in the thesis

filled. I am grateful to my company, Samsung Electronics, for providing me this

wonderful chance to do research so that I can catch up with the latest research trend. I

would like to really express my gratitude to my parents, brothers, and sister for their

faithful support throughout my life. Also, I would like to thank all my colleague students,

Abhishek Jajoo, Cheng-Yuan Wen, Gokce Keskin, Jaewon Choi, Jon Proesel, Sandipan

Kundu, Shadi Saberi Ghouchani, Umut Arslan, and the other graduate students. Without

them, my life and research at Carnegie Mellon University might have been monotonous

and dry.

Finally, I would like to thank my wife, HoKyoung Kim, for her patience and support,

including dedication to our two sweethearts. I dedicate this thesis to her with my love.


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ABSTRACT

A multi-standard RF front-end wideband receiver should achieve not only wide

bandwidth to support wideband operation, but also high linearity to minimize sensitivity

degradation due to in-band intermodulation and cross modulation distortion due to co-

existence of strong interference signals. This dissertation addresses both wideband circuit

designs and linearity enhancement techniques.

First of all, wideband circuit designs are described for RF front-end receivers

including low-noise amplifier (LNA), active balun, and down-conversion mixer. The RF

front-end receiver is designed for wideband operation, while accommodating low voltage

and low power operation. Small supply voltage, needed for scaled CMOS where

transistors can operate at multi-GHz frequencies, however, degrades linearity of the RF

front-end receiver. The degradation of the second-order distortion is minimized by using

fully differential topology in the mixer, but there is still the second-order distortion due to

process variation and asymmetric circuit operation, resulting in DC offsets from different

mechanisms. The DC offsets in a fully differential circuit are segmented into different

categories depending contribution mechanisms. The relationship between DC offset and

nonlinearity is derived and the measurement approach of nonlinearity from DC offset is

demonstrated with simulated and measured results in the wideband receiver.

Linearity requirements are more stringent in multi-standard RF front-end receivers

since out-of-band interference signals fall into within operation bandwidth, requiring

higher linearity since they cannot be filtered out any longer for multi-standard

applications by an off-chip band selection filter. Wideband derivative superposition


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(WBDS) and self-biasing current reuse (SBCR) techniques are combined to achieve high

linearity even in a low-voltage operation for a wideband LNA. These linearity

enhancements are analyzed by the newly introduced frequency-dependent nonlinearity

coefficients and conceptual diagrams are shown to provide intuitive understanding about

nonlinear behavior of a linearity-enhanced wideband LNA. The coefficients provide

more accurate linearity estimation in an initial circuit design phase and enable us to

reduce circuit optimization iterations since they can capture the memory effects of FETs

such as parasitic capacitances.

To confirm the proposed linearity enhancement techniques, the two prototype LNAs

with Chebyshev bandpass filter (BPF) and transformer-based input matching networks

are designed, and the simulated and measured results of IIP3 are presented over an

operation bandwidth as well as with different frequency spacing of two sinusoidal test-

tone signals. Furthermore, the measured results of the second-order input intercept point

(IIP2) of the two LNAs are shown to observe the linearity degradation due to strong in-

band interference signals in a multi-standard radio depending on frequency allocation and

spacing, which have not been addressed in precedent publications.


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LIST OF CONTENTS

Acknowledgements .......................................................................................................... iv

Abstract.............................................................................................................................. v

Table of contents .............................................................................................................. ix

List of Tables ................................................................................................................... xii

Chapter 1 Introduction .................................................................................................... 1

1.1 RF Front-End Receiver ..................................................................................... 1

1.2 Issues in Multi-Standard RF Front-End Receivers ........................................... 4

1.3 Motivation ........................................................................................................ 5

1.4 Research Contributions..................................................................................... 81.5 Thesis Organization .......................................................................................... 9

Chapter 2 Wideband RF Circuit Design Techniques .................................................... 11

2.1 Introduction .................................................................................................... 11

2.2 Wideband RF Front-End Receiver ................................................................. 13

2.3 Wideband Low Noise Amplifier .................................................................... 15

2.4 Active Balun with Compensation Circuits ..................................................... 22

2.5 Low-Voltage Folded Mixer ............................................................................ 23

2.6 Simulated and Measured Results of the Wideband Receiver ......................... 34

2.7 Summary ......................................................................................................... 41

Chapter 3 Wideband Linearity Enhancement Techniques for LNAs ........................... 43

3.1 Introduction .................................................................................................... 43

3.2 Theory for Nonlinearity Analysis ................................................................... 45

3.3 Linearity Enhancement Techniques ............................................................... 54

3.4 Summary ......................................................................................................... 68

Chapter 4 Proposed Highly-Linear Wideband LNA .................................................... 70

4.1 Introduction .................................................................................................... 71

4.2 Self-biasing Current Reuse (SBCR) Technique ............................................. 72

4.3 Wideband Derivative Superposition (WBDS) Method .................................. 77

4.4 Derivation of IIP3 Expression Using Volterra Series .................................... 81


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4.5 Summary ......................................................................................................... 84

Chapter 5 LNA Design, Simulated and Measured Results ........................................... 85

5.1 Circuit Design of the Proposed LNA ............................................................. 85

5.2 Simulated and Measured Results .................................................................... 93

5.3 Summary ....................................................................................................... 106

Chapter 6 Conclusions ................................................................................................ 107

Suggestions for Future Research ................................................................................. 110

Introduction to Volterra Series and Harmonic Input ................................................... 112

Volterra Analysis of the Derivative Superposition Topology ..................................... 116

Volterra Analysis of the Wideband Modified Derivative Superposition Topology ... 126

Matching Table of Frequency-dependent Nonlinearity Coefficients from HB Analysis

..................................................................................................................................... 136

Bibliography ................................................................................................................ 138


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ix

TABLE OF CONTENTS

Number Page

Figure 1-1. Direct-conversion receiver architecture. ...........................................................2

Figure 1-2. Architectures of RF front-end receivers for multi-standard applications. ........6Figure 1-3. Frequency spectrum and state-of-art IIP3. ........................................................8Figure 2-1. Receiver block diagram for link budget calculation. ......................................14 Figure 2-2. (a) Simplified input matching network of a transformer-based wideband

LNA and (b) its equivalent input matching circuit. ...............................................17Figure 2-3. Embedded Chebyshev BPF input matching network......................................18Figure 2-4. Shunt peaking network: (a) simplified schematic and (b) its equivalent

circuit. ....................................................................................................................20Figure 2-5. Wideband LNA with transformer-based input matching network. .................22Figure 2-6. A schematic of the active balun with compensation feedback circuit. ...........23 Figure 2-7. Simplified schematic of the folded Gilbert cell mixer. ...................................24

Figure 2-8. Simulated DC offset vs. LO device mismatch. ...............................................26Figure 2-9. Chip micrograph and performance summary ..................................................27Figure 2-10. Frequency response of CG, NF and IIP3. .....................................................28Figure 2-11. Effect of supply voltage on CG. ....................................................................29Figure 2-12. Effect of input stage current density on CG, NF, and IIP3. ..........................30Figure 2-13. Effect of LO amplitude on CG, NF, and IIP3. ..............................................30Figure 2-14. DC offsets due to different contributors in the mixer. ..................................33Figure 2-15.(a) IIP2 and IIP3 extrapolation plot and (b) IF output spectrum...................34Figure 2-16. The chip micrograph of the receiver with wirebond and COB. ....................35Figure 2-17. Comparison of simulated and measured S-parameter S11. ..........................36Figure 2-18. Frequency responses of CG, NF, and IIP3. ...................................................36Figure 2-19. DC offsets due to different contributors in the receiver. ...............................38Figure 2-20. DC offset voltage due to self-mixing with different LO amplitude. .............39Figure 2-21. Differential circuit with input-referred offset voltage for relationship

between DC offset and nonlinearity. .....................................................................39Figure 2-22. Nonlinearity of simulated, measured, and calculated results. .......................41Figure 3-1. (a) A MOSFET transistor, (b) its incremental model including back-gate

effect, and (c) simplified equivalent circuit with the assumption that thenonlinearity is weak and memoryless. ...................................................................46

Figure 3-2. Flow chart for the derivation of an IIP3 derivation.........................................51Figure 3-3. Line spectrum of the positive frequency terms with two-tone input

signals. ...................................................................................................................52Figure 3-4. (a) Simplified schematic of a CS amplifier, (b) its DC transfer

characteristics, and (c) IIP3 plots. ..........................................................................57Figure 3-5. IIP3 plots with different source degeneration inductances at 0.1 and 1

GHz. .......................................................................................................................59Figure 3-6. (a) Schematic of the derivative superposition method, (b) conceptual

diagram of DS and (c) small-signal equivalent circuit. .........................................60Figure 3-7. Derivative superposition method. (a) 1

st-, 2

nd-, and 3

rd-order power

series coefficients of the auxiliary transistor, (b) 1st-, 2

nd-, and 3

rd-order


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power series coefficients of the main transistor, (c) 3rd

-order power series

coefficients and superposition, (d) Calculated IIP3 dBV. .....................................61Figure 3-8. IIP3 plots in different frequencies with 0.1 nH source inductance. ................63Figure 3-9. (a) Schematic of the modified DS method and (b) conceptual vector

diagram. .................................................................................................................65Figure 3-10. (a) Schematic of the alternative DS method and (b) conceptual diagram.....67

Figure 4-1. (a) Simplified common-source amplifier and (b) IIP3 vs. Vds. .......................73Figure 4-2. The effects of voltage headroom on IIP3: (a) simplified schematic and (a)

IIP3 vs. Vds plot. ...................................................................................................74Figure 4-3. LNA schematic with the self-biasing current reuse technique of the red-

colored portion. ......................................................................................................75Figure 4-4. (a) Node voltages and (b) currents in the LNA with the SBCR technique. ....76Figure 4-5. Conceptual diagram of linearity behavior over an operating frequency (a)

at the low-frequency optimized topology, (b) at the high-frequency optimized

topology, and (c) the resulting IIP3 plot. ...............................................................78Figure 4-6. LNA schematic with wideband derivative superposition (WBDS) method.

................................................................................................................................79

Figure 4-7. Polar plot of the frequency-dependent nonlinearity coefficients as a

function of frequency. ............................................................................................80Figure 4-8. Conceptual vector diagram with SBCR and WBDS techniques (a) at low

frequency and (b) at high frequency. .....................................................................81Figure 4-9. (a) Simplified LNA schematic with SBCR and WBDS techniques and (b)

its equivalent circuit. ..............................................................................................82Figure 5-1. Input matching network (a) Chebyshev BPF matching (b) transformer-

based matching.......................................................................................................86Figure 5-2. Distributed gate capacitance and channel resistance at high frequencies. ......88Figure 5-3. Simplified schematic of linearity-enhanced wideband LNAs. .......................89Figure 5-4. First-, second-, and third-order DC transfer coefficients of (a) the

auxiliary and (b) main transistors, (c) third-order coefficients and

superposition, (d) calculated IIP3 dBV in the proposed topology. ........................91Figure 5-5. Chip micrographs of the proposed LNAs with (a) transformer-based and

(b) Chebyshev BPF input matching networks. ......................................................92Figure 5-6. Simulated and measured results of the designed LNA (a) with

transformer-based matching network and (b) with Chebyshev BPF matchingnetwork. .................................................................................................................93

Figure 5-7. Parallel RC load impedance for Bode-Fano limit. ..........................................94Figure 5-8. NF and NFopt of the LNA with Chebyshev matching network. ......................95Figure 5-9. NF comparison of the LNA with transformer-based matching with or

without the SBCR. .................................................................................................96Figure 5-10. Noise summary of the devices in the LNA with Chebyshev BPF

matching. ................................................................................................................97Figure 5-11. IIP3 vs. gate bias voltage at 4GHz in the LNA with Chebyshev BPF

input matching network. ........................................................................................98Figure 5-12. IIP3 extrapolation plot at 4GHz in the LNA with Chebyshev BPF input

matching network...................................................................................................99


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Figure 5-13. IIP3 plot over frequency range in the LNA with transformer-based

input matching network. ......................................................................................100Figure 5-14. Simulated and measured IIP3 (a) vs. frequency range and (b) vs.

frequency spacing plots in the wideband LNAs with transformer-based

matching and with Chebyshev BPF matching. ....................................................101Figure 5-15. IIP3 vs. frequency spacing plots of (a) transformer-based matching and(b) Chebyshev BPF matching LNAs at different reference frequencies. ............102Figure 5-16. IIP2 vs. frequency plots of (a) transformer-based matching and (b)

Chebyshev BPF matching LNAs at different 2nd

-order IMD frequencies. ..........102Figure 5-17. Mechanism of IMD2 tones depending on frequency spacing. ....................104Figure 5-18. IIP2 vs. frequency spacing plots of transformer-based matching (a)-(c)

and Chebyshev BPF matching (d)-(f) LNAs at different 2nd

-order IMDfrequencies with different reference frequencies. ................................................106

Figure 6-1. IIP3 comparison plot with narrowband and wideband LNAs. ......................108


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LIST OF TABLES

Number Page

Table 1. IIP3 requirements of several standards ............................................................... 5

Table 2. Component values of Chebyshev BPF and transformer-based matching

networks......................................................................................................... 86

Table 3. Component values of the designed wideband LNA prototypes ................... 89

Table 4. IIP3 comparison with narrow band and wideband LNAs ................................ 109


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Chapter 1 Equation Chapter 1 Section 1

Introduction

As wireless telecommunication services are proliferating across the world, more

demands for both a new standard and multiple standards seem uprising rapidly to satisfy

the end users who want to access an increasing number of services from a single handset

regardless of geographical region [1]. This leads to ubiquitous wireless connectivity that

supports multiple standards across multiple frequency bands [2]. Minimizing the number

of external components and highly integrated solutions in low-cost CMOS technologies

are the keys when the same mobile handset supports multi-standard services. Zero-IF or

direct-conversion receiver architecture is most suitable for the high-level integration for

multi-standard RF receivers. One of the key challenges for multi-standard RF receivers is

how to achieve high linearity and low noise over a wide frequency range [3].

1.1 RF Front-End Receiver

One of the key components for wireless telecommunication systems is the RF front-

end receiver which receives both wanted and interference signals. It filters out the

unwanted out-of-band signal out, and amplifies the received weak signal with low noise,

and then downconverts the amplified signal into a baseband signal, with subsequent

filtering, amplification and dizitization, as shown in the direct-conversion receiver


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architecture of Figure 1-1. Gain, noise, and linearity should be carefully taken into

account in each block of the receiver to deliver desired communication quality when the

receiver is designed, while making a circuit implementation feasible in a given

technology. The importance of these three design parameters is described below.

BPF LNA Balun Mixer LPF VGA ADC

LO090

I

Q

Figure 1-1. Direct-conversion receiver architecture.

The received signal can be very weak since the transmitted signal will experience

attenuation due to spatial separation between the transmitter and the receiver or due to

objects located on the signal path. The signal has to be amplified such that it has large

enough amplitude to be digitized correctly while providing a required signal-to-noise

ratio (SNR) at the input of an analog-digital converter (ADC).

Since the received signal is weak, the noise generated in the RF front-end receiver

must be minimized the degradation of the receiver sensitivity. A low-noise amplifier is

typically implemented to reduce noise caused by the losses of the input matching network

and the noise of the amplifying devices.

The received signal can include unwanted out-of-band signals with large amplitude.

These unwanted signals can be filtered out by a band selection filter of an RF front-end

receiver. Therefore, linearity requirements for the out-of-band interference signals can be


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alleviated at the cost of using the band selection filter. Most of RF front-end receivers

have dedicated hardware for multiple standards with multiple band selection filters.

Accordingly, high linearity is not necessarily required in a conventional narrowband

receiver unless the filtered out-of-band interference signals are so strong that they can

deteriorate the linearity of the receiver. However, the co-existence of multiple standards

in the same cell area creates a hostile jamming environment for multi-standard wideband

receivers. These interference signals degrade the receiver sensitivity and thus can cause

the handset to drop the call. Thus higher linearity is demanded to guarantee the required

sensitivity in the hostile environment, compared to a single standard receiver.

In general, a RF front-end receiver consists of a low-noise amplifier, balun, and mixer.

In the receiver, a single-ended LNA topology is preferred since it can reduce I/O pins and

power consumption while providing easy interconnection between the single-ended

antenna or RF filter and LNA. On the other hand, a differential topology in the

subsequent devices such as a mixer and a variable gain amplifier as shown in Figure 1-1

is preferred not only to minimize the second-order distortion but also to reject power

supply and substrate noise [4]. Therefore, a balun is required to convert the single-ended

signal of the LNA into the differential signal for the mixer in the receiver. For

implementation of the balun, a passive or active balun can be chosen depending on the

receiver link budget in the system level design. An active balun is preferred to alleviate

the gain requirement in the subsequent stage as well as the NF requirement in the

previous stage. To facilitate low-voltage operation, a folded Gilbert cell mixer [5] or a

passive mixer is preferred to a conventional Gilbert cell mixer since it has three stacked

transistors and one load resistor.


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1.2 Issues in Multi-Standard RF Front-End Receivers

There are mainly two approaches to satisfy requirements of multi-standard RF front-

end receivers: 1) parallel combination of a narrowband receiver and 2) a single tunable or

wideband receiver. The single chip solution is more flexible and efficient in terms of area,

power, and cost.

The key components in achieving the RF requirements of multiple standards with a

fully integrated single chip solution are an LNA with low noise, a mixer with a very high

dynamic range, and a careful control of DC offset [6]. For the key components of multi-

standard RF front-end receivers, wide bandwidth, low noise, and high linearity are

important design parameters to achieve RF requirements. As a CMOS technology scales

down, the noise and bandwidth performance of RF front-end improves, but unfortunately

the linearity performance degrades with supply voltage reduction and high-field mobility

effects [7], [8]. On the contrary, the required linearity becomes higher due to the co-

existence of adjacent blockers from multiple standards, which were filtered out by a band

selection filter in a narrowband front-end receiver. In other words, since the co-existing

blockers within an operating wide bandwidth experience intermodulation and cross-

modulation without out-of-band filtering, higher linearity is inevitably required to support

multiple standards in a single chip solution. Furthermore, the second-order

intermodulation products are becoming a critical contributor of nonlinearity even in an

amplifier before downconversion in a mixer since the IMD2 terms which fall out of the

operating bandwidth in a narrowband amplifier fall within the in-band in a wideband

amplifier and thus deteriorate linearity along with the third-order intermodulation terms

depending on frequency spacing between interference signals.


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To evaluate the required performance of RF blocks for multi-standard applications, the

receiver (Rx) link budget calculation can be performed using cascade equations for gain,

NF, and IIP3, based on the system-level performance requirements. The required IIP3 for

several narrowband and wideband standards is summarized in Table 1. As described

above, the IIP3 requirement for multi-standard front-end receivers is expected to be much

higher than that for each receiver. For example, the IIP3 requirement for multi-standard

receivers has to be at least greater than the highest IIP3 among the standards, i.e., 0 dBm

and +12 dBm for LNA and mixer, respectively.

Table 1. IIP3 requirements of RF blocks in several standards.

StandardReceiver

IIP3 [dBm]

LNA

IIP3 [dBm]

Mixer

IIP3 [dBm]

UMTS [3] -4.6 0 +12

WLAN 802.11 a/b/g [3] -16* -5 +5

WiMAX 802.16 e [9] - -2.7 -

UWB (Group 1) [10] -18 -6.7 -

Multiband receiver [3] -4.6 0 +12

* high gain mode

1.3 Motivation

As we can see in the upper figure of Figure 1-2, multiple-dedicated RF front-end

circuits are necessary to support different standards. The single chip solution as shown in

the lower figure of Figure 1-2 is preferred due to its compact size and possible re-

configurability between standards. On top of wideband circuit design, the key challenge

in the design of the single-chip, multi-standard RF front-end is to achieve high linearity


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without out-of-band filtering since multiple blockers from different communications co-

exist within an operation bandwidth and thus deteriorate linearity due to cross-

modulation and intermodulation.

Figure 1-2. Architectures of RF front-end receivers for multi-standard applications.

As the part of a low-voltage wideband RF front-end receiver, the wideband folded

mixer was designed in [5] to facilitate low-voltage operation with 0.81.2-V supply. The

designed mixer showed reasonably competitive performance over 37 GHz bandwidth

even under 0.8-V power supply. Along with this folded wideband mixer, the wideband

RF front-end receiver with an active balun was designed in [11] such that it achieved

relatively wideband operation over 35 GHz bandwidth while achieving high second-

order linearity and low DC offset by adopting a fully differential topology after the


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wideband LNA. However, the RF front-end receiver showed low linearity performance

due to both low supply voltage and degradation of linearity by IMD2 contribution on the

IIP3.

According to the previous research [3] and system-level link budget calculation, the

required IIP3 in a mixer should be much higher than that in a LNA since interference

signals are amplified in the LNA, with deteriorating IMD terms further in the following

stages. For example, for multi-standard receiver [3], the required IIP3 in the mixer as

shown in Table 1 is 12 dB higher than that in the LNA. To understand why the wideband

receiver in [11] has low IIP3 even though the mixer IIP3 is not as low as to degrade the

receiver IIP3, further analysis and simulation are performed. It turned out that the

linearity of the LNA and active balun was not so high due to low supply voltage as well

as IMD2 contribution on the IIP3. To achieve high linearity in the wideband receiver,

some survey has been performed including precedent narrowband linearity enhancement

techniques for LNAs, as described below.

To support multiple standards, wide bandwidth and high linearity are required for

different frequency coverage as shown in the frequency spectrum plot of Figure 1-3 along

with IIP3 versus frequency plot for state-of-art LNAs. The square marks represent IIP3 of

narrow band LNAs and the circle marks represent IIP3 of wideband LNAs. The reference

circled with red dotted line used linearity enhancement techniques to achieve such a high

IIP3 for a narrow band LNA and wideband LNA.

While numerous techniques have been proposed for increasing LNA bandwidth (e.g.,

[10], [11]), there have been relatively few studies of linearity enhancement in wideband

LNAs. For example, [4] and [12] employ noise and distortion cancellation techniques to


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achieve an IIP3 of about 0 dBm for small frequency spacing at 0.82.1 GHz and 0.25.2

GHz while consuming a large amount of power of 17.4 mW and 21 mW, respectively. In

the design of highly-linear wideband RF front-end receivers, linearity enhancement and

wideband circuit techniques should be incorporated and implemented simultaneously

while minimizing power consumption for high mobility of handsets.

(1) J. Lee,

MTT2006(2) A. Ismail,

JSSC2004

(3) A. Bevilacqua,JSSC2004

(4) D. Mukherjee,RAWCON2002

(5) V. Aparin,

MTT2005(6) S. Ganesan,

MTT2006(7) C. Kim,

JSSC2005

(8) S. Blaakmeer,JSSC2008

(9) F. Agnelli,CAS2006

(10)A. Amer,

CAS2007

Linearity Enhancement Techniques

Figure 1-3. Frequency spectrum and state-of-art IIP3.

1.4 Research Contributions

The contribution of this research is to provide the techniques to implement both a

wideband RF front-end receiver and a linearity-enhanced wideband LNA, in conjunction

with analyzing DC offset, nonlinearity behavior, and the relationship between DC offset

and linearity. The details of contributions are described below:

1) Designed the wideband RF front-end receiver including a LNA, active balun, and

mixer.


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2) Demonstrated how to segment DC offsets caused by different DC offset

mechanisms in a differential circuit, showed the relationship between DC offset

and nonlinearity, and quantified the relationship by simulated, calculated, and

measured results in the wideband RF front-end receiver.

3) Proposed a linearity-enhanced wideband LNA topology.

4) Analyzed how linearity over the wide frequency range is improved with a

wideband derivative superposition method using newly introduced frequency-

dependent nonlinearity coefficients in the proposed LNA topology.

5) Designed linearity-enhanced wideband LNA prototypes and verified the

effectiveness of the proposed linearity-enhanced wideband LNA topology.

1.5 Thesis Organization

Chapter 2 describes the design of a low-power wideband RF front-end receiver. First,

receiver architectures are described and then the link budget calculation is explained to

define the requirements of the receiver building blocks such as an LNA, active balun, and

mixer. Second, wideband LNA topologies are introduced and then a proper topology for

the wideband LNA is chosen. As a part of design for a wideband RF front-end receiver,

matching networks are described for the design of the wideband LNA. Third, the design

of the active balun and low-voltage folded mixer are described to complete the wideband

RF front-end receiver. The detailed analysis is shown for the mixer with simulated and

measured results. Fourth, the simulated and measured results of the wideband RF front-

end receiver are shown with frequency responses, receiver DC offset, linearity, and the

relationship between DC offset and linearity.


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Chapter 3 describes theories for nonlinearity analysis including DC and frequency-

domain theories. Then some limitations of precedent analysis approaches are addressed

and the frequency-dependent nonlinearity coefficients are newly introduced to capture

memory effects of a MOSFET. The state-of-art linearity enhancement techniques are

presented to provide the understanding of distortion cancellation using Volterra series as

well as to address the limitation of those narrow band techniques.

Chapter 4 describes two proposed linearity enhancement approaches. One is the

wideband derivative superposition (WBDS) which makes IMD3 terms cancelled with

IMD2 terms at two frequencies such that IIP3 has two peaks over an operating frequency

bandwidth. The other one is the self-bias current reuse (SBCR) technique which bleeds

some amount of current directly to an RF input transistor with self-biasing such that the

voltage headroom problem in a deeply-scaled CMOS technology can be alleviated even

under low supply voltages. Conceptual diagrams of nonlinearity cancellation are shown

with both derived IIP3 expression and newly introduced frequency-dependent

nonlinearity coefficients to provide insight how two IIP3 peaks can be achieved over

wide operating bandwidth in the proposed LNA topology.

Chapter 5 describes the prototype implementation of two linearity-enhanced wideband

LNAs using the proposed LNA topology. Two wideband LNAs are implemented in a 0.13

m CMOS technology and the simulated and measured results are presented to confirm

the effectiveness of the proposed topology.

Chapter 6 concludes with a summary as well as suggestions for future research.


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Chapter 2 Equation Chapter (Next) Section 1

Wideband RF Circuit Design Techniques

2.1 Introduction

Several wireless standards have been used for their own communication services with

dedicated RF front-end receivers. The straight solution for multiple standards employs

parallel narrowband receivers at the expense of die area. A key factor for successful

design of multi-standard wideband systems is a low-power wideband RF front-end

receiver across multiple frequency bands in a single chip while meeting RF performance

requirements in a wideband LNA, an active balun, and a down-conversion mixer.

To design a compact low-power wideband receiver, the design of a 35-GHz CMOS

wideband RF front-end receiver is presented with an LNA utilizing a transformer

matching network, an active balun with compensation feedback, and a low-voltage folded

mixer. To achieve low-power operation and to realize a compact input matching network,

the LNA utilizes transformer-based input matching. The active balun is adopted to

convert single-ended signal into double-balanced one while alleviating gain and NF

requirements in the following stage and in the previous stage, respectively. To facilitate

low-voltage operation, the folded mixer is employed. For measurement of the wideband

receiver, a chip is attached on a PCB board using Chip-On-Board (COB) with bond wires.


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The relationship between DC offset, IIP2, and IIP3 is derived and confirmed by

simulated, calculated, and measured results. With this approach, nonlinearity in mass

production line can be estimated accurately and promptly without expensive RF

measurement facilities.

While a number of wideband RF front-ends have been reported, detailed circuit

analysis and optimization have been limited to wideband LNA designs. The design of

wideband mixers has not been studied extensively except in [13]. The distributed mixer

achieves wideband performance at the expense of large die area and high power

consumption. Another important requirement for the wideband mixer is low-voltage

operation to facilitate integration of the RF transceiver and the baseband DSP using

scaled CMOS processes. Low-voltage mixers using a folded Gilbert cell topology have

been proposed in [14], [15]. However, these designs are limited to narrow-band operation

owing to the use of LC-tank for biasing. To facilitate low-voltage operation, the mixer

employs a folded Gilbert cell topology with PMOS devices for LO switches and utilizes

on-chip broadband RF chokes for biasing. Detailed DC offset analysis in a mixer is

shown in the following section [5] and receiver nonlinearity is calculated based on the

measured DC offsets and then compared to the measured results.

In Section 2.2, the wideband RF front-end receiver is described on top of receiver

architectures and Rx link budget calculation. The implementation of the wideband low-

noise amplifier is described in Section 2.3 along with matching networks, followed by the

design of the active balun in Section 2.4 and the design of the low-voltage folded mixer

in Section 2.5. The simulated and measured results of the wideband receiver are shown in


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Section 2.6. Finally, the wideband circuit design techniques are summarized in Section

2.7.

2.2

Wideband RF Front-End Receiver

2.2.1 Receiver Architectures

The main categories of the RF front-end receiver architectures are heterodyne and

homodyne [16]. The heterodyne receiver is widely used for current wireless applications

since it achieves high performance requirements without limitations. However, it requires

an external image rejection filter and thus more components are required, resulting in

more area and power consumption. On the other hand, the homodyne receiver also called

the direction conversion or zero IF receiver has no image problem and thus needs no

external band selection filters. This architecture is more promising for high level

integration. However, the direction conversion architecture has some drawbacks [17]: DC

offset, 1/f noise, I/Q mismatch, even-order distortion, and LO leakage. In this Chapter,

the direct conversion receiver architecture is chosen to implement a compact low-power

wideband RF front-end receiver.

2.2.2 Receiver Link Budget Calculation

When a RF front-end receiver is designed with several RF building blocks, an Rx link

budget calculation is mandatory in the receiver design such that each block can

reasonably share the performance requirements by determining the feasibility of any

given blocks. The link budget calculation is also an excellent means for anyone to begin

to understand the various factors which must be traded off to realize a given area, cost,

feasibility, and level of reliability for a communications link.


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In the RF front-end receiver, the total gain, NF, and IIP3 of the receiver (G total, NFtotal,

and IIP3total, respectively) are calculated by the cascade equations of (2.1)-(2.4) whereg1,

g2, , gn are the linear gain of each stage, nf1, nf2, , and nfnare the noise factor of each

stage, and iip3,1, iip3,2, , iip3,n are the linear IIP3 of each stage, as shown in Figure 2-1.

( )1 2[ ] 10logtotal nG dB g g g = L (2.1)

321

1 1 2 1 2 1

1 11[ ] 10log ntotal

n

nf nf nfNF dB nf

g g g g g g

= + + + +

L

L

(2.2)

1 2 11 1 2

2,1 2,2 2,3 2,

12 [ ] 10log ntotal

n

g g gg g gIIP dBm

iip iip iip iip

+ + + +

L

L (2.3)

1 2 11 1 2

2 2 22 2 2

2 2 2 2

3,1 3,2 3,3 3,

13 [ ] 10log ntotal

n

g g gg g gIIP dBm

iip iip iip iip

+ + + +

L

L (2.4)

1

1

2,1

3,1

g

nf

iip

iip

2

2

2,2

3,2

g

nf

iip

iip

3

3

2,3

3,3

g

nf

iip

iip

4

4

2,4

3,4

g

nf

iip

iip

5

5

2,5

3,5

g

nf

iip

iip

Figure 2-1. Receiver block diagram for link budget calculation.

2.2.3 Wideband RF Front-End Receiver Design

The design of a 35-GHz CMOS wideband RF front-end receiver is performed with

an LNA utilizing a transformer matching network, an active balun with compensation

feedback, and a low-voltage folded mixer. To achieve low-power operation as well as to

realize a compact input matching network, the LNA utilizes transformer-based input


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matching. The active balun is adopted to convert single-ended signal into double-

balanced one while alleviating gain and NF requirements in the subsequent stage and in

the previous stage, respectively. To facilitate low-voltage operation, the mixer employs a

folded Gilbert cell topology with PMOS devices for LO switches and utilizes on-chip

broadband RF chokes for biasing. For measurement, a chip is attached on a PCB board

using Chip-On-Board (COB) with bond wires. The RF front-end consumes 19.3 mW

from a 1.2-V supply. The receiver achieves a CG of 28.532.3 dB, a single-sideband NF

of 5.59.9 dB, an IIP2 of 12.319.2 dBm, and an IIP3 of 28.3 to 23.7 dBm between 2

5 GHz. Relationship between DC offset, IIP2, and IIP3 is derived and confirmed by

simulated, measured, and calculated results. The calculated IIP2 and IIP3 based on

measured DC offsets have relatively better match with measured IIP2 and IIP3 results,

compared to the simulated ones. With this approach, nonlinearity in mass production line

can be estimated accurately and promptly without expensive RF measurement facilities.

2.3 Wideband Low Noise Amplifier

2.3.1 Wideband LNA Topologies

Among wideband LNAs, the distributed amplifiers [18] absorb all circuit parasitic

capacitances by incorporating on-chip transmission lines and provide wide bandwidth at

the expense of delay. These LNAs demand high-quality transmission lines, making them

less attractive to low-cost on-chip solutions due to the large chip area. The resistive

feedback amplifiers [19] can achieve wideband input matching, reducing the NF by the

local feedback with a feedback resistance and high voltage gain. However, large power

consumption is required to obtain a high loop gain in a single stage due to the inherently

low transconductance of a CMOS transistor, while stability will be caused with multiple


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stages. For moderate chip solutions in terms of area and power consumption, the ladder

network [20] and Chebyshev BPF network [10] amplifiers are proposed with multi-

section reactive networks so that the overall input reactance is resonated out over a wide

bandwidth. Another benefit of the LNA employing the Chebyshev BPF network is that

the topology can incorporate with linearity enhancement techniques addressed in Section

3.3.

2.3.2 Matching Networks

In this sub-section, a transformer-based input matching and Chebyshev BPF input

matching networks are analyzed to show how a wide bandwidth can be achieved with a

multi-section reactive network and a transformer. In addition, the shunt-peaking output

load network widely used in a wideband LNA is explained to address its limitation on

linearity enhancement techniques in Section 4.2.

A. Transformer-based Input Matching Network[11]

For a moderately wide bandwidth with a relatively small chip area, the transformer-

based input matching network is proposed. Figure 2-2 (a) shows the simplified input

matching network of the transformer-based wideband LNA and Figure 2-2 (b) represents

its equivalent circuit.


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(a) (b)

Figure 2-2. (a) Simplified input matching network of a transformer-based wideband

LNA and (b) its equivalent input matching circuit.

With the assumption that 1 2/k M L L= is as close to 1 as to neglect ( )2 11 k L in

Figure 2-2 (b), the input impedance of the LNA is given by

2 2

1

2 2 2 3 2 4 2

1 1 1

(1 )( )

1 ( )

T T s T sin

T T s T s T T T p s T p s

sk L s C L s C LZ s

s C L s C L n k C L s k C C L L s k C C L L

+ +=

+ + + + + (2.5)

where n is the turn ratio of the primary and secondary coils, k the coupling coefficient,

TC the total gate-source capacitance of the LNA input transistor, and T the unity-gain

frequency of the input transistor. As written in Eq. (2.5), the input matching networks

have two complex poles at the frequency smaller than the lower frequency of the target

bandwidth and two complex poles at the frequency greater than the higher frequency of

the target bandwidth, respectively. In addition, it has one zero at DC and one complex

zeros at the center frequency of the target bandwidth,2

1 1 4 / / 4T T T sC L , such

that the LNA has wideband input matching by arranging four complex poles and one

complex zero.

B. Input Matching Network Using LP-to-BP Filter Transformations


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The input matching network using LP-to-BP filter transformations shown in Figure

2-3 expands the use of an inductively degenerated common-source amplifier by

embedding the input network in a multi-section reactive network so that the overall input

matching network is resonated over a wide frequency range [10]. The parasitics of the

input device are embedded as the part of input matching networks.

Figure 2-3. Embedded Chebyshev BPF input matching network.

The input impedance of the MOS amplifier with a source degeneration inductor is

written as in Eq. (2.6)

( )11

( ) g S T ST

Z s s L L LsC

= + + + (2.6)

where CT is the equivalent gate-source capacitance,Lg the gate inductance,LS the source

degeneration inductance, and T the unity-gain frequency of the NMOS amplifier. The

gate-drain capacitance Cgd is not taken into account due to the complexity of the equation.

The -network topology in Figure 2-3 is chosen to achieve sharp out-of-band cutoff

characteristic by employing Chebyshev LP-to-BP transformations. For filter termination

and input impedance matching, the real part of the input impedance Z1(s) is ideally

determined to be equal to the source resistance, that is, TLS=RS. Ideally the power loss

in the filter passband is 0 dB with a ripple. Based on the bandwidth and in-band ripple,


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the reactive components of the filter, C1C3 andL1L3, are determined. The parasitics of

input devices are embedded as the part of input matching networks. The input impedance

of the amplifier including the -network filter structure is derived as shown in Eq. (2.7).

( )( )

2 2 4

2

2

1 2 3 4 1 1

2 4 6

1 2 3 5 6 1

4

4

1 ( )

1(

))

(in

z z s s z s z s L Z s

s p p s p s p s p s p s

sZ s

Z s

+ + + +

+ + + + + +

=

(2.7)

where11 3

z L L= ,12 2 2 3

C L Lz L= ,23 2 2 3 3 3

C L C Lz C L+ += ,34 2 2 3

C C Lz L= ,1 3

p L= ,

1 1 3 2 1 3 2 32 2C L L C L L C Lp L+ += , 1 2 1 33 2C C L Lp L= , ( ) ( )1 2 1 2 2 2 34 3C C L C Lp L C C+ + + += ,

( ) ( )1 2 1 2 3 1 3 1 3 2 3 3 15 2C C L L L C C L L C C Lp L L+ + + += , and 16 2 3 1 2 3C C C L Lp L= . Ideally with the

assumption that the real part of the 1( )Z s is equal to SR , the input matching network has

one zero at DC, four complex zeroes, and 6 poles such that it provides wideband input

matching by arranging the poles and zeros properly at the expense of an in-band ripple.

C. Wideband Output Load Network: Shunt Peaking

In addition to a wideband input matching network, the output load network should be

designed properly to achieve flat gain over a wide frequency range. One of the most

popular peaking techniques, the shunt-peaking technique as shown in Figure 2-4 is

applied. By adding an inductance in series with a load resistor, the impedance looking

into the load introduces a zero at /z d dR L = and thus increases with frequency. The

increasing impedance compensates the offset of the decreasing impedance due to the

parasitic capacitance of the following stage, resulting in constant load impedance over a

wide frequency range. The behavior of the shunt-peaking load can be interpreted with the

time-domain view. Since the inductor delays current flow through the resistor, the


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capacitor can be charged fast due to more available current. Faster charging time means a

shorter rising time, that is, can be interpreted the wider bandwidth.

(a) (b)

Figure 2-4. Shunt peaking network: (a) simplified schematic and (b) its equivalent

circuit.

The output impedance ( )outZ s in Figure 2-4 (b) is written by

( )2

/ 1( )

1

d d d

out

d par d par

R s L RZ s

s L C sR C

+ =+ +

. (2.8)

To obtain an optimum inductance value, a factorm is introduced and defined as the ratio

of the d par R C and /d dL R time constants [21]:

/

d par

d d

R Cm

L R= . (2.9)

To maximize the bandwidth, m should be approximately 1.41, resulting in extending the

bandwidth to 1.85 times wider than the uncompensated bandwidth. On the other hand, the

shunt-peaking inductance dL is determined by two opposite requirements [10]: the


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21

inductance dL should be large to have large gain, and it should be small to resonate with

the load parasitic capacitance added by the parasitic of the following stage such as a

mixer in a receiver and a buffer amplifier for test purpose out of band. The load

resistance dR is determined so that the zero frequency is located closely to the lowest

operating frequency to compensate the gain decreased abruptly at the low frequencies.

Usually the largest load resistance is chosen to achieve high gain, but it limits the voltage

headroom, resulting in degrading linearity that will be addressed in detail in Section 4.2.

2.3.3 Implementation of LNA with Transformer-Based Matching Network

Figure 2-5 shows the simplified schematic of the LNA with transformer-based input

matching network of the previous sub-section 2.3.2. To achieve high gain and large

reverse isolation, a cascode topology is employed with the source degeneration inductor

Ls to realize 50- real input impedance. The external gate-source capacitance Cd is

added to reduce the gate inductance value required for input match since the gate-source

capacitance of the transistorM1 is usually small. The use of the degeneration inductor

poses inherent narrowband input match due to narrowband resonance in the equivalent

series RLC resonant circuit. These series RLC circuits are embedded as the part of an

input matching network with the transformer (L1, L2) and shunt capacitor (Cp). The

detailed analysis of the input matching network is described in the sub-section 2.3.3.


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Figure 2-5. Wideband LNA with transformer-based input matching network.

2.4 Active Balun with Compensation Circuits

Fully differential circuits are preferred in mixed-signal chip design as balanced circuits

have advantages of keeping common mode substrate noise from high speed digital

circuits at a minimum level. The direct conversion receiver suffers from the second-order

distortion like low IF. To overcome those issues, fully differential RF circuit techniques

have been employed in the following stages after the single-ended LNA. Baluns are basic

elements required in RF components such as balanced mixers and phase splitters to

convert single-ended input signal into differential output signal [22]. There are two

different types of baluns: passive baluns by passive LC networks and active baluns by

differential amplifiers. Since passive baluns occupy large chip area and are lossy, an

active balun is adopted in this design while alleviating gain requirement in the LNA and

NF requirement in the mixer. If a differential amplifier has infinite impedance at the drain

k

Vin

Ls

L2L1Cp

VDD

Cc

Rd

Ld

M2

M1

VBS1

CdVs

Rs

LNAout

128/0.12

256/0.12

k

Vin

Ls

L2L1Cp

VDD

Cc

Rd

Ld

M2

M1

VBS1

CdVs

Rs

LNAout

128/0.12

256/0.12


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node of the tail current sourceM7 in Figure 2-6, differential amplifier can provide equal

amplitude and 180 phase difference. Due to finite impedance and parasitics at higher

frequencies, good gain and phase balance are not achievable. In order to compensate gain

and phase imbalance, a fraction of the single-ended signal is fed back to the input

transistorM4 through a series RLC network as shown in Figure 2-6. The detailed design

is shown in the schematic of Figure 2-6.

Figure 2-6. A schematic of the active balun with compensation feedback circuit.

2.5 Low-Voltage Folded Mixer

This section presents the design and analysis of a low-voltage downconversion mixer

in 0.13-m CMOS for wideband applications between 37 GHz. To facilitate low-voltage

operation with 0.81.2-V supply, the mixer employs a folded Gilbert cell topology with

PMOS devices for LO switches and utilizes on-chip broadband RF chokes for biasing.

The folded topology allows the transconductance and LO stages to have different bias

VDD

LNAout M3 Rbias M4

M7

32/0.12

VBS2

320/0.5

32/0.12

64/0.12

64/0.12

150 150

88 0.8pF 3nH

20K

M5 M6

RF-RF+

VDD

LNAout M3 Rbias M4

M7

32/0.12

VBS2

320/0.5

32/0.12

64/0.12

64/0.12

150 150

88 0.8pF 3nH

20K

M5 M6

RF-RF+


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current. By setting the bias current in the PMOS switches near zero, the mixer DC offset

due to device mismatch is greatly reduced. The effect of supply voltage on the mixer

performance is studied.

The wideband frequency responses of the mixer performance under different supply

voltages are studied in detail. To achieve high performance with low power consumption,

DC bias current density and LO amplitude are optimized based on experimental data. DC

offsets due to different sources are measured methodically to analyze their relative

importance.

2.5.1 Folded Mixer Circuit Design

The schematic of the folded, double-balanced mixer is shown in Figure 2-7. The

NMOS differential pair, M1 and M2, forms the input transconductance stage (gm-stage).

The PMOS LO switches,M3 throughM6, are folded with respect to thegm-stage.

Figure 2-7. Simplified schematic of the folded Gilbert cell mixer.

LO+

VDD

RL480

IF+ IF-

LO+

LO-

RF+ RF-M 1 M 2 M 3 M 4 M 5 M 6

L2=5.4 nH

Rs=18.4

Rbias Rbias Rbias Rbias

RFdc LOdc

M7

RL480

32/0.12

16/0.12

Vbias320/0.5

32/0.12

L1=5.4 nH

Rs=18.4

LO+

VDD

RL480

IF+ IF-

LO+

LO-

RF+ RF-M 1 M 2 M 3 M 4 M 5 M 6

L2=5.4 nH

Rs=18.4

Rbias Rbias Rbias Rbias

RFdc LOdc

M7

RL480

32/0.12

16/0.12

Vbias320/0.5

32/0.12

L1=5.4 nH

Rs=18.4


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This technique is effective in 0.13-m technology because PMOS devices with

moderate W/L are sufficiently fast to completely steer the current from the gm-stage to

the LO switches with reasonable LO amplitudes. The folded topology offers a key

advantage over the standard stacked topology for allowing independent settings of the

bias currents through the gm-stage and LO switches. The bias current for the gm-stage

should be high enough to achieve the desired CG, NF, and IIP3. However, the bias

current through the LO switches should be minimized to suppress DC offset, thermal and

1/fnoise. The Vgs of the LO switches is set nearVt to achieve a low bias current (~50A)

and at the same time ensure that the required LO amplitude remains at a reasonable level

(~300 mVpp) for complete current commutation. The small bias current in the LO

switches also allows the usage of large load resistances (RL = 480 ) to increase the CG

without consuming large IR drop from the limited voltage headroom. The RF chokes,L1

andL2, present a high impedance from 3 to 7 GHz such that the output AC currents of the

gm-stage will flow into the LO switches. The RF chokes are realized using two inductors

rather than one differential inductor to achieve higher self-resonance frequency (SRF)

and hence wider operating bandwidth. The series inductance and resistance of the RF

choke are 5.4 nH and 18.4 , respectively. The RF choke has a SRF of 10.8 GHz due to

its parasitic shunt capacitance which is 40 fF.

The DC offset in mixers is a critical parameter for direct conversion receivers since

most of the gain occurs after the downconversion of the input signal and the receiver can

be saturated if the offset is too large. Static DC offset can be caused by device mismatch,

LO self-mixing due to LO-to-RF leakage, and secondary nonlinearity. Mismatch in the

LO switches and load resistances is usually a major contributor to DC offset in fully


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balanced mixers. Figure 2-8 shows the simulated DC offset voltage at the IF output port

versus the LO device mismatch percentage for both the proposed folded mixer and a

standard Gilbert cell mixer. The folded mixer is simulated with two LO bias current

levels at ~0 and 44 A/m. As expected, the DC offset voltage due to mismatch

decreases with the low bias current level. Since the folded mixer can have nearly zero LO

bias current and still functions properly, the IF output DC offset is suppressed to 2 mV

even with a 20% device mismatch. In contrast, a standard Gilbert cell mixer with the

same device mismatch exhibits a DC offset of more than 40 mV. The higher DC offset

voltages of the folded mixer at the same current density is caused by larger load

resistance value. For example, the load resistance is around 150 in the Gilbert cell

mixer, but 480 in the folded mixer, causing larger voltage drop across the load resistor.

The detailed analysis of the different sources for static and dynamic DC offsets will be

presented with measured data in the next section.

Figure 2-8. Simulated DC offset vs. LO device mismatch.

-25 -20 -15 -10 -5 0 5 10 15 20 25-50

-40

-30

-20

-10

0

10

20

30

40

50

Device Mismatch Percentage [%]

DC

OffsetVoltage[mV]


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2.5.2 Simulated and Measured Results of the Folded Mixer

The chip micrograph and performance summary are shown in Figure 2-9. The active

area is 360x380 m2. The layout of the mixer uses pre-characterized components from an

in-house RF parameterized cell (P-cell) library for accurate device and interconnect

model [23]. The layout is fully symmetrical in order to reject common-mode noise and to

minimize phase and amplitude imbalance in the differential signal paths which can

degrade CG, linearity, and port-to-port isolation. All signal paths are shielded from each

other to improve port-to-port isolation.

The measurements are performed using an Agilent E4440A spectrum analyzer.

Cascade SGS probes with external 180 hybrids are used for supplying the RF and LO

signals. A high-impedance differential active probe (Agilent N1025A) is used for

measuring the IF signals.

Figure 2-9. Chip micrograph and performance summary

3.2 0.3 dBmIIP3

360 m380 mActive area

9.6 13.5 dBNF

2.4 4.3 mVDC offset

37.3 43.4 dBmIIP2

5.3 8.2 dBCG

3.0 7.0 GHzFrequency

5.8 mW at 1.2 VPower

0.13-m CMOSTechnology

3.2 0.3 dBmIIP3

360 m380 mActive area

9.6 13.5 dBNF

2.4 4.3 mVDC offset

37.3 43.4 dBmIIP2

5.3 8.2 dBCG

3.0 7.0 GHzFrequency

5.8 mW at 1.2 VPower

0.13-m CMOSTechnology


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A. Frequency ResponseThe measured frequency responses of the mixer CG, NF, and IIP3 under a 1.2-V

supply are shown in Figure 2-10 along with simulation results. The dotted line and solid

line represent the simulated and measured performance, respectively. Good agreement

between simulation and measurement is achieved due to the accurate modeling of the

device and layout parasitics as well as the test setup including the off-chip hybrids. Both

CG and NF exhibit the best performance, 7.8 dB and 9.7 dB, respectively, near 5.2 GHz

where the effective choke impedance reaches its peak value. The IIP3 is recorded

between 3.2 to 0.3 dBm and does not show a strong frequency dependency since it is

predominately determined by the input transconsductance which does not vary

significantly with frequency.

Figure 2-10. Frequency response of CG, NF and IIP3.

B.Performance vs. Biasing and LO AmplitudeNext, the effects of supply voltage on the mixer performance are studied. The

frequency responses of the CG at 0.8-V, 1-V, and 1.2-V supply are compared in Figure

2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5-6

-4

-2

0

2

46

8

10

12

14

Frequency [GHz]

CG[

dB]

NF[dB]

IIP3[dBm

]

IIP3

CG

NF


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2-11. As the supply voltage reduces from 1.2 V to 0.8 V, the CG is degraded by an

average of 2.5 dB. However, the NF and IIP3 remain relatively the same with less than 1

dB of degradation on average over the entire frequency range of 37 GHz. This illustrates

that the folded mixer is a robust topology for low-voltage operation.

Figure 2-11. Effect of supply voltage on CG.

The biasing conditions for the input gm-stage have a major impact on the mixer

performance and therefore must be optimized. Figure 2-12 shows that the CG, NF, and

IIP3 improve with increasing bias current density and then saturate as the input

transconductance starts to degrade due to velocity saturation at high current density. For

this design, the optimal bias current density is 115 A/m and further increases merely

consume more power without any performance improvements. The effect of LO

amplitude on the mixer performance is also examined. Figure 2-13 shows that the CG,

NF, and IIP3 degrade noticeably when the LO amplitude is below 300 mVpp because of

insufficient voltage swing to completely steer the LO current.

2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.50

1

2

3

4

5

6

7

8

9

10

Frequency [GHz]

C

G[

dB]

CG Measured at VDD=1.2V




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30

Figure 2-12. Effect of input stage current density on CG, NF, and IIP3.

Figure 2-13. Effect of LO amplitude on CG, NF, and IIP3.

C.DC OffsetTo measure the mixer DC offset due to the different mechanisms including device

mismatch, LO self-mixing, and second-order intermodulation product, the testing

0 20 40 60 80 100 120 140 160 180-6

-4

-2

0

2

4

6

8

10

12

14

16

Current Density [uA/um]

CG[

dB]

NF[dB]

IIP3[dBm]

CG

NF

IIP3

0 0.1 0.2 0.3 0.4 0.5-15

-10

-5

0

5

10

15

20

Single-ended LO Amplitude [Vpp]

CG[

dB

]

NF[dB

]

IIP3[dBm]

CG

NF

IIP3


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31

procedure described in [24] is adopted. In the first measurement, the RF and LO inputs

are supplied with DC bias only and are terminated with precision 50-terminations. As a

result, the measured DC offset is due to device mismatch only (Vos, mismatch). In the second

measurement, the LO signal is applied whereas the RF input is still with DC bias only. In

this case, the measured DC offset (Vos, LO) includes the effect of both device mismatch

and LO self-mixing owing to LO-to-RF leakage. The DC offset due to LO self-mixing

(Vos, self-mixing) can be determined by taking the difference between Vos, LO and Vos, mismatch

from the first measurement:

, , ,os sel f mixing os LO os mismatchV V V = . (2.10)

In the third measurement, two-tone signals at 3.99975 GHz and 4.00025 GHz are

applied to the RF input while the LO frequency is set to 3.990 GHz. The two-tone RF

signal strength is set at 20 dBm to model low-power interferers. It should be pointed out

that the RF frequencies are chosen to be about 10 MHz away from the LO frequency so

as to separate the effects of LO self-mixing and second-order nonlinearity. With this

setup, the total static DC offset (Vos, total) is measured, which includes the effect of device

mismatch, LO self-mixing, and second-order nonlinearity. Consequently, the contribution

of second-order nonlinearity (Vos, IM2) to the total DC offset can be extracted using Vos, LO

from the second measurement as follows:

, 2 , ,os IM os total os LOV V V= . (2.11)

As an attempt to estimate the dynamic DC offset which can be caused by strong in-

band interferers, the fourth measurement is performed with the two-tone RF signals

increased from 20 dBm to 0 dBm. The excess DC offset due to the high-power


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interferers (Vos, strong IM2) can then be determined from the measured DC offset (Vos, system)

as

, 2 , , 2 ,os strongIM os system os IM os LOV V V V = . (2.12)

The breakdown of DC offsets due to the different sources is summarized in Figure

2-14 based on the measurement results from 10 different samples. The measured offset

ranges from 2.4 to 4.3 mV when LO amplitude of 450 mVpp is applied. LO self-mixing

is the main contributor at 51 %. Device mismatch is responsible for 37 % of the offset.

Typically, device mismatch is the dominant cause for mixer DC offset. The superior

performance obtained is due to the folded topology which allows the LO bias current to

be set at near zero. Even when the strong RF interferers at 0 dBm are applied, the DC

offset due to second-order intermodulation contributes only 12 % to the total DC offset.

However, further measurements reveal that when the LO amplitude is reduced to optimal

level at about 300 mVpp, the DC offset reduces to between 1.73.6 mV. The device

mismatch becomes the main contributor at about 45 % whereas the LO self-mixing and

high-power intermodulation have almost the same contributions at 29 % and 26 %,

respectively. It is observed that the offset due to high-power intermodulation is higher at

the lower LO amplitude. This result confirms that excessive LO amplitudes should be

avoided for the proposed folded mixer to minimize DC offset due to LO self-mixing.

Furthermore, within the bandwidth limitation, the LO switching PMOS devices should be

made as wide as possible to reduce both mismatch and the required LO amplitude.


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Figure 2-14. DC offsets due to different contributors in the mixer.

D.LinearityFigure 2-15 shows an extrapolation plot of IIP2 and IIP3 based on a two-tone test with

RF inputs at 5.20 GHz and 5.2005 GHz and the IF output spectrum centered at 10.25

MHz. Over the 37 GHz wideband, the mixer achieves an IIP2 of 37.3 to 43.4 dBm, and

an IIP3 of 3.2 to 0.3 dBm.

(a)

0 1 2 3 4 5 6 7 8 9 10 110

1

2

3

4

5

6

7

Number of Samples

DC

OffsetVoltag

e[mV]

Device Mismatch

Self-mixing

Low-power Intermodulation

High-power Intermodulation

0 1 2 3 4 5 6 7 8 9 10 110

1

2

3

4

5

6

7

Number of Samples

DC

OffsetVoltag

e[mV]

Device Mismatch

Self-mixing

Low-power Intermodulation

High-power Intermodulation

-40 -30 -20 -10 0 10 20 30 40 50-120

-100

-80

-60

-40

-20

0

20

40

60

80

RF Input Power [dBm]

IFO

utputPower[dBm]

IIP3=-2.02dBm

IIP2=38.63dBm


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(b)

Figure 2-15.(a) IIP2 and IIP3 extrapolation plot and (b) IF output spectrum.

2.6 Simulated and Measured Results of the Wideband Receiver

The wideband front-end receiver including the LNA, active balun, and folded mixer is

designed in a 0.13-m CMOS process and fabricated as shown in Figure 2-16. The active

area is 1200x400 m2. For measurement, the RF front-end portion is diced and attached

on the designed PCB board with bondwire connectivity for signal and power supply. To

convert a differential mixer output signal into a single-ended signal, an external receiver

[25] is used on the PCB board.


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Figure 2-16. The chip micrograph of the receiver with wirebond and COB.

A. Conversion Gain, NF, and Nonlinearity

The simulated and measured S11 are compared in Figure 2-17. The measured S11

including bondwire and PCB parasitics is less than 10 dB over 2.55.5 GHz without

external matching networks on the PCB board. The measured frequency responses of the

CG, NF, and IIP3 under a 1.2-V supply are shown in Figure 2-18 along with simulation

results. The line with circles and the line with triangles represent the simulated and

measured performance, respectively.


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Figure 2-17. Comparison of simulated and measured S-parameter S11.

Figure 2-18. Frequency responses of CG, NF, and IIP3.

All the measured results include parasitics from the COB and PCB without external

input matching networks. Both CG and NF exhibit the best performance, 32.3 dB and 5.5

dB, respectively, near 3 GHz where the S11 has deep notch and the output load impedance

of the LNA has peak impedance since the active balun and mixer are designed to have

1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7-25

-20

-15

-10

-5

0

Frequency [GHz]

S11[dB]

S11 Measured

S11 Simulated

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5-40

-30

-20

-10

0

10

20

30

40

Frequency [GHz]

CG

[dB],NF[dB],IIP3[dBm]

NF

CG

IIP3


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relatively flat gain characteristic by having opposite gain slope over the frequency range.

The IIP3 is recorded between 28.3 to 23.7 dBm over 25 GHz frequency. The lower

nonlinearity comes from the load resistance of 150 in the active balun since it causes

around 0.3 V voltage drop across the load resistors. If the load resistors are replaced by

inductors, linearity will be improved. The CG and IIP3 are de-embedded to get

performance of the receiver itself, but the NF includes noise contribution of the external

receiver.

B. DC Offset and Nonlinearity

The DC offset is a critical parameter for direct conversion receivers since most of the

gain occurs after the downconversion of the input signal and the receiver can be saturated

if the offset is too large. Static DC offset is caused by device mismatch, LO self-mixing

due to LO-to-RF leakage, and secondary nonlinearity.

To measure the receiver DC offsets due to the different mechanisms including device

mismatch, LO self-mixing, and second-order intermodulation product, the testing

procedure described in [5] is adopted. The measured DC offsets due to the different

mechanisms are isolated and plotted in Figure 2-19 over the frequency range. The main

contributor of the DC offset in the receiver is the self-mixing due to LO feedback to the

input of the LNA, active balun, and mixer. The big change in the plot compared to the

previous DC offset plot of the mixer itself is the increment of the DC offset due to self-

mixing. It was less than 3mV in the mixer, but it increases a few tens of mV to a few

hundreds of mV amplitude. Since the LO amplitude coupled at the LNA and active balun

input is amplified as much as the gain of each block or the cascaded blocks. For example,


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if the cascade gain of the LNA and active balun is greater than 20 dB, the DC offset due

to the self-mixing will be amplified by the amount of the gain as well.Abrupt change in

the DC offset due to self-mixing over the operating bandwidth comes from amplitude and

phase imbalance of the external hybrid and cable assembly to make differential LO

signals. The maximum imbalance of amplitude and phase are 0.5 dB and 14,

respectively. As shown in Figure 2-19, the main contributor to the DC offset is LO self-

mixing. In order to understand the effects of LO amplitude on the DC offset due to the

self-mixing, LO signal is swept and DC offset due to the self-mixing term is measured

and shown in Figure 2-20. The LO amplitude should be minimized to reduce DC offset

from the self-mixing as long as complete commutation is achieved in the LO switching

stage of the mixer.

Figure 2-19. DC offsets due to different contributors in the receiver.

2 2.5 3 3.5 4 4.5 5 5.5 60

50

100

150

200

250

300

350

Frequency [GHz]

DC

OffsetVoltage[mV

]

Device Mismatch

Intermodulation

Self-mixing


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Figure 2-20. DC offset voltage due to self-mixing with different LO amplitude.

RF linearity measurement requires expensive test facilities such as network analyzer,

spectrum analyzer, signal generator, and so on. For nonlinearity measurement of IIP2

and IIP3, two signal generators and one spectrum analyzer are mandatory equipments.

Furthermore, it takes time since input signal amplitude needs to be swept by 1 dB step to

pick appropriate extrapolation point up for accurate measurement. As an alternative way,

DC offset can be utilized to get relatively accurate IIP2 and IIP3 as described below.

Suppose that there is a static offset voltage in differential circuit arising from device

mismatch or bias asymmetry, the offset voltage can be referred to the input of the

differential circuit to model all internal offsets as shown in Figure 2-21 [26].

Figure 2-21. Differential circuit with input-referred offset voltage for relationship

between DC offset and nonlinearity.

-20 -15 -10 -5 0 5-10

0

10

20

30

40

50

LO Power [dBm]

Vos,S

M[m

V]

Differential

Circuit

(Av,diffor Gdiff)

Oscilloscope

or

Multimeter

Zeq

Vos,in

Vos,IM2

Vin Vout

Differential

Circuit

(Av,diffor Gdiff)

Oscilloscope

or

Multimeter

Zeq

Vos,in

Vos,IM2

Vin Vout


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The DC offset due to the second-order intermodulation (Vos,IM2) can be employed to

evaluate the IIP2. Because Vos,IM2 represents the amplitude of the second-order

intermodulation product, IIP2 can be calculated as in Eq.(2.13)

2,2 2 in osIIP P P CG= + (2.13)

where Pin is the input power and P2,os is the amplitude of the second-order

intermodulation product (Vos, IM2) in dBm, and CG is the conversion gain of the receiver

in dB. When P2,os is calculated, the input impedance (Zeq) of the multimeter or

oscilloscope which measures the DC offset voltage as shown in Figure 2-21 should be

taken into account. In this measurement, LeCroy 9354L oscilloscope is used along with

AP020 probe having 1-M input impedance. If the input-referred offset voltage (Vos,,in)

of the differential circuit and the calculated IIP2 from the output DC offset voltage are

known, IIP3 can be calculated based on the following equation which is derived using

power series L+++= 3in32

in2in1out VaVaVaV as shown in [7] with two input tones including

the input-referred offset voltage, )tcos(A)tcos(AVV 21in,osin ++= .

( )( ), 2 ,3 10 log 2 2 / 50 30os in IIP os inIIP V V V= + (2.14)

where VIIP2 is the input-referred second-order intercept voltage, VIIP3 the input-referred

third-order intercept voltage.

To calculate IIP3 based on the measured DC offset and calculated IIP2, the measured

output DC offset voltage should be referred to the input using the following equation

, 2

,

,

os IM

os in

v diff

VV

A= (2.15)


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whereAv,diff is the gain of the differential circuit as shown Figure 2-21. The IIP2 and IIP3

are calculated with Eq. (2.14) and Eq.(2.15), respectively and compared to the simulated

and measured results in Figure 2-22. The line with circles represents the simulated results,

the line with squares the calculated ones, and the line with triangles the measured ones.

The measured results show relatively better matching with the calculated results from the

measured DC offset voltage rather than the simulated results. This comparison proves

promising usefulness of the DC offset in differential circuits to estimate nonlinearity by

simply measuring DC offsets since the calculated IIP3 is placed in between the simulated

and measured results.

Figure 2-22. Nonlinearity of simulated, measured, and calculated results.

2.7 Summary

The low-power wideband receiver with active balun is realized using 0.13-m CMOS

technology. The compact LNA with transformer-based input matching is realized,

followed by the active balun to provide fully differential circuit for the folded mixer. The

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

Frequency [GHz]

IIP2&IIP3[dBm]

IIP2

IIP3

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

Frequency [GHz]

IIP2&IIP3[dBm]

IIP2

IIP3


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folded mixer topology utilizing PMOS devices in the switching stage and broadband RF

chokes for biasing is shown to be an effective technique for both low-voltage and

wideband operation. The key sources to the receiver DC offset are measured

systematically using a multi-step procedure under different excitations. The usefulness of

DC offset in the receiver is proven to estimate nonlinearity without measuring IIP2 and

IIP3 which requires expensive RF equipments.

The low-power, high-performance wideband down-conversion mixer is realized to

suppress the impact of device mismatch on DC offset. The key sources to the mixer DC

offset are measured systematically using a multi-step procedure under different

excitations.


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Chapter 3 Equation Chapter (Next) Section 1

Wideband Linea

Linearity Enhancement Techniques _cmu Ece 2009 011 1

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