Aurora’s Technological and Research Institute ECE Department 1 CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION TO VLSI : Very-large-scale integration (VLSI) is the process of creating an integrated circuit by combining thousands of transistors into a single chip. VLSI began when complex semiconductor and communication technologies were being developed. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other peripherals; VLSI lets IC makers add all of these into one chip. The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices with ten diodes, transistors, resistors and capacitors making it possible to fabricate one or more logic gates on a single device. The fabrication of IC’s began with Small Scale Integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as Medium Scale Integration (MSI), followed by thousands of logic gates called Large Scale Integration (LSI). Current technology has moved far past this mark having many millions of transistors fabricated on single chip known as Very large Scale Integration (VLSI).In the course of enhancement of technology suitable softwares like VHDL were developed during electric circuit design to work in real time applications for military purpose by the USA. VHDL an acronym for VHSIC hardware description language (VHSIC is an acronym for Very High Speed Integrated circuits ). It is a hardware description language that can be used to model a digital system at many levels of abstraction, ranging from algorithm level to gate level. It contains elements that can be used to describe the behavior or structure of the digital system, with the provision for specifying its timing explicitly and supporting system hierarchy
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Aurora’s Technological and Research Institute ECE Department
1
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION TO VLSI :
Very-large-scale integration (VLSI) is the process of creating an integrated circuit by combining
thousands of transistors into a single chip. VLSI began when complex semiconductor
and communication technologies were being developed. Before the introduction of VLSI
technology most ICs had a limited set of functions they could perform. An electronic
circuit might consist of a CPU, ROM, RAM and other peripherals; VLSI lets IC makers add all
of these into one chip. The first semiconductor chips held two transistors each. Subsequent
advances added more transistors, and as a consequence, more individual functions or systems
were integrated over time. The first integrated circuits held only a few devices with
ten diodes, transistors, resistors and capacitors making it possible to fabricate one or more logic
gates on a single device. The fabrication of IC’s began with Small Scale Integration (SSI),
improvements in technique led to devices with hundreds of logic gates, known as Medium Scale
Integration (MSI), followed by thousands of logic gates called Large Scale Integration (LSI).
Current technology has moved far past this mark having many millions of transistors fabricated
on single chip known as Very large Scale Integration (VLSI).In the course of enhancement of
technology suitable softwares like VHDL were developed during electric circuit design to work
in real time applications for military purpose by the USA. VHDL an acronym for VHSIC
hardware description language (VHSIC is an acronym for Very High Speed Integrated circuits ).
It is a hardware description language that can be used to model a digital system at many levels of
abstraction, ranging from algorithm level to gate level. It contains elements that can be used to
describe the behavior or structure of the digital system, with the provision for specifying its
timing explicitly and supporting system hierarchy
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1.2 . ADVANTAGES OF VLSI:
Very Large Scale integration is a method of putting the functionality of many different types of
electronic components into a small space or chip
Reduces the Size of the device
Reduces the cost of the device
Reduces the power consumption
Increases the Speed of operation
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CHAPTER 2
BLOCK DIAGRAM
LFSR is widely used as test pattern generator because of its small circuit area and excellent
random characteristics. The proposed architecture consists of a seed generator (SG) with LFSR,
a n-bit counter, a Gray encoder and an exclusive-OR array. The n-bit counter and Gray encoder
generate single input changing patterns.
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Working:
According to the design the proposed structure of TPG C[n-1:0] is the counter output and G[n-
1:0] is the gray encoder output. The counter and SG are controlled by test clock TCK. The initial
value of the n-bit counter is all zeroes, and it generates 2n continuous binary data periodically.
The output of NOR operation of C[m-1:0] will be the clock control signal of SG where m<=n. It
can be found that SG will generate the next seed only when C[m-1:0] are all “0‟ and NOR output
changes to “1‟. The period of the single input changing sequences will be 2m.Gray encoder in
Fig. 1 is used to encode the counters output C[n-1:0] so that two successive values of its output
G[n-1:0] will differ in only one bit. Gray encoder can be implemented by following logic.
G[0] = C[0] XOR C[1]
G[1] = C[1] XOR C[2]
G[2] = C[2] XOR C[3]
…….
G[n-2] = C[n-2] XOR C[n-1]G[n-1] = C[n-1] The seed generating circuit SG is a modified
LFSR. The theory stated that the conventional LFSR’s outputs can’t be taken as the seed directly
because some seeds may share the same vectors. So the seed generator circuit should make sure
that any two of the signal input changing sequences do not share the same vectors or share as few
vectors as possible. The final test patterns are implemented as following logic.
V[0] = S[0] XOR G[0]
V[1] = S[1] XOR G[1]
V[2] = S[2] XOR G[2]
…
V[n-1] = S[n-1] XOR G[n-1]
The Seed Generator’s clock will be TCK/2m due to the control signal. As SICG’s cyclic
sequences are single input changing patterns, the XOR result of the sequences and a certain
vector must be a single input changing sequence too. The circuit structure of single input
changing generator (SICG), consists of an n-bit counter and a Gray code encoder. The n-bit
counter consists of n D flip-flops and the gray encoder consists of n-1 exclusive-OR gates.
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BLOCK DIAGRAM DESCRIPTION:
2.1 Linear Feedback shift Register (LFSR):
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its
previous state. The most commonly used linear function of single bits is XOR. Thus, an LFSR is
most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the
overall shift register value.
The initial value of the LFSR is called the seed, and because the operation of the register is
deterministic, the stream of values produced by the register is completely determined by its
current (or previous) state. Likewise, because the register has a finite number of possible states, it
must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback
function can produce a sequence of bits which appears random and which has a very long cycle.
.
Linear feedback shift registers make extremely good pseudorandom pattern generators. When the
outputs of the flip-flops are loaded with a seed value (anything except all 0s, which would cause
the LFSR to produce all 0 patterns) and when the LFSR is clocked, it will generate the test
patterns necessary for the clock and a pseudorandom pattern of 1s and 0s.
2.1.1 Circuit Diagram
FIG. LINEAR FEED BACK SHIFT REGISTER
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2.2 GRAY CODES:
A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by
1. The term Gray code is often used to refer to a "reflected" code, or more specifically still, the
binary reflected Gray code. Code is a symbolic representation of discrete information. Codes are
of different types. Gray Code is one of the most important codes. It is a non-weighted code
which belongs to a class of codes called minimum change codes. In this codes while traversing
from one step to another step only one bit in the code group changes. In case of Gray Code two
adjacent code numbers differs from each other by only one bit. The idea of it can be cleared from
the table given below:
Decimal Number Binary Code Gray Code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
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To convert a binary number d_1d_2...d_(n-1)d_n to its corresponding binary reflected Gray
code, start at the right with the digit d_n (the nth, or last, digit). If the d_(n-1) is 1, replace d_n
by 1-d_n; otherwise, leave it unchanged. Then proceed to d_(n-1). Continue up to the first digit
d_1, which is kept the same since d_0 is assumed to be a 0. The resulting number g_1g_2...g_(n-
1)g_n is the reflected binary Gray code.
2.2.1 Circuit Diagram:
2.2.2 Advantages of gray codes:
power consumption and decoding logic is less
Helps to reduce the digital noise issue for counter application.
used as a counter, changes only one bit, so it is glitch free
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CHAPTER 4
SOFT WARE TOOLS
This Chapter deals with the Software tools used in this Application
4.1 XILINX SOFTWARE:
Xilinx ISE(Integrated Software Environment) is a software tool produced by Xilinx for Synthesis
and analysis of HDL designs ,enabling the developer to synthesize(“compile”) their designs,
perform timing analysis ,examine RTL diagrams, simulate a design’s reaction to different
stimuli, and configure the target device with the programmer
4.2 Steps to write program in Xilinx on VHDL environment
Create New project from File menu
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Give the file name
Select options as shown below
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Press Next two times in the follow-up window and then finish at last
Select New source by clicking on project in source window as shown below
Select VHDL module and name the file .Then click next
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Give port declaration as we do in entity .Then click Next and then hit Finish
VHDL Code with entity and libraries are present on the screen, Now we just have to
write the code in architecture
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Select New Source by clicking on the project in Source script and then select Test Bench
waveform and name the file .Then click Next and then select the file for which u would
like to write the test bench and then finish
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A new window appears as shown below .For combinational circuits select combinational
clock
Change the source type to behavioral in the source box and from the process window
simulate the file
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The simulation output is observed at last
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CHAPTER-5
IMPLEMENTATION
In our project we are going to implement test pattern generator by using LFSR . The power
dissipation of the test pattern generator mainly depends on the switching activities. So mainly we
concentrate on reducing the switching activities from one pattern to the other pattern. We in our
project are going to implement 8 bit pattern generator.
8 BIT PATTERN GENERATOR:
An 8bit pattern generator is used to generate 8bit single bit changing output. We are going to
implement 8bit lfsr , 8bit gray code counter, along with clock gating circuit for this pattern
generation. LFSR generate a random pattern for every clock pulse depending on the input seed.
Whenever the seed is changed the LFSR patterns differs from the previously generated patterns.
Gray code counter is used for generation of single bit changing sequences. These are generated
from the binary count value. The clock gating circuitry is a clock enabling circuit which provides
the clock input to the LFSR. This clock is activated for every 256 clock pulses. Thus LFSR
generates a pattern for every 256 clock pulses .this is a low power technique for generating Low
power TPG using lfsr. The output of lfsr is Ex-ored with the gray code counter which in turn
generates a random single bit changing pattern. In similar way we generate another 8bit pattern
by changing seed of the LFSR.
Aurora’s Technological and Research Institute ECE Department