Lic Manual final

IFET COLLEGE OF ENGINEERING

VILLUPURAM

DEPARTMENT OF

ELECTRICAL & ELECTRONICS ENGINEERING

LABORATORY MANUAL

EE2258 LINEAR AND DIGITAL INTEGRATED CIRCUITS

LABORATORY

IV - SEMESTER EEE

PREPARED BY

G. LAVANYA M.E

Assistant Professor

Department of Electrical and Electronics Engineering

S.No DATE EXPERIMENTS PAGE NO MARKS SIGNATURE

1 Study of basic digital IC’S

2 Implementation of Boolean functions, adder/ subtractor circuits

3(a)Code converters, parity generator and parity checking, excess-3,2s complement, binary to gray code using IC’s

3(b) Encoders and decorders

4Counters: design and implementation of 4-bit modulo counters as synchronous and asynchronous types.

5Shift registers: design and implementation of 4-bit shift registers in SISO,SIPO,PISO,PIPO

6 Study of 4:1 multiplexer, 1:4 demultiplexer

7Timer IC application:Study of SE/NE 555 timer in Astable, Monostable Operation

8

Application of Op-Amp:Slew rate verifications, inverting and non-inverting amplifier, adder, comparator, integrator, differentiator

9Study of analog to digital converter and digital to analog converter: verification of A/D conversion.

10

Study of VCO and PLL IC’s:i)voltage to frequency characteristics of NE/SE 566ICii)frequency multiplication using NE/SE 565 PLL IC

INDEX

EE 2258 INTEGRATED CIRCUITS LABORATORY

AIMTo study various digital & linear integrated circuits used in simple system

configuration.

1. Study of Basic Digital IC’s.(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF)

2. Implementation of Boolean Functions, Adder/ Subtractor circuits.

3. (a)Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to grey code using suitable IC’s.(b)Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s.

4. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF IC’s and specific counter IC.

5. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s.

6. Multiplex/ De-multiplex : Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer

7. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation.

8. Application of Op-Amp-I. Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrater and Differentiator.

9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated IC’s.

10. Study of VCO and PLL ICs.Voltage to frequency characteristics of NE/ SE 566 IC.Frequency multiplication using NE/SE 565 PLL IC.

DETAILED SYLLABUS

1. Study of Basic Digital IC’s.(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF)

Aim To test of ICs by using verification of truth table of basic ICs. Exercise

1. Breadboard connection of ICs with truth table verification using LED’s.

2. Implementation of Boolean Functions, Adder/ Subtractor circuits.(Minimization using K-map and implementing the same in POS, SOP from using basic gates)

Aim Minimization of functions using K-map implementation and combination

circuit. Exercise

1. Realization of functions using SOP, POS, form.2. Addition, Subtraction of atleast 3 bit binary number using basic gate IC’ s.

3a) Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to grey code using suitable IC’s . Aim Realizing code conversion of numbers of different bar. Exercise

1. Conversion Binary to Grey, Grey to Binary; i. 1’s. 2’s complement of numbers addition, subtraction,

2. Parity checking of numbers using Gates and with dedicated IC’s

3b) Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO,PISO,PIPO modes using suitable IC’s.

Exercise 1. Decimal to binary Conversion using dedicated IC’s.2. BCD – 7 Segment display decoder using dedicated decoder IC& display.

4. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF IC’s and specific counter IC

Aim Design and implementation of 4 bit modulo counters.

Exercise1. Using flipflop for up-down count synchronous count.2. Realization of counter function using dedicated ICs.

5. Shift Registers. Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s. Aim

Design and implementation of shift register.Exercise 1. Shift Register function realization of the above using dedicated IC’s

a. For SISO, SIPO, PISO, PIPO, modes of atleast 3 bit binary word. 2. Realization of the above using dedicated IC’s.

6. Multiplex/ De-multiplex Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer

Aim To demonstrate the addressing way of data channel selection for multiplex De-

multiplex operation. Exercise

1. Realization of mux-demux functions using direct IC’s2. Realization of mux-demux using dedicated IC’s for 4:1, 8:1, and vice versa.

7. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation.

Aim To design a multi vibrator circuit for square wave and pulse generation.

Exercise1. Realization of Astable multi vibrator & mono stable multi vibrator circuit using

Timer IC.2. Variation of R, C, to vary the frequency, duty cycle for signal generator.

8. Application of Op-Amp-ISlew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrater and Differentiator.

Aim

Design and Realization of Op-Amp application.

Exercise1. Verification of Op-Amp IC characteristics.2. Op-Amp IC application for simple arithmetic circuit.3. Op-Amp IC application for voltage comparator wave generator and wave shifting

circuits.9. Study of Analog to Digital Converter and Digital to Analog Converter:

Verification of A/D conversion using dedicated IC’s.

Aim Realization of circuit for digital conversions.

Exercise1. Design of circuit for analog to digital signal conversion using dedicated IC’s.2. Realization of circuit using dedicated IC for digital analog conversion.

10. Study of VCO and PLL Ics i) Voltage to frequency characteristics of NE/ SE 566 IC. ii) Frequency multiplication using NE/SE 565 PLL IC.

Aim Demonstration of circuit for communication application

Exercise1. To realize V/F conversion using dedicated IC’s vary the frequency of the

generated signal.To realize PLL IC based circuit for frequency multiplier, divider.

AIM:

To verify the truth table for AND, OR, EXOR, NOT, NOR, NAND and JK, RS, D, T

Flip Flops.

APPARATUS REQUIRED:

Digital Trainer Kit.

Connecting wires.

COMPONENTS REQUIRED:

IC 7408, IC 7404, IC 7432, IC 7486, IC 7400, IC 7402 and IC 7410.

PROCEDURE:

1. Connections are made as per the pin/logic diagrams.

2. Truth tables are verified.

PIN DIAGRAMS AND TRUTH TABLES:

ANDC= A.B

A B C

0 0 0

0 1 0

1 0 0

1 1 1

14

13 12 11 10 9 8

1 2 3 4 5 6 7

GND

I C 7408

Vcc

Ex. No. 1Date : STUDY OF BASIC DIGITAL ICS

OR C= A+B

NOT B=A

A B C

0 0 0

0 1 1

1 0 1

1 1 1

A B

0 1

1 0

14

13 12 11 10 9 8

9 8

1 2 3 4 5 6 7

GND

I C 7432

Vcc

Vcc

13 12 11 10 9 8

1 2 3 4 5 6 7 GND

I C 7404

14

Ex- OR C=AB

NAND C = A . B

A B C

0 0 0

0 1 1

1 0 1

1 1 0

A B C

0 0 1

0 1 1

1 0 1

1 1 0

Vcc

14 13 12 11 10 9 8

1 2 3 4 5 6 7

GND

I C 7486

14

13 12 11 10 9 8

1 2 3 4 5 6 7

GND

I C 7400

Vcc

1 2 3 4 5 67

14 13 12 11 10 9 8

GND

I C 7402

Vcc

NOR C=A +B

LOGIC DIAGRAMS AND TRUTH TABLES:

JK FLIP FLOP:

A B C

0 0 1

0 1 0

1 0 0

1 1 0

Clk R S Q

0

1

0

1

0

0

1

1

NC

1

0

Toggle

J

K

CLK

Q

Q

RS FLIP FLOP:

D FLIP FLOP:

Clk R S Q

0

0

1

1

0

1

0

1

NC

1

0

Race

Clk D Q

0

1

0

1

S

R

CLK

Q

Q

CLK

D

Q

Q

T – FLIP FLOP

RESULT:

Thus the truth table for AND, OR, EXOR, NOT, NOR, NAND gates and JK, RS, D, T

Flip Flops are verified.

Clk T Q

0

1

NC

Complement

T

CLK

Q

Q

AIM:

(a) To minimize Boolean functions using K-map and to implement the same in

POS and SOP forms using basic gates.

(b) To implement Half Adder, Full Adder, Half Subtractor and Full Subtractor

Circuits.

APPARATUS REQUIRED:

Digital Trainer Kit.

Connecting wires.

COMPONENTS REQUIRED:

IC 7408, IC 7432, IC 7404 and IC 7486.

PROCEDURE:

1. The logic circuit is designed using K map.

2. Gates are decided for the logic circuit.

3. Connections are made as per the logic diagrams.

4. Truth tables are verified.

(a) MINIMIZATION OF BOOLEAN FUNCTION AND TO IMPLEMENT IN SOP

AND POS FORMS F= ∑m(2,3,5,7,9,11,12,13,14)

SOP:

CD

AB00 01 11 10

00 1 1

01 1 1

11 1 1 1

101

1

F= AB C + A B D + A BD + A BC + A B D

Ex. No. 2

Date :IMPLEMENTATION OF BOOLEAN FUNCTIONS

TRUTH TABLE:

Inputs OutputA B C D F

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0011010101011110

LOGIC DIAGRAM:

A B C D

F

POS:

TRUTH TABLE:

Inputs OutputA B C D F

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0011010101011110

CD

AB

0001 11 10

00 0 0

01 0 0

11 0

100 0

F= AB C + A B D + A BD + A B C D

F=(A+B+C).(A+B + D).(A + B+D). (A+B+C+D)

LOGIC DIAGRAM:

A B C D

A+B+C+D

A+B+D

A+B+D

A+B+C

(A+B+C+D) (A+B+D)

(A+B+D) (A+B+C)

F

(b) IMPLEMENTATION OF HALF ADDER, FULL ADDER, HALF SUBTRACTOR AND FULL SUBTRACTOR CIRCUITS

Half Adder: Block Diagram:

Sum: Carry:

Inputs Outputs

A B Sum Carry

0

0

1

1

0

1

0

1

0

1

1

0

0

0

0

1

0 0

0 1

0 1

1 0

Carry

Sum

B

AHA

Sum = (AB +A B) = A B Carry = A. B

B 0 1

0

1

A

0

1

B 0 1A

Sum = A B

Carry = A.B

A B

Full Adder: Block Diagram:

Sum: Carry:

Inputs Outputs

A B C Sum Carry

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

11

1 1

1

11

1

Expression = AB + C(A + B)

0

1

Expression = A + B + C

FA

C

A

B

Sum

Carry

B C 00 01 11 10A

0

1

0

B C 00 01 11 10A

0

1

0

Sum = A B CCarry = AB + C(A + B)

Sum= A B C

A B C

C(A+B)A+B

AB

Carry = AB + C(A+ B)

A B

Half Subtractor: Block Diagram:

Difference: Borrow:

Inputs Outputs

A B Diff Borr

0

0

1

1

0

1

0

1

0

1

1

0

0

1

0

0

0 1

1 0

0 1

0 0

Borr

Diff

B

AHS

Diff = (AB +A B) = A B Borr= A. B

B 0 1

0

1

A

0

1

B 0 1A

Difference = A B

Borrow = A.B

A B

Full Subtractor: Block Diagram:

Difference: Borrow:

Inputs Outputs

A B C Diff Borr

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

1

1

1

0

0

0

1

11

1 1

11 1

1

FS

C

A

B

Diff

Borr

0

1

B C 00 01 11 10A

0

1

0

B C 00 01 11 10A

0

1

0

Sum = A B CCarry = AB + C(A + B)

RESULT:

(a) Thus minimization of Boolean functions using K-map is performed and same

is implemented in POS and SOP forms using basic gates

(b) Thus Half Adder, Full Adder, Half Subtractor and Full Subtractor Circuits are

implemented.

C B A

Difference

Borrow

AIM:

To construct logic diagram and to verify the truth table for

(a) Binary to Gray code Converter

(b) Gray to Binary code converter

(c) Odd Parity Generator

(d) Odd Parity Checker

(e) Even Parity Generator

(f) Even Parity Checker

APPARATUS REQUIRED:

Digital Trainer Kit

Connecting wires

COMPONENTS REQUIRED:

IC7404, IC 7432, IC 7408, IC 7486 and IC 7411

PROCEDURE:

The logic circuit is designed using K map.

Gates are decided for the logic circuit.

Connections are made as per the logic diagrams.

Truth tables are verified.

Ex. No. 3.a

Date :CODE CONVERTERS, PARITY GENERATOR, PARITY CHECKER

(a) BINARY TO GRAY CODE CONVERTER

TRUTH TABLE:

Binary code Gray code

B1 B2 B3 B4 G1 G2 G3 G4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

K Map

G1:

B3B4

B1B2

00 01 11 10

00

01

11 1 1 1 1

10 1 1 1 1

G1 = B1

G2:

B3B4

B1B2

00 01 11 10

00

01 1 1 1 1

11

10 1 1 11

G3:

B3B4

B1B2

00 01 11 10

00 1 1

01 1 1

11 1 1

101 1

G4:

B3B4

B1B2

00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

G2 = B1 B2

G3 = B2 B3

G4 = B3 B4

LOGIC DIAGRAM:

(b) GRAY TO BINARY CODE CONVERTER:

TRUTH TABLE:

Gray code Binary code

G1 G2 G3 G4 B1 B2 B3 B4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 1 0

1 0 0 1 1 1 1 1

1 0 1 0 1 1 0 1

1 0 1 1 1 1 0 0

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0

B1 B2 B3 B4

G1

G2

G3

G4

K MAP:B1 : G3G4

G1G2

00 01 11 10

00

01

11 1 1 1 1

10 1 1 1 1

B2:

G3G4

G1G2

00 01 11 10

00

01 1 1 1 1

11

101

1 1 1

B3:

G3G4

G1G2

00 01 11 10

00 1 1

01 1 1

11 1 1

101

1

B4:

B1 = G1

B2 = G1 G2

B3= G1 G2 G3

G3G4

G1G2

00 01 11 10

00 1 1

01 1 1

11 1 1

101 1

LOGIC DIAGRAM:

B4= G1 G2 G3 G4

B1

B2

B3

B4

G1 G2 G3 G4

(c) ODD PARITY GENERATOR:

TRUTH TABLE:

Input Output

A B C P

0 0 0 1

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

K - Map

BCA 00 01 11 10

1 1 1

0 1 1

P = A BC + A B C + AB C + A BC

P = A( BC + BC ) + A( B C )

LOGIC DIAGRAM:

A B C

(d) ODD PARITY CHECKER

TRUTH TABLE:

Inputs Output

A B C D(P) P

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

0

1

1

0

0

1

1

0

1

0

0

1

K Map

CD

AB00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

P = (A+B+ C+D)’

LOGIC DIAGRAM:

(e) EVEN PARITY GENERATOR:

TRUTH TABLE:

Input Output

A B C P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

K MAP:

P = A B C

BC

A00 01 11 10

0 1 1

1 1 1

A B C D

P

LOGIC DIAGRAM:

(f) EVEN PARITY CHECKER:

TRUTH TABLE:

Inputs Output

A B C D(P) P

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

A B C

P

K MAP:

CD

AB00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

P = A B C D

LOGIC DIAGRAM:

RESULT:

Thus the logic diagrams are constructed and truth tables are verified for

a) Binary to Gray code Converter

b) Gray to Binary code converter

c) Odd Parity Generator

d) Odd Parity Checker

e) Even Parity Generator

f) Even Parity Checker

A B C D

P

AIM:To construct logic diagram and to verify the truth table for Encoder and decoders

APPARATUS REQUIRED:

Digital Trainer Kit

Connecting wires

COMPONENTS REQUIRED:

IC7404, IC 7432, IC 7408, IC 7486 and IC 7411

PROCEDURE:

The logic circuit is designed using K map.

Gates are decided for the logic circuit.

Connections are made as per the logic diagrams.

Truth tables are verified.

8 TO 3 LINE ENCODER:

TRUTH TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Ex. No. 3.b

Date :ENCODERS AND DECODERS

LOGIC DIAGRAM:

(h) 3 TO 8 LINE DECODER:

TRUTH TABLE:

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

LOGIC DIAGRAM:

D0 D1 D2 D3 D4 D5 D6 D7

X

Y

Z

D0 = x’y’z’

RESULT:

Thus the logic diagrams are constructed and truth tables are verified for

a) 8 to 3 line Encoder

b) 3 to 8 line Decoder

X

Y

ZD1 = x’y’z

D2= x’yz’

D3= x’yz

D4= xy’z’

D5 xy’z

D6= xyz’

D7= xyz

AIM:

To design and implement 4 bit Synchronous mod-10 Counter Asynchronous Up

Counter using JK flip flops.

APPARATUS REQUIRED:

Digital Trainer Kit

Connecting wires.

COMPONENTS REQUIRED:

IC 7408 and IC 7476.

PROCEDURE:

The logic circuit is designed using K map.

Gates are decided for the logic circuit.

Connections are made as per the logic diagrams.

Truth tables are verified.

Ex. No. 4

Date :COUNTERS

PIN DIAGRAM:

JK FLIP FLOP:

CLKSOURCE

2

16

15

14

LED

330

LED

3301

4

Vcc = 5V

2.2K2.2K

3

Vcc = 5V

Pr

J Q

½ 7476

_K Q

Cr

a) SYNCHRONOUS MOD-10 COUNTER

STATE TABLE:

Present State Next State Flip Flop Inputs

A B C D A+ B+ C+ D+ JA KA JB KB JC KC JD KD

0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X

0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1

0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X

0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1

0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X

0 1 0 1 0 1 1 0 0 X X 0 1 X X 1

0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X

0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1

1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X

1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1

K MAP:

JA :CD

AB00 01 11 10

00

01 1

11 X X X X

10 X X X X

KA :CD

AB00 01 11 10

00 X X X X

01 X X X X

JA = BCD

11 X X 1 X

10 X X X

JB :

CD

AB00 01 11 10

001

01 X X X X

11 X X X X

10 X X

KB :

CD

AB00 01 11 10

00X

XX

X

01 1

11 X X X X

10 X X X X

JC :

CD

AB00 01 11 10

001

X X

01 1 X X

11 X X X X

10 X X XX

KC :

KA = D

JB = CD

KB = CD

JC = D

CD

AB00 01 11 10

00X X

1

01 X X 1

11 X X X X

10 X X XX

JD :

CD

AB00 01 11 10

00 1 X X 1

01 1 X X 1

11 X X X X

10 X X XX

KD :

CD

AB00 01 11 10

00 X

1 1 X

01 X 1 1 1

11 X X X X

10 X 1 X X

KC = D

JD = 1

KD = 1

LOGIC DIAGRAM:

HIGH

JD D

KD D

KA QA

JC C

KC C

KA QA

JB B

KB B

KA QA

JA A

KA A

KA QA

CLK

D C BA

b) ASYNCHRONOUS UP COUNTER:

STATE TABLE:

Present State Next State

A B C D A+ B+ C+ D+

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 1 0 1 0

1 0 1 0 1 0 1 1

1 0 1 1 1 1 0 0

1 1 0 0 1 1 0 1

1 1 0 1 1 1 1 0

1 1 1 0 1 1 1 1

1 1 1 1 0 0 0 0

LOGIC DIAGRAM:

CLK

J Q

CLK

K Q

J Q

CLK

K Q

J Q

CLK

K Q

J Q

CLK

K Q

+5V

AB C D

TIMING DIAGRAM:

RESULT:

Thus the Synchronous and Asynchronous Counters are designed and

implemented.

B

C

D

A

CLK

0 0 0 0 0 0 0 01 1 1 1 1 1 1 1

0 0 0 0 0 0 0 01 1 1 11 1 1 1

0 00 00 0 0 0

1 1 1 1 1 1 1 1

0 0 00

0 0 0 01 1 1 1 1 1 1 1

AIM:

To design and implement 4-bit shift registers in SIPO, PISO modes using suitable

ICs.

APPARATUS REQUIRED:

Digital Trainer Kit.

Connecting wires.

COMPONENTS REQUIRED:

IC 7474, IC 7408, IC 7432 and IC 7404.

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Input is given to the gates and flips flops.

3. Output is obtained and the truth table is verified.

PIN DIAGRAM:

D FLIP FLOP:

1/6 7404

CLKSOURCE

2

16

15

14

LED

330

LED

330

D 4

3

1

Vcc = 5V

Pr

J Q

½ 7476

_K Q

Cr

Ex. No. 5

Date :SHIFT REGISTERS

(a) SERIAL IN PARALLEL OUT (SIPO):

Data

Input CLK QA QB QC QD

0

1

1

0

1

1

1

1

0

1

1

0

1

0

1

1

1

1

0

1

1

1

1

0

LOGIC DIAGRAM:

(b)PARALLEL IN SERIAL OUT (PISO):

SHIFT CLK A B C D QD

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

1

0

1

0

95 12

QCQBQA

CLKSOURCE

9 25 12SERIAL

INPUT 2

3

D QA

7474

clk 3

D QA

7474

clk 111

D QA

7474

clk11

D QA

7474

clk

QD

LOGIC DIAGRAM:

RESULT:

SHIFTINPUT

9QD

12QA

CLKSOURCE

7414

2

3

D

7474

clk11

D QA

7474

clk3

D QA

7474

clk11

D QA

7474

clk

QA

5

3

621

3

5421

5 12

6

1154

8

1213910

QA

5 12

3

6910

3

5421

PARALLEL INPUTS

Thus 4-bit shift registers in SIPO, PISO modes using suitable ICs are designed and

implemented.

AIM:

To construct the logic diagram and verify the truth table for

(a) 2:1 Multiplexer

(b) 1: 2 De multiplexer

(c) 4:1 Multiplexer.

(d) 1: 4 De multiplexer.

APPARATUS REQUIRED:

Digital trainer kit

Connecting Wires.

COMPONENTS REQUIRED:

IC 7408, IC 7404, IC 7486 and IC 7432.

PROCEDURE:

1. Connections are made as per the logic diagram.

2. The truth tables are verified.

a) 2: 1 MULTIPLEXER:

S0 O/P

0

1

I0

I1

0

1

I0

I1

O/P

S0

Ex. No. 6

Date :MULTIPLEXER AND DEMULTIPLEXER

LOGIC DIAGRAM:

b) 1: 2 DE MULTIPLEXER:

LOGIC DIAGRAM:

S0 I/P

at

0

1

O0

O1

I1

S0

I0 1

6

5

4

2

3IC 7408

IC 7408

IC 7432

O/P

0

1

O0

O1

I/P

S0

7404 3

I / P

S0

1

6

5

4

2

IC 7408

IC 7408

O1

O0

c) 4: 1 MULTIPLEXER:

LOGIC DIAGRAM:

S0 S1 O/P

0

0

1

1

0

1

0

1

I0

I1

I2

I3

01

10

11

00

O/P

I0

I1

I2

I3

S0 S1

So S1

I0

I1

I2

I3

IC7408

IC7486

IC7432

O/P

d) 1:4 DE MULTIPLEXER:

LOGIC DIAGRAM:

RESULT:

Thus logic diagrams are constructed and truth tables are verified for

(a) 2:1 Multiplexer

(b) 1: 2 De multiplexer

(c) 4:1 Multiplexer.

(d) 1: 4 De multiplexer.

I/P S0 S1 O0 O1 O2 O3

1

0

0

0

0

X

0

0

1

1

0

0

1

0

1

0

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

1

01

10

11

00

I/P

O0

O1

O2

O3

S0 S1

So S1

O0

O1

O2

O3

IC7408

I/P

AIM:

(a) To design and obtain the Mono stable multivibrator using IC555 timer for the

given time period, T= 5 sec.

(b) To design and obtain the Astable multivibrator using IC555 timer for the

given time period.

APPARATUS REQUIRED:

S.No. Items Range Quantity

1 IC555 1

2 Resistor 10KΩ,330Ω 1

3 Capacitor 470µF,0.01µF 1

4 RPS (0- 30)V 1

5 CRO 1

6 Bread Board 1

7 Connecting Wires

PROCEDURE:

1. Connections are made as per the Circuit diagram.

2. The trigger input is given to pin2 and the output voltage Vo is observed at

pin6.

3. Voltage across the capacitor Vc is measured, with the help of CRO.

PIN DIAGRAM:

Threshold

Discharge

Control Voltage

VCCGround

Trigger

Output

Reset

1

2

3

4

8

7

6

5

IC 555

Ex. No. 7

Date :STUDY OF 555 TIMER

a) MONOSTABLE MULTIVIBRATOR:

DESIGN:

Given T = 5 sec. T = 1.1 RC

Assume C = 470 F

5 = 1.1 R ( 470 x 10 -6 )

R = 9.6 K = 10 K .

CIRCUIT DIAGRAM:

TRIGGERINPUT

R =10kΩ

330Ω

7

0.01µF

470µF

5 1

CRO

+Vcc=5V

IC555

5

8

2 4

63

TABULAR COLUMN:

S.NO.VOLTAGE

(VOLTS)

CHARGING TIME

TC (SEC)

DISCHARGING TIME

TD (SEC)

MODEL GRAPH:

b) ASTABLE MULTIVIBRATOR:

0V

0V

VO

VCC

2/3VC

C

VC

RA = 10KΩ

RB = 4.5KΩ

C = 470µFLED

330Ω

0.01µF

7 4 8 3

IC555

CRO

Vcc= 5V

TABULAR COLUMNS:

S.No.VOLTAGE

(VOLTS)

TON

(mS)

TOFF

(mS)

S.No.V1

(VOLTS)

V2

(VOLTS)

TC

(mS)

TD

(mS)

MODEL GRAPH:

RESULT:

Thus the Mono stable multivibrator and Astable multivibrator using 555 timer

for the given time period was designed and waveforms are obtained.

T (ms)VO

(Volts)

2/3VCC

1/3VCC

T (ms)

AIM:

(a) To measure the following characteristics of Op-Amp IC 741: (i) Input bias

current (ii) Input offset current (iii) Input offset Voltage (iv) Slew rate.

(b) To design and test the operation of Inverting amplifier.

(c) To design and test the operation of Non-inverting amplifier.

(d) To design and test the operation of summing amplifier.

(e) To design and test the operation of Integrator.

(f) To design and test the operation of Differentiator.

(g) To design and test the operation of Comparator.

APPARATUS REQUIRED:

S.No. Name of the Item Range Qty

1 IC 741 1

2 Resistors 1M,1k,10K,100,2.5K,5.2K 2

3 Capacitors .01F,.005F 2

4 Dual Power Supply 1

5 RPS 1

6 Function Generator 1

7 CRO 1

8 Bread Board 1

9 Connecting Wires Few

PROCEDURE:

Ex. No. 8

Date :APPLICATIONS OF OP-AMP

1. The connections are made as per the circuit diagram.

2. The inputs are given and the outputs are observed from CRO.

3. In case of slew rate the input sine wave signal is adjusted so that the output is in

peak time wave of 1 KHz, the frequency of the input is then increased until the

output is diminished.

4. In case of comparator, the reference voltage Vref is varied and the corresponding

change in the waveforms are observed.

PIN DIAGRAM:

(a) CHARACTERISTICS OF OP-AMP:

Input Offset Current:

Observation:

Input Offset Current:

Vo

Ios = = Rf

R1 = 1M

0.01f

Cf = 0.01f

Vo6

4

72

V-

V+

IC 741

3

Rf = 1M

-

Output

+Vcc

Offset

NCOffset

Input

Gnd

-Ve

1

2

3

4

8

7

6

5

Input Offset Voltage:

Slew Rate:

Measure the Output Voltage using CRO.

Vo = …………….. Volts

Vo

Vos = = ………….. Volts Rf

Rcomp

=100

0.01f4

7

2

3

V-

V+

IC 741

Vo

R1= 100

Rf= 10 K

RL = 10 K

Vo6

4

72

V-

V+

A 741

3

Measure the Magnitude and Frequency of the Output Voltage using CRO.

F = …………….. Hz

Vm = ……………. V

SR = ( 2 f Vm ) / 106 Volts / sec.

Inverting Input Bias Current:

Non Inverting Input Bias Current

Measure the Output Voltage using CRO.

Vo = …………….. Volts

Vo

IB + = = …………..nA Rf

Cf = 0.01f

Vo6

4

72

V-

V+

IC 741

3

Rf = 1M

Measure the Output Voltage using CRO.

Vo = …………….. Volts

Vo

IB - = = …………..nA Rf

Rf = 1MCf = 0.01f

Vo6

4

72

V-

V+

IC 741

3

b) INVERTING AMPLIFIER:

CIRCUIT DIAGRAM:

IC 741

TABULAR COLUMN:

DC INPUT:

Vin

(VOLTS)

THEORETICAL OUTPUT

(VOLTS)

PRACTICAL OUTPUT

(VOLTS)

AC INPUT:

SignalGenerator

Rcomp=1kΩ

CRO

+15V

-15V

Rf =10kΩ

Rin =1kΩ

V0= [-Rf/Rin] Vi

-

+Vi

Vin

(VOLTS)

Tin

(ms)

V0

(VOLTS)

T0

(ms)

MODEL GRAPH:

Vin

(Volts)

Vo

(Volts)

t (ms)

t (ms)

c) NON INVERTING AMPLIFIER:

CIRCUIT DIAGRAM:

IC 741

TABULAR COLUMN:

DC INPUT:

Vin

(VOLTS)

THEORETICAL OUTPUT

(VOLTS)

PRACTICAL OUTPUT

(VOLTS)

CRO

~

+15V

-15V

Rf =5.6kΩ

Rin =1kΩ

SignalGenerator

V0= [1+Rf/Rin]+

-

AC INPUT:Vin

(VOLTS)

Tin

(mS)

V0

(VOLTS)

T0

(mS)

MODEL GRAPH:

Vin

(Volts)

Vo

(Volts)

t (ms)

t (ms)

d) SUMMING AMPLIFIER

DESIGN:

Vo/Rf =-[ V1/R1 +V2/R2 +V3/R3 ]

If R1 = R2= R3 =Rf

Then Vo= - [V1 +V2 + V3] and

Rcomp =R1 || R2 || R3|| Rf

If R1 = R2= R3 =Rf = 10 K ,then R comp =2.5 K

CIRCUIT DIAGRAM:

TABULAR COLUMN :

Wave form Amplitude (v) Time (mS)

Sine I/P

O/P

V3

V2

V1

R3=10k

Rcomp=2.5k

Vo6

4

72

V-

V+

IC 741

3

Rf =10k

R2=10 k

R1=10 k

MODEL GRAPH:

V2

Vm

t

Vm

t

Vm

V3

3Vm

tV0

t

V1

e) INTEGRATOR:

DESIGN:

In an integrator circuit, Fa = Fb/10 where Fa is the frequency of the periodic

signal and Fb is the break frequency, assuming the values Fa= 1khz, Rf=10K, Fb= 10Khz,

R1 = 1 K

From which

Fa=1/ (2 Rf Cf) = Cf = 1/(2 R1 Fa) => Cf = 0.015f

Fb = 1(2 R1 Cf )= R1 = 1(2 Fb Cf) => R1 = 1.06K

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Wave form Amplitude (v) Time (mS)

Sine I/P O/P

Square I/P

O/P

Cf = 0.015f

Rf = 10K

Vo6

4

R1 = 1K72

V-

V+

IC 741

3

MODEL GRAPH:

f) DIFFERENTIATOR:

DESIGN:

Fb=20 Fa, selecting C1 =0.1 F (C<1F) and Fa = 1KHZ then Fb= 20KHZ

From which

Fa = 1/(2 Rf C1) = Rf = 1/(2 Fa C1) = Rf= 1.5 K

Fb = 1(2 Rf Cf) = Cf = 1/(2 Fb Rf) = Cf= 0.005F

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Cf = 0.01f Vo6

4

R1 = 1K7

2

V-

V+

IC 7413

Rf = 1.5K

Cf = 0.005f

Vi

(volts)

V0

(volts)

t(ms)

t(ms)

Vi (volts)

Vo (volts)t(ms)

t(ms)

Wave formAmplitude(v) Time (mS)

Sine I/P

O/P

Square I/P

O/P

MODEL GRAPH:

g) COMPARATOR:

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Vi

(volts)

V0

(volts) t(ms)

t(ms)

Vi (volts)

Vo (volts) t(ms)

t(ms)

+

-R =1K Ω

R =1K Ω RL=10K Ω

Vo

Vi

Vref

Wave form Amplitude(v) Time (mS)

Sine I/P

O/P

MODEL GRAPH:

RESULT:

Thus the characteristics and applications of Op-Amp IC 741 are verified.

Vm

Vref

0V

0V

t

t

AIM:

(a) To construct a circuit using successive approximation ADC(ADC0804) to

convert the analog voltage into its digital equivalent.

(b)To design a 3 bit R-2R resistor DAC using Op-Amp.

(a) ANALOG TO DIGITAL CONVERTER:

APPARATUS REQUIRED:

PROCEDURE:

1. Connections are given as per the circuit diagram

2. In this circuit ADC is connected in free running mode.

3. Initially the conversions are started by connecting signal w R signal momentarily

to ground.

4. The digital outputs are observed by means of LEDS for various pot positions and

are noted down.

COMPUTATION:

For an n bit ADC

Step size = Vref / pot (2,n)

For a 8 bit ADC with

Vref = +5v

S.No. Items Range Type Quantity

1 Resistor 10KΩ 1

2 Capacitor 150pf 1

3 Pot 10KΩ 1

4 LEDS 8

5 ADC IC 0804 1

6 Bread Board 1

7 Connecting wires

Ex. No. 9

Date :STUDY OF ANALOG TO DIGITAL & DIGITAL TO ANALOG CONVERTER

CIRCUIT DIAGRAM:

C1 = 150pF

R1 = 1K

R2 = 10K

IC 0804

Vin+(6)

Vin-(7)

AGND(8)

+5V

Vreg (9)

CLR (19)

CLK IN (4)

CS(1)

RD(2)

DGND(10)

D0(18)

D1(17)

D2(16)

D3(15)

D4(14)

D5(13)

D6(12)

D7(11)

wR(3)

INTR(5)

INTR

TOLEDs

TABULAR COLUMN:

S.No. ANALOG INPUT BINARY OUTPUT

OUTPUTCOUNT

THEORETICALOUTPUT

(b) DIGITAL TO ANALOG CONVERTER

APPARATUS REQUIRED:

S.No. Name of the Item Range Type Qty

PIN DIAGRAM:

-

Output

+Vcc

Offset

NCOffset

Input

Gnd

-Ve

1

2

3

4

8

7

6

5

DESIGN:

Vo=VR(Rf/R)[ D1 2-1 +D2 2-2 +D3

2-3 ]

PROCEDURE:

1. The connections are given as per the circuit diagram.

2. The input voltages are given according to the circuit.

3. The outputs are observed and plotted.

CIRCUIT DIAGRAM:

TABULAR COLUMN:

INPUT THEORITICAL OUTPUT PRACTICAL OUTPUT

A B C

MODEL GRAPH:

D3

2 K2 K2 K2 K

R2 = 10 K

Vo6

4

72

V-

V+

IC 741

3

Rf = 1 K 1 K 1 K 1 K

-Vref = -7V

D2 D1

Bits

Vo(volts)

000 001 010 011 100 101

RESULT:

Thus the successive approximation ADC are R-2R DAC are designed and

constructed

AIM:

(a) To study about voltage controlled oscillator

(b) To study about Phase locked loop.

(a) VOLTAGE CONTROLLED OSCILLATOR

THEORY:

A common type of VCO available in IC form is sign tics NE/SE 566. It consists

of a timing capacitor CT linearly charged or discharged by a constant current

source/sink. The amount of current can be controlled by changing the voltage Vc applied

at the modulating input (Pin 5) or by changing the timing resistor Rr external to the IC

chip. The voltage at Pin 6 is held at the same voltage as Pin 5. Thus, if the modulating

voltage at Pin5 is measured, the voltage at Pin6 also increases, resulting in less voltage

across R and there by decreasing the changing current.

The voltage across the capacitor CT is applied at the inverting input terminal of

Schmitt trigger A2 via buffer amplifier. The output voltage swing of the Schmitt trigger is

designed to Vcc and 0.5Vcc. If Ra = Rb in the positive feedback loop, the voltage at the non

inverting terminal of A2 swings from 0.5Vcc to 0.25 Vcc.

When the voltage on the capacitor CT exceeds 0.5Vcc during charging the output of

the Schmitt trigger goes low (0-5) Vcc. The capacitor now discharges and when it is at

0.25Vcc the output of Schmitt trigger goes high (Vcc). Since the source and sink currents

are equal, capacitor charges and discharges for, the same amount of the time.

Thus ∆v = 0.25Vcc

∆V = i

∆t CT

Ex. No. 10

Date :STUDY OF VCO AND PLL ICS.

0.25Vcc = i

∆t CT

∆t = 0.25VccCT

i

The frequency of oscillator f0 is

f0 = 1/t

= 1/2∆t

= i

0.5Vcc CT

i = Vcc - Vc

Rt

PIN DIAGRAM:

Ground

Square wave output

Triangular wave output

NC

+Vcc

CT

RT

Modulated input

8

7

6

5

1

4

3

2 NE/SE566VCO

CIRCUIT DIAGRAM:

OUTPUT WAVEFORMS:

Vcc

0.5Vcc

O/P at Pin4

0.5 Vcc

0.25 Vcc

Schmitt trigger O/P

O/P at Pin3

Vcc

0.5Vcc

Modulating input

17

5

6 8

4

3

CT

R2

Rf

+Vcc

Vc

566

R1

b) PHASE LOCKED LOOP

THEORY:

MONOLITHIC PHASE LOCKED LOOP:

All the different building blocks of the PLL are available as independent IC

packages and can be externally interconnected to make a PLL. Moreover a number of

manufacturer have introduced monolithic PLL’s too.

Some of the important monolithic PLL’s are SE/NE 560 series introduced by

signetics and LM560 series by rational semiconductor. The SE/NE 560,561,

562,564,565 and 567 mainly differ in operating frequency range, power supply

requirement, frequency and bandwidth adjustment ranges. Since 565 is the most

commonly used PLL.

565 iss available as 14-Pin DIP Packages and as 10 Pin Metal can package. The

output frequency of the VCO (both inputs 2,3 grounded)

f0 = 0.25/RtCt hz

where Rt and Ct are the external resistor and capacitor connected to Pin8 and Pin 9.

A value between 2KΩ and 20KΩ is recommended for Rt.

The VCO free running frequency is adjusted with Rt and Ct to be at the centre of

the input frequency range.

It may be seen that phase locked loop is internally broken between the VCO

output and the phase comparator input. A short circuit between pins 4 and 5 connects

the VCO output to the phase comparator, so as to compare f0 with input signal fs. A

capacitor C is connected between Pin 7 and Pin 10 to make a low pass filter with

internal resistance of 3.6KΩ.

PIN DIAGRAM:

CIRCUIT DIAGRAM: +Vcc

Vco o/p 4

RT

9

3.6kΩ

C

Phase detector

Amplifier

VCO

i/p 2

i/p 3

i/p 5

-VccVcc

CT

Demodulatedo/p

Ref o/p

8

10

Reference o/p

VCO output

NC

+Vcc

External capacitor for VCO

NC

NC

-Vcc

External resistor for VCO

input

VCO input

Demodulated o/p

input

12

11

10

9

1

4

3

2

NE/SE565

5

87

6

13

14

NC

RESULT:

Thus the voltage controlled oscillator and the phase locked loop are studied.