lg_gsa-4040b

Super Multi DVD DriveS E RVICE MANUALMODEL: GSA-4040B

website http://biz.LGEservice.come-mail http://www.LGEservice.com/techsup.html

P/NO : 3828HS1044AS e p t e m b e r, 2003Printed in Korea

MODEL : GSA-4040B

TABLE OF CONTENTSINTRODUCTION .......................................................................................................................................................................3FEATURES............................................................................................................................................................................3~4SPECIFICATIONS.................................................................................................................................................................5~8LOCATION OF CUSTOMER CONTROLS .........................................................................................................................9~10DISASSEMBLY.................................................................................................................................................................11~12

1. CABINET and CIRCUIT BOARD DISASSEMBLY ..........................................................................................................111-1. Bottom Chassis..........................................................................................................................................................111-2. Front Bezel Assy........................................................................................................................................................111-3. Cabinet and Main Circuit Board .................................................................................................................................11

2. MECHANISM ASSY DISASSEMBLY..............................................................................................................................112-1. Pick-up Unit................................................................................................................................................................112-2. Pick-up ......................................................................................................................................................................12

GLOSSARY.............................................................................................................................................................................16EXPLODED VIEW.............................................................................................................................................................13~14MECHANICAL REPLACEMENT PARTS LIST ......................................................................................................................15THE DIFFERENCES OF CD-R/CD-RW DISCS AND GENERAL CD-ROM...........................................................................17

1. Recording Layer ..............................................................................................................................................................172. Disc Specification ............................................................................................................................................................173. Disc Materials ..................................................................................................................................................................184. Reading Process of Optical Disc .....................................................................................................................................195. Writing Process of CD-R Disc .........................................................................................................................................206. Writing Process of CD-RW Disc ......................................................................................................................................207. Organization of the PCA, PMA and Lead-in Area ...........................................................................................................218. Function of PCA and PMA area ......................................................................................................................................229. OPC and ROPC ..............................................................................................................................................................2210. Writing Process of DISC................................................................................................................................................23

THE DIFFERENCES OF DVD-R/RW, DVD+R/RW DISCS AND DVDD-ROM .......................................................................241. Recording Layer ..............................................................................................................................................................242. Disc Specification ............................................................................................................................................................253. Disc Materials ..................................................................................................................................................................254. Writing Pulse Waveform of DVD+R.................................................................................................................................285. Writing Pulse Waveform DVD+RW .................................................................................................................................306. Organization of Inner Drive Area, Outer Drive Area, Lead-in Zone and Lead-out Zone .................................................31

DVD & CD DATA PROCESSING......................................................................................................................................33~361. Data Processing Flow......................................................................................................................................................332. Copy Protection and Regional Code Management Block ...............................................................................................343. About Prevention the DVD-ROm from to be copy ...........................................................................................................354. About the DVD-ROM Regional Code ..............................................................................................................................36

INTERNAL STRUCTURE OF THE PICK-UP....................................................................................................................37~391. Block Diagram of the Pick-up(HOP-8511T).....................................................................................................................372. Pick up Pin Assignment...................................................................................................................................................383. Signal detection of the P/U..............................................................................................................................................39

DESCRIPTION OF CIRCUIT.............................................................................................................................................40~471. ALPC Circuit ....................................................................................................................................................................402. Focus Circuit....................................................................................................................................................................423. Tracking & Sled Circuit ....................................................................................................................................................434. Spindle Circuit .................................................................................................................................................................43

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION.............................................................................48~73TROUBLESHOOTING GUIDE..........................................................................................................................................74~90BLOCK DIAGRAM ..................................................................................................................................................................92PRINTED CIRCUIT BOARD DIAGRAM ...........................................................................................................................93~96ELECTRICAL REPLACEMENT PARTS LIST........................................................................................................................97

CAUTION - INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM.

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INTRODUCTION

GSA-4040B series *1)Design Specifications

*1)GMA-4040B does not apply to the record function of DVD+R/+RW.GRA-4040B does not apply to the record function of DVD-R/-RW/-RAMGWA-4040B does not apply to the record function of DVD-RAM.GDA-4040B does not apply to the record function of DVD+R/+RW andCD-R/RW.

FEATURES

1 General1) Enhanced IDE (ATAPI) interface.2) Internal Half-height Drive.3) CD-R/RW, DVD-R/RW/RAM/+R/+RW read and write compatible CD Family and DVD-ROM read

compatible.4) Buffer Under-run prevention function embedded.5) 2MB buffer memory.6) Power loading and power eject of a disc. Bare media loading.7) MTBF : 100,000 POH8) Vertical and Horizontal installable.

2. Supported disc formats1) Reads data in each CD-ROM, CD-ROM XA, CD-I, Video CD, CD-Extra and CD-Text.2) Reads data in Photo CD (Single and Multi session).3) Reads standard CD-DA.4) Reads and writes CD-R discs conforming to “Orange Book Part 2”.5) Reads and writes CD-RW discs conforming to “Orange Book Parts 3”.6) Reads data in each DVD-ROM, DVD-R(Ver.1.0, Ver.2.0 for Authoring) and DVD-RAM(Ver.1.0)7) Reads and writes in each DVD-R(Ver.2.0 for General), DVD-RW, DVD-RAM(Ver.2.1), DVD+R and

DVD+RW

This service manual provides a variety of serviceinformation.It contains the mechanical structure of the SuperMulti DVD Drive and the electronic circuits inschematic form. This Super Multi DVD Drive wasmanufactured and assembled under our strictquality control standards and meets or exceedsindustry specifications and standards.This Super Multi DVD drive is an internal drive unitdesigned for use with IBM PC, HP Vectra, orcompatible computer. It can write as much as 700Mbytes of digital data into CD-R/RW disc, and can

read as much as 700 Mbytes of digital data storedin a CD-ROM, CD-R and CD-RW disc.It can write as much as 4.7Gbytes of digital datainto DVD+R/RW disc, and can read as much as4.7Gbytes of digital data stored in a DVD-ROM,DVD-R, DVD-RW, DVD+R and DVD+RW disc.This Super Multi DVD Drive can easily meet theupcoming MPC level 3 specification, and itsEnhanced Intelligent Device Electronics (E-IDE)and ATAPI interface allows Plug and playintegration in the majority of today’s PCs withoutthe need of an additional interface card.

3. Supported write method1) For CD-R/RW

Disc at once, Session at Once, Track at once and Packet Write.2) For DVD-R

Disc at Once and Incremental Recording.3) For DVD-RW

Disc at Once, Incremental Recording and Restricted Overwrite.4) For DVD-RAM

Random Write5) For DVD+R

Sequential Recording6) For DVD+RW

Random Write

4. Performance1) Average access time : CD-ROM 125ms

(1/3 stroke) DVD-ROM 145ms2) Write speed : CD-R 4x, 8x CLV, 16x, 24x ZCAV

CD-RW 4x, 8x, 12x CLV, 16x ZCLV (High Speed CD-RW supported: 8x, 12x, Ultra Speed CD-RW supported: 16x)

DVD-R 1x, 2x, 4x CLVDVD-RW 1x, 2x CLV

DVD-RAM (Ver.2.1) 2x, 3x ZCLVDVD+R 2.4x, 4x CLV

DVD+RW 2.4 CLV3) Read speed: CD-ROM/R/RW 32x/32x/24x Max.

CD-DA(DAE) 24x Max. DVD-ROM/R/RW 12x/8x/8x Max.

+R/+RW 8x Max.DVD-Video(CSS Compliant Disc)

(Single/Dual layer) 8x Max.DVD-RAM(Ver. 1.0/2.1) 2x/2x, 3x

4) Sustained Transfer rate : CD-ROM 4,800 kB/s (32x).Max.DVD-ROM 16.62 Mbytes/s (12x)Max.

5) Burst Transfer rate: Ultra DMA Mode2, Multi word DMA Mode2, PIO Mode4.6) Multimedia MPC-3 compliant

5. Audio1) 16 bit digital data output through ATA interface.2) Software Volume Control 3) Equipped with audio line output for audio CD playback.

* DefinitionTransfer Rate : 1x (DVD) = 1.385 Mbytes/s, Mbytes/s = 106bytes/s

1x(CD) = 150 kB/s, kB/s = 210 bytes/sCapacity : MB = 220 bytes, kB = 210bytes

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5

SPECIFICATIONS1. SYSTEM REQUIREMENTS

-CPU: IBM Compatible Pentium 700MHZ (or faster)(For High speed, 700MHz or faster recommended.)-128MB Memory or greater

2. SUPPORTING OPERATING SYSTEM

2.1 Applicable disc formatsDVD DVD-ROM: 4.7GB (Single Layer)

8.5GB (Dual Layer)DVD-R: 3.95GB (Ver.1.0 : read only)

4.7GB (Ver.2.0 for Authoring : read only)4.7GB (Ver.2.0 for General: read & write)

DVD-RW: 4.7GB (Ver.1.1)DVD-RAM: 2.6GB/side (Ver.1.0)

1.46GB/side, 4.7GB/side (Ver.2.1)DVD+R: 4.7GBDVD+RW: 4.7GB

CD CD-ROM Mode-1 data discCD-ROM Mode-2 data disc

CD-ROM XA, CD-I, Photo-CD Multi-Session, Video CDCD-Audio Disc

Mixed mode CD-ROM disc (data and audio)CD-ExtraCD-TextCD-R (Conforming to “Orange Book Part2”: read & write)CD-RW (Conforming to “Orange Book Part3”: read & write)

2.2 Writing method(1) For CD-R/RW.......................Disc at Once (DAO)

Session at Once (SAO)Track at Once (TAO)Packet Writing

(2) For DVD-R/RW.....................Disc at OnceIncremental RecordingRestricted Overwrite (DVD-RW only)

(3) For DVD-RAM/+RW .............Random Write(4) For DVD+R...........................Sequential Recording

* Operating SystemWindow 98 Second EditionWindows Millennium Edition (Me)Window 2000 ProfessionalWindow XP Home Edition, Professional

* Recording tool(1) RecordNow (Veritas)(2) DLA (Veritas)(3) DVD-RAM Device driver software (Panasonic)(4) WinCDR (Aplix)(5) B’s Recorder Gold (BHA)(6) B;s Clip (BHA)(7) Drag’n Drop (Easy System Japan)(8) Nero(Ahead)(9) In CD(Ahead)(10) Easy CD Creator (Roxio)(11) Direct CD (Roxio)

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2.3 Disc capacity...............................................120mm80mm (Horizontal only)

2.4 Data capacity• User Data/Block DVD-ROM/R/RW/RAM/+R/+RW ......2,048 bytes/block

CD (Yellow Book) ..........................................2,048 bytes/block(Mode 1 & Mode 2 Form 1)2,336 bytes/block (Mode 2)2,328 bytes/block (Mode 2 Form 2)2,352 bytes/block (CD-DA)

2.5 RPC (Regional Playback Control) Phase2, No Region

3. DRIVE PERFORMANCE3.1 Host interface ..................................................................X3T13 ATA/ATAPI5/1321D

INF-8090i Rev.5.33.2 Read/Write & Rotational speed<Read> CD-ROM ........................................................14x ~ 32x (CAV), Approx. 6,850r/min

CD-RW data/CD-I/Video CD..........................10x ~ 24x (CAV), Approx. 5,130 r/minCD-DA (DAE) .................................................10x ~ 24x (CAV), Approx. 5,130 r/minCD-DA (Audio out) .........................................4.3x ~ 10x (CAV), Approx. 2,140 r/min

DVD-ROM ............Single layer......................5.0x ~ 12x (CAV), Approx. 6,890 r/minDual layer ........................3.3x ~ 8x (CAV), Approx. 5,056 r/min

DVD-R...................3.95GB ............................3.3x ~ 8x (CAV), Approx. 5,056 r/min4.7GB ..............................3.3x ~ 8x (CAV), Approx. 4,600 r/min

DVD-RW................4.7GB ..............................3.3x ~ 8x (CAV), Approx. 4,600 r/minDVD-RAM..............Ver.1.0.............................2x (ZCLV)*

Ver.2.1.............................2x, 3x (ZCLV)*DVD+R ..................4.7GB ..............................3.3x ~ 8x (CAV), Approx. 4,600 r/minDVD+RW...............4.7GB ..............................3.3x ~ 8x (CAV), Approx. 4,600 r/min

<Write> CD-R ..............................................................4x, 8x (CLV), 16x , 24x (ZCLV)CD-RW...........................................................4x(CLV), High speed Disc 8x, 12x (CLV)

Ultra speed Disc 16x(ZCLV)

DVD-R............................................................1x, 2x, 4x (CLV)DVD-RW ........................................................1x, 2x (CLV)DVD-RAM..............Ver.2.1.............................2x, 3x (ZCLV)DVD+R...........................................................2.4x, 4x (CLV)DVD+RW .......................................................2.4x (CLV)

* Rotational speed (CLV, ZCLV)CD-ROM/R/RW..............................................1x: Approx. 497 +38/-39 (Inside)(CLV = 1.2 - 1.4 m/s) to 214 +17/-16 r/min (Outside)DVD-R/RW.....................................................1x: Approx. 1,390(Inside) ~ 575 r/min(Outside)(CLV = 3.49 m/s)DVD-RAM..............Ver.1.0.............................1x: Approx. 2,387(Inside) ~ 1,014 r/min(Outside)

Ver.2.1...............................2x: Approx. 3,246(Inside) ~ 1,375 r/min(Outside)DVD+R/RW....................................................1x: Approx. 1,390(Inside) ~ 575 r/min(Outside)

3.3 Data transfer rate3.3.1 Sustained transfer rate<Read> CD-ROM/R.....................................................2.07 ~ 4.8 Mbytes/s (32x) Max.

CD-RW...........................................................1.5 ~ 3.6 Mbytes/s (24x) Max.CD-DA(DAE) ..................................................1.5 ~ 3.6 Mbytes/s (24x) Max.

DVD-ROM ............Single layer......................6.88 ~ 16.2 Mbytes/s (12x) Max.Dual layer ........................4.57 ~ 11 Mbytes/s (8x) Max.

DVD-R............................................................4.57 ~ 11 Mbytes/s (8x) Max.DVD-RW ........................................................4.57 ~ 11 Mbytes/s (8x) Max.DVD-RAM..............Ver.1.0.............................2.77 Mbytes/s

Ver.2.1.............................2.77, 4.155 Mbytes/sDVD+R...........................................................4.57 ~ 11 Mbytes/s (8x) Max.DVD+RW .......................................................4.57 ~ 11 Mbytes/s (8x) Max.

<Write> CD-R .....................4x, 8x ..............................0.6, 1.2 Mbytes/s (Mode-1)16x, 24x (ZCLV)..............1.8 ~ 2.4, 1.8 ~ 3.6 Mbytes/s (Mode-1)

CD-RW..................4x, 8x, 12x.......................0.6, 1.2, 1.8 Mbytes/s (Mode-1)16x (ZCLV)......................1.8 ~ 2.4, Mbytes/s (Mode-1)

DVD-R...................2x, 4x...............................2.77, 5.54 Mbytes/s

DVD-RW................1x, 2x...............................1.385, 2.77 Mbytes/sDVD-RAM..............2x, 3x...............................2.77, 4.155 Mbytes/s(Ver.2.1):Without verifyDVD+R ..................2.4x, 4x............................3.32, 5.54 Mbytes/sDVD+RW...............2.4x..................................3.32 Mbytes/s

3.3.2 Burst transfer rateUltra DMA Mode 2..........................................33.3 Mbytes/s Max.Multiword DMA Mode 2..................................16.6 Mbytes/s Max.PIO Mode 4 ....................................................16.6 Mbytes/s Max.

3.4 Access time (1/3 stroke)* Typical value

DVD-ROM......................................................145 ms Typ. (Note 1)

DVD-RAM (Ver.2.1) .......................................165 ms Typ.CD-ROM ........................................................125ms Typ. (Note 1)

Note :

1) Average random access time is the typcal value of more than 50 times including latency and error correction time.

Test Disc : DVD : ALMEDIO TDV-520 / TDR-820

CD : ALMEDIO TCDR-701 / HITACH HCD-1

*) Typical value defines a measured value in normal temperature (20 deg.C.) and horizontal position.

3.5 Data error rate (Measured with 5 retries maximum)DVD-RAM..............<10 -12

DVD-ROM .............<10 -12

CD-ROM................<10-12 (Mode-1)<10-9 (Mode-2)

Condition : It is assumed that the worst case raw error rate of the disc is 10-3

3.6 Data buffer capacity .......................................................2Mbytes

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4. Quality and Reliability4.1 MTBF..................................................100,000 Power On Hours(Consecutive/Cumulative POH)

Assumption : ..........................Used in a normall office environment at room temperature.-POH per year.........................3,000-ON/OFF cycles per year........600-Operating duty cycle..............20% of power on time (Seek: 5% of operating time)

4.2 Tray cycle test...................................10,000 timesNo degeneration in the mechanical part after test

4.3 Actuator mechanism ........................1,000,000 full stroke seek4.4 MTTR (Mean Time To Repair) ...........0.5 h 4.5 Component life .................................5 years or 2,000 h of Laser radiating time

Assumption : ..........................Used in a normall office environment.

5. POWER REQUIREMENTS5.1 Source voltage

+5V + 5% tolerance, less than 150 mVp-p Ripple voltage+12V + 10% tolerance, less than 300 mVp-p Ripple voltage

5.2 CurrentIdle (Hold track state)..............+5V DC 0.6A Typ. < 0.9 A Max.

+12V DC 0.5A Typ. < 0.9 A Max.Read (Active) ..........................+5V DC 0.7A Typ. < 1.3 A Max.

+12V DC 0.6A Typ. < 1.2 A Max.Seek (Acess) ..........................+5V DC 0.8A Typ. < 1.5 A Max.

+12V DC 1.3A Typ. < 1.8 A Max.

5.3 StandbySleep mode (No disc) .............1.0 W Typ. 1.2 W Max.

6. AUDIO PERFORMANCE

Item Typical Test Signal Test Condition Note

Output Level 0.7 Vrms 1KHz 0 dB No Filter

Frequency response +/-3dB 20-20kHz 0dB at 47kΩ

THD 0.1% 1KHz 0 dB with IHF-A + 20KHz LPF

Headphone output level(Optional) - - - None

AU

DIO

O

UT

7. Acoustic noiseLess than 50dB, A scale, at 0.5 m away from the driveNote : 1. Disc : Less than unbalance 0.5 x10-4 Nm

2. Installation : Horizontal3. Ambient temperature : Normal temperature4. Except loading, unloading and seek

8. DimensionsExternal dimensions (W x H xD) 146x41.3x184.6mmFront bezel (WxHxD) 148.2x42x5 mm

9. Mass .................................................Approx. 0.92 kg

* Which is not provided with Circuit Diagram of this model. Please Contact the friendly staff of LGService Care at: Website http: //biz.LGEservice.com

e-mail http : //www.LGEservice.com/techsup.html

LOCATION OF CUSTOMER CONTROLS

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1. Disc trayThis is the tray for the disc. Place the disc on theejected disc tray, then lightly push the tray (orpush the eject button) and the CD will be loaded.NOTE: Don’t pull out or push in the disc trayforcibly. This might cause damage to the loadingsection of the drive.

2. Stop/Eject buttonThis button is pressed to open the CD tray.This button works only when power is supplied tothe drive.If an Audio CD is playing, pressing this button willstop it, and pressing it again will open the tray.

3. Emergency Eject HoleInsert a paper clip here to eject the Disc traymanually or when there is no power.

4. Drive activity indicatorGreen colored LED is used to indicate theoperation of Super Multi DVD Drive.

Drive Activity Indicators

Stop/Eject Button

Disc Tray

Emergency Eject Hole

Front Panel

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1. Power ConnectorConnects to the power supply (5-and 12-V DC) ofthe host computer.NOTE : Be careful to connect with the properpolarity. Connecting the wrong way may damagethe system (and is not guaranteed). Usually thisconnector can only be attached one-way.

2. IDE Interface ConnectorConnect to the IDE (Integrated DeviceElectronics) Interface using a 40-pin flat IDEcable.NOTE : Do not connect or disconnect the cablewhen the power is on, as this could cause a shortcircuit and damage the system. Always turn thepower OFF when connecting or disconnecting thecable.

3. Jumper ConnectorThis jumper determines whether the drive isconfigured as a master or slave. Changing themaster-slave configuration takes effect afterpower-on reset.

4. Analog Audio Output ConnectorProvides output to a sound card (analog signal).Generally you need this to play a regular audioCD.

5. Digital Audio Output ConnectorThis connector is not supported.

RESERVED ANALOG AUDIO

INTERFACEPOWER

3940

1+5 GND +12

2

C S MS L AR G L

Digital Audio OutputConnector

Jumper Connector

Analog Audio Output Connector IDE Interface Connector

Power Connector

Rear Panel

1. CABINET and CIRCUIT BOARDDISASSEMBLY

1-1. Bottom ChassisA. Release 4 screws (A) and remove the Bottom Chassis

in the direction of arrow (1). (See Fig.1-1)

1-2. Front Bezel Assy A. Insert and press a rod in the Emergency Eject

Hole and then the CD Tray will open in the directionof arrow (2).

B. Remove the Tray Door in the direction of arrow (3) by pushing the stoppers forward.

C. Release 3 stoppers and remove the Front Bezel Assy.

1-3. Cabinet and Main Circuit BoardA. Remove the Cabinet in the direction of arrow (4).

(See Fig. 1-3)B. Release 2 hooks (a) and remove the CD Tray

drawing forward.C. Remove the Main Circuit Board in the direction of

arrow (5).D. At this time, be careful not to damage the 4

connectors, are positioned at left and bottom sides,of the Main Circuit Board.

2. MECHANISM ASSY DISASSEMBLY2-1. Pick-up UnitA. Release screws (B).B. Separate the Pick-up Unit in the direction of arrow (6).

MainCircuit Board

Cabinet

(4)

(5)

Hooks (a)

(A)

(A) (A)

(A)

(1)

Bottom Chassis

(2)

(3)

Tray Door

CD Tray

Front Bezel Assy

Emergency Eject Hole

Stoppers

Fig. 1-1

Fig. 1-2

DISASSEMBLY

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Fig. 1-3

Mechanism Assy

Pick-up Unit

(6)

(B) (B)

Fig. 2-1

2-2. Pick-upA. Release 1 screw (C) and remove the Pick-up.

Pick-up Unit

Pick-up

(C)

Fig. 2-2

12

030

050

PBM00 (MAIN C.B.A)

007

A02

A01

A03

401

031

401

018

401

019

023

401

022

024

401

017

021

021

413413

413

001

413

430

010

009420

008011

012

005035

016

015

004

006

A B C D E F G H

1

2

3

4

5

003

002

013

025

430

020

401

401

028

026

014

032

020

027

471

13 14

EXPLODED VIEW

ATIP Absolute Time in Pre-groove. With an additional modulation of the “Wobble”, the “Groove” contains a timecode information.

Wobble The pre-groove in the Disc is not a perfect spiral but is wobbled.With : – A typical amplitude of 30 nm

– A spatial peried of 54~64 µm

CW Continuous Wave. The laser light output is at a constant level.

DOW Direct Over-Write. The action in which new information is recored over previously recorded information inCD-RW disc.

Overwrite The action in which new information is recorded over previously recorded information.

(Pre-)Groove The guidance track in which clocking and time code information is stored by means of an FMmodulated wobble.

Land Land is characterized in the following way:When radial signals are concerned,land is defined as the area between the grooves.When HF signal are concerned,land is defined as the area between the marks(pits) in tangentialdirection.

Hybrid Disc A Multisession disc of which the first Session is mastered. On a hybrid disc, recorded andmastered information may co-exist.

Mastered Information,stored as pits on the disc during the manufacturing process of the disc.Information (when making the master)

OPC Optimum Power Control. Procedure is determined optimum recording power according to CD-R/RW Media in recording start step.

ROPC Running OPC. The purpose is to continuously adjust the writing power to the optimum powerthat is required.When the optimum power may change because of changed conditions of disc and change inoperating temperature.

Jitter The 16 value of the time variation between leading and trailing edges of a specific (I3 … I11) pitor land as measured by Time Interval Analysis.

Deviation The difference between a fixed value of Pit length and Land length.

TOC Table Of Contents : in the Lead-in Area the subcode Q-channel contains information about theTracks on the disc.

Packet A method of writing data on a CD in small increments. Writing Two kinds of packets can be written : Fixed-length and Variable-length.

Write The shape of the HF write signal used to modulate the power of the laser.Strategy The Write Strategy must be used for recordings necessary for disc measurements.

Information Wobble, ATIP, Disc Identification, Write Power, Speed Range OPC Parameters, etc areArea recorded in the Information area of CD-RW Disc

Finalization The action in which (partially) unrecorded or logically erased tracks are finished and the Lead-inand/or Lead-out areas are recorded or overwritten with the appropriate TOC subcode.

Logical Erase A method to remove information from a disc area by overwriting it with an EFM signal containingmode 0 subcode A logically erased area is equivalent to an unrecorded

Physical Erase The action in which previously recorded information is erased by overwriting with a CW laseroutput.After a Physical Erase action, the erased area on the CD-RW disc is in the unrecorded stateagain.

Session An area on the disc consisting of a Lead-in area, a Program area, a lead-out area.

Multi session A session that contains or can contain more than one session composed Lead-in and Lead-out

GLOSSARY

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17

The differences of CD-R/CD-RW discs and General CD-ROM1. Recording Layer

Recordable CD has a wobbled pre-groove on the surface of disc for laser beam to follow track.

2. Disc Specification

Read-only Disc

CD-R and CD-RW Disc

3~11T

1.6um

0.4~0.5 um

(Pit)Groove

Land

Track pitch(p)

Radial Direction

Iw

A

O

a

a

GrooveLand

Radial Error Signal

The Groove wobble

Average center

Actual center

CD-ROM (READ-ONLY DISC) a=30nm

ITEM CD-ROM CD-R CD-RW

Standard Yellow Book Orange Book II Orange Book III

Record Not available Write once Re-Writeable

Tracking Signal I11/Itop > 0.6 > 0.6 0.55 > M11> 0.70(HF Modulation)

Read Laser Power(mW) < 0.5 mW < 0.7 mW < 1.0 mW

Jitter < 35 nsec < 35 nsec < 35 nsec

Reflectivity (Rtop) 70 % 65 % 15 % ~ 25 %Remark)

Write Laser Power(mW) 14-65 mW 6-45 mW

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3. Disc Materials

1) CD-ROM disc

Laser Beam Groove

Substrate(Polycarbonate)

Organic Dye LayerReflective LayerProtective Layer

Label Printing

2) CD-R disc

Pigment Reflective Layer Color

Phtalocyanine Gold/Silver Yellow/White

Cyanine Gold/Silver Dark Green/Bright Green

Azo Gold/Silver Dark Blue

• It is composed of Silver _ colored aluminum plate and Reflective layer.• Groove (Pit) of aluminum plate make a track.• Laser wavelength : 780 nm, Laser Power (Read): 0.5mW• Signal is detected by the

difference of reflective beam intensity between “pit” and “Land” on the disc.

• It is so-called WORM (Write Once Read Many) CD.• It is composed of polycarbonate layer, Organic dye layer, Reflective layer, and Protective

layer.Gold/Silver Reflective layer is used to enhance the reflectivity• According to the kinds of Organic dye layer, it is divided by Green CD, Gold CD, Blue CD.• Laser Wavelength : 780 nm, Laser Power (read) : 0.7 mW• Recording Power : 8x(14~20mW), 16x(25~35mW)• When some part of dye layer is exposed to laser heat, it’s color changs black.Therefore, writing and

reading is enabled by the difference of reflectivity between changed part and unchanged part.• Polycarbonate layer has Pre_Groove which make a Track.

Laser BeamPit


Reflective Layer

Protective Layer

Label Printing

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3) CD-RW Disc

4. Reading process of Optical Disc

Laser Beam Groove


Recording LayerDielectric Layer(TL)

Dielectric Layer(UL)

Protective Layer

Label Printing

• It is composed of polycarbonate layer, alloy(silver, arsenic) layer, aluminum reflectivity layer, protective layer.• An crystalized alloy layer is transformed into noncrystalized by the laser heat. Therefore, writing and reading

is enabled by the difference of reflectivity.• It is possible to overwrite about 1000 times.• Laser Wavelength : 780 nm, Laser Power (Read) : 1.0mW• Recording Power : Erase (4~18mW), Write (6~45mW)• When disc rewriting, new data is overwritten previously recorded data.• Polycarbonate layer has a Pre-Groove which make a track.

LensH

D

BeamSpot

FocusingLens

Laser Spotat ConstantRead Intensity

ReflectedLightSignal

Laser SpotPosition(Time)

Previously Recorded Marks

Groove Land Mirror

I3 Itop

I11 IG IL I0

Numerical aperture: NA=nsinθ, n: Refractive index

Focus depth : H = λ/NAlaser spot diameter : D = λ/NA2

θ

20

5. Writing Process of CD-R Disc

a b c d e f g

a

b

c

d

e

f

g

IncidentLaserPower

(Read) (Read)

(Write)

Laser SpotPosition(Time)

a b c d e f gLaser SpotPosition(Time)

LaserSpot

RecordedMark



Below "ORP"– Mark Too Short

At Optimum Record Power ("ORP")

Above "ORP" – Mark Too Long

Time

6. Writing process of CD-RW Disc

Write Power

Erase Power

Read Power

Groove

Crystal Amorphous

Amorphous

Recorded state(lower reflectivity)

Melting/quenching

Heating/gradual cooling

Crystal phase

Erased state(higher reflectivity)

21

7. Organization of the PCA, PMA and Lead-in Area

1) Layout of CD-ROM disc

Center hole Clamping and Label Area Information Area

Lead-in Area

Lead-in Area

Diameter 15 mm

Diameter 46 mm

Diameter 120 mm

Program Area

Read Only Disc

Lead-out Area

Program Area Lead-out Area

Center hole Clamping and Label Area Information Area

PCA PMA

Test Area Count Area

Diameter 15 mm

Diameter 45 mm

Diameter 120 mm

Unrecorded Disc

Tsl-00:35:65 Tsl-00:15:05 Tsl-00:13:25 Tsl 99:59:7400:00:00

in out

Test Area : for performing OPC procedures.

Count Area : to find the usable area immediately in T.A

Tsl : start time of the Lead-in Area, as encoded in ATIP

PMA : Program Memory Area

Disc Center

Disc Center

2) Layout of CD-R/RW disc

22

8. Function of PCA and PMA area

1) PCA (Power Calibration Area)

• PCA area is used to determine the correct Laser Power for a disc.– Method 1 : PCA area is divided by a track.– Method 2 : The previous Calibration value is referred.– Method 3 : ROPC is used to determine Laser Power value automatically in data writing.

• CD-R Disc can write maximum 99 Tracks but CD-RW Disc can write unlimited tracks because it has a rewritable function.

2) PMA (Program Memory Area)

• It has a track information (track No, track Start/End time) of every track before writing completed.– PMA area has the last written point and the next writable point of a disc.– In case of CD to CD copy, some writer may not write PMA area.

* When Disc is Finalized,PMA information is transferred to the Lead_In area so that general Driver can read it.

* Because PCA and PMA area exist before Lead-In area, General CD Player or CD-ROM Drive can’t read these areas.

9. OPC and ROPC

1) OPC (Optimum Power Control)• This is the first step of writing process, because CD writer has its own laser power value and media have different writing characteristics,– This is determined by the Writing characteristic, speed, temperature, and humidity.– Laser wavelength is determined by the environmental temperature (775~795nm) and Optical Laser Power is

determined by the test and retry.

• Asymmetry and optimum writing Power– EFM signal Asymmetry is determined by the writing power.

Therefore, Optical Power which has the same value to the preset power value can be estimated by measuring HF signal Asymmetry on the PCA area.

• Measurement of Asymmetry* Parameter setting (Beta) : Using AC coupled HF signal before equalization

Beta = (A1+A2)/(A1-A2)

Time P << Po TimeP = Po

HF

Sig

nal A1

0

A2

TimeP >> Po

23

2) ROPC (Running Optimum Power Control)

• Variable primary factor of Optimum Power– Change of Power sensitivity on the Disc. (limited to 0.05 *Po)– Wavelength shift of the laser diode due to the operating temperature change.– Change of the Spot aberration due to the Disc skew,

Substrate thickness, Defocus.– Change of Disc or Optics conditions due to the long term OPC

==> It is necessary to adjust continuously to obtain the Optimum Power.

• Principle of Running OPC– To meet the factors mentioned above,

a horizontal _ direction movement of a curve is uesd.– Beta = f(B-level) = constant on the Recorded Disc– Procedure of ROPC

a. Reference B-level is determined during OPC Procedure.b. During Recording, B-level value is controlled to have a close

Reference B-level value.c. Normalization of B-level is used to eliminate the effect of reflectivity fluctuation.

==> The reflected B-level value is normalized by the disc reflectivity itself.

CD-R/RW Media

Write StrategyDetermination

PCA Test Area

Program Area

PMA Area

Lead-In Area

Lead-out Area

OP

C

PCA Count Area

RO

PC

* Recording Capacity of CD-R/RW (74Minute Recording media)

• (2048 Byte/Sector) X (75 Sector/Second) X (60 Second/Minute) X 74 Minute= 681,984,000 Bytes = 682 Mbytes

• But the actual recording capacity is about 650 Mbytes. (according to the ISO 9660 standard, approximately 30 Mbytes are used to make directory structure and volume names.)

Incident recording pulse

Reflected recording pulse

Sampled timing B

11T

Sample B-level (Write Power)

Leve

l B

Sampled at timing B

Pwo decided by OPC

Recording Power

Level B with Pwo

normalized to recording power

Sample Disc Reflectivity (Read power)

10. Writing Process of DISC

24

The differences of DVD-R/RW, DVD+R/RW discs and DVD-ROM1. Recording Layer

LPP(Land Pre-Pit)

DVD+R/RW Disc

DVD-R/RW Disc

0.74 um

3T

0.4 um

DVD-ROM (Read Only Disc)

25

2. Disc Specification

3. Disc Materials

1) DVD-ROM

DVD-ROM

Media Type

User data capacity

Single-Layer

Read Only

4.7GB

Dual-Layer

Read Only

8.54GB

DVD-R DVD-RW DVD+R DVD+RW

Dye Phase change Dye Phase change

4.7GB 4.7GB 4.7GB 4.7GB

Wavelength 650nm 650nm 650nm 650nm 650nm 650nm

Reflectivity 45~85% 18~30nm 45~85% 18~30% 45~85% 18~30nm

Track pitch 0.74 0.74 0.74 0.74 0.74 0.74

Minimum pit length 0.4 0.44 0.4 0.4 0.4 0.4

Modulation >0.6 >0.6 >0.6 >0.6 >0.6 >0.6

Channel bit- rate 26.16MHz 26.16MHz 26.16MHz 26.16MHz 26.16MHz 26.16MHz

Wobble Frequency - - 140KHz 140KHz 817.4KHz 817.4KHz

Addressing 26.16MHz 26.16MHz Wobble & LPP Wobble & LPP Wobble(ADIP) Wobble(ADIP)

Read Power (mW) 0.7 0.1 0.7 0.1

Write Power (mW) - -

JItter <8% <8% <8% <8% <9% <9%

++

Bonding layer

Polycarbonate

Semi-reflectivePolycarbonate

Reflective layer

Label

Polycarbonate

Label

Bonding layer

Reflective layer

Polycarbonate

<Single Layer >

<Dual Layer >

26

2) Recording format using organic dye material (DVD-R/DVD+R)

* The format that records data through the creation of recorded marks by changing the organic dye materialwith a laser beam.

DVD-R

Adhesive layerProtective layer

Reflective layerRecording layer(dye)

Disc substrate

DVD+R


Reflective layerRecording layer(dye)

Disc substrate


Reflective layerDye layer

Substrate

Laser beam

> Disc structure

> Disc structure

[Recording]Recording is done by changing the organic dye layer and the substrate with a laser when a strong isapplied to a disc, the temperature of the ortanic dye material goes up, the dye is decomposed and thesubstrate changes at the same time. At this time, a durable bit is created as is the case with a CD-ROM.

[Playback]Signals are read with the differences of the reflection of a laser from pits.

27

3) Recording format using phase-change recording material (DVD-RW/DVD+RW)

* Data is recorded by changing the recording layer from the amorphous status to the crystalline status, andplayed back by reading the difference of the reflection coefficient.

[ Amorphous : Non-crystalline ]

Substrate

Laser beam

Recording data(Melting/Quick cooling)

Erasing data(Heating/Gradual cooling)

Data erased state(High reflection coefficient)

Recorded state(Low reflection coefficient)

Crystalline status Amorphous status

DVD-RW

Adhesive layerProtective layerReflective layerDielectric layerRecording layer(Phase change material)Dielectric layerDisc substrate

DVD+RW

Adhesive layerProtective layerReflective layerDielectric layerRecording layer(Phase change material)Dielectric layerDisc substrate

> Disc structure

> Recording principles

[Recording]When a high-power laser is applied to the recording material, it melts and then becomes amorphous witha low reflection coefficient when it quickly cools off. When a mid-power laser is applied to heat graduallythe recording material and then gradually cools it off, it becomes crystal with a high reflection coefficient.

[Playback]A low-power laser is used for playback. The amount of reflected light depends on the status (amorphousor crystalline) of the recording material. This is detected by an optical sensor.

28

4. Writing Pulse Wave Form of DVD+R

For different speed ranges, different write strategies can be used. This document specifies 2 options:

- a pulsed write strategy, where each single mark is created by a number of subsequent separated shortpulses.

- a blocked write strategy, where each single mark is created by one continuous pulse.

1) 1st Method : Using Pulsed Write Strategy

* 3T :

NRZIT = 3

2Tw

TtopdTtop

dTle

Pb

top

top le

Pp

Channel bits

N = 3 : only the top pulse(T ),first pulse lead-time dT , dT

NRZI

T > 4

2Tw Tw

Ttop Tmp Tmp TlpdTtop

dTle

Pb

top

top le

lpmp

Pp

Channel bits

N > 4 : the top pulse (T ), multi-pulse (T ) and last pulse (T ),first pulse lead-time dT , dT

Pp : Actual write powerPb : Bias Power

* > 4T :

29

2) 2st Method : Using Blocked Write Strategy

NRZIChannel bits

2Tw Tw

dTtop

Ttop

dTlePp

Pb

Tmp

lpT

dPp

0mWPc Pb

1.25Tw

3T mark

4T mark

5T mark

Etc.

dTtop,3 dPp3

Ttop,3dTle

1.25Tw

PcPb

1.25Tw

1.25Tw

1.25Tw

dTtop,4 dPp4

Ttop,4 Tlp

Ttop,4

Ttop,4

Tmp

Tmp

Tlp

TlpTmp

N = 3 : T (cm = 3) can be optimized individually. N > 4 : T (cm 4) + x (N-3) T + T , T = TP shall be < 0.1mW

topmplpw wtop

c

Pp : Actual write powerPb : Bias PowerdPp : Additional power ( Only be applied for the 3T and 4T marks)Pc : Cooling power (Especially at higher recording speeds, optimum cooling down of the recording layer after writing a mark may be needed.)

>

30

5. Writing Pulse Wave Form of DVD+RW

NRZIChannel bits

2Tw Tw

TtopdTtop

Pp

Pe

TmpmpT dTera

Pp : Actual write powerPe : Erase PowerPb : Bias Power

Pb0mW

Tmp

6. Organization of the Inner Drive Area, Outer Drive Area, Lead-in Zone andLead-out Zone

1) Layout of DVD-ROM disc

31

Center hole

1st transition area2nd transition area

Clamping Zone

3rd transtionarea Information Zone

Lead-in Zone

Lead-inZone

Lead -outZone

Diameter 15 mm

Diameter 16 mm

Diameter 22 mm

Diameter 33 mm

Diameter 44 mm

Diameter 120 mm

Data Zone

Read Only Disc

Lead-out Zone

Data ZoneOuter DriveArea

Inner DriveArea

Inner DiscTest Zone

Outer DiscTest Zone

Unrecorded Disc

PSN: 23080H 27080H 27480H 28480H 2A480H 30000H 260540H 261940H 262940H 263940H 267940H

in OUT

Disc Center

Rim area

Center hole


Clamping Zone


Diameter 15 mm

Diameter 16 mm

Diameter 22 mm

Diameter 33 mm

Diameter 44 mm

Diameter 120 mmDisc Center

Rim area

Inner DiscCount Zone

Outer DiscCount Zone

2) Layout of DVD+R disc

> Inner Disc Test Zone : for performing OPC procedures.> Inner Disc Count Zone : for counting the number of OPC algorithm performed in IDT Zone.> Outer Disc Test Zone : for performing OPC procedures.> Outer Disc Count Zone : for counting the mumger of OPC algorithm performed in IDT Zone.

3) Layout of DVD+RW disc

32

> Inner Disc Test Zone : for performing OPC procedures.> Inner Disc Count Zone : for counting the number of OPC algorithm performed in IDT Zone.> Outer Disc Test Zone : for performing OPC procedures.> Outer Disc Count Zone : for counting the number of OPC algorithm performed in IDT Zone.

Lead-in Zone Lead -out ZoneData Zone

Inner DiscTest Zone

Outer DiscTest Zone

Unrecorded Disc

PSN: 2A480H 2A7C80H 2DC80H 30000H 260540H 262940H 265940H 266140H

in OUT

Center hole


Clamping Zone


Diameter 15 mm

Diameter 16 mm

Diameter 22 mm

Diameter 33 mm

Diameter 44 mm

Diameter 120 mmDisc Center

Rim area

Inner DiscCount Zone

Outer DiscCount Zone

33

DVD & CD DATA PROCESSING1. Data Processing Flow

Com

man

d

Dat

a S

tatu

s

RF

EQ

& A

GC

SE

RV

OD

SP

Enc

oder

& D

ecod

er &

CS

S

RF

dat

a sl

ice

EF

M d

emod

ulat

orC

iRC

err

or c

orre

ctio

nA

udio

DA

CB

uffe

r/M

emor

y co

ntro

ller

CS

S c

ontr

olle

rA

tapi

inte

rfac

e co

ntro

l

Dat

a P

LLS

ervo

AD

CF

ocus

/trac

king

con

trol

out

put

Sle

d co

ntro

l out

put

CA

V S

pind

le c

ontr

ol

P-u

pU

nit

(HO

P-8

511T

)

IC10

1R

F A

MP

(HD

1537

21TF

)C

D

DV

D

IC70

1(H

D62

604F

DV

)

TE

/CS

O G

EN

FE

GE

N

IC70

2 D

RA

M

IC80

1IC

802

EE

PR

OM

Fla

sh R

OM

IC80

4IC

803

SR

AM

34

HD62604FDV/BPVHOST DVDPLAYER

(EMPEG2 B/D)

Scrambled MPEG Data

Change the "KEY"

KEY Management Control

2. Copy Protection and Regional Code Management Block

Block Diagram

Brief Process1. Regional Code for DVD Disc

– DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVDplayer of host reads the regional code, and plays title in the case of allowed regional code only.

2. Management of DVD Disc for the scrambled of data (1) DVD-ROM and DVD player of host generate the “KEY 1” respectively, transfer to opposite part, the

“KEY 2” is received, recognizes the data transfer or not with this value, and generates the bus key encoded the data.

(2) Encoded “Disc Key” and “Title Key” host is transfer with the bus Key.(3) DVD player of host reads the key value, and uses the value to restore the scrambled data.* Refer to the next page for the details.

35

3. About Prevention the DVD-ROM from to be copyA data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying.

In case of a disc enhanced movie of 3 titles......DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLEKEY (5 Bytes) is used to encode the title respectively.So, the data is encoded and stored in a disc through the unknown algorithmswith a disc key and title key. (At this time, the disc key and title key are storedin a disc.)…As above, the disc is able to copy when the disc key and title key areopened.Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG-2 board.

If you want to play the disc prevented from the copy......First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as describedbelow.

1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID).The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive.

2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. Theboard and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithmgenerating the key 1 is not known.)

3. Compare with the generated key 1, if it corresponds each other, the first step of authentication iscompleted. This is a course to identify the MPEG-2 board with a drive.

4. The second step of authentication is a course to identify a drive with the MPEG-2 board.The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 boardgenerate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and thesecondary step of authentication is completed.

5. As above, the identification is completed.6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it.7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board.8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only.9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into

the video signal by decoding.

ROM-DRIVE

AGID HOST

MPEG-2BOARD

Challenge key

encoded disc key, title key

36

4. About the DVD-ROM Regional Code

DISC ROM - DRIVE MPEG-2 BOARD VGA CARD MONITOR

1

CAN

U.S.A

MIX

CUB

BHS

PRI. VIR

1

BMG

GRL

2

2 ZAFISOSWZ

FIN

POI

FSTLTU

BIR

UKR

TUR

FGY

JRN

TKM

AFGPAK

CHN

MMR

MNG

RUS

KOR JPN

HKGMAC

TWN

PHL

6

3

21

5

5

4

1

MDI

MNP

GUM

PLW

PNG

NZL

AUS

4

The disc hasthe regionalcode of 8 bit.

Example)The discmanufacturedin the U.S.A,has thenumber one.

Transfer toMPEG-2 boardreading theregional code.

Receivingdata from theMPEG-2board andoutputthrough themonitor

If the board is setting to the regionalcode 1 for the U.S.A. ...Check the received regional code tonumber 1, all or not, transfer thedata to VGA card in accordance withonly a case among the three case.

Regional code

INTERNAL STRUCTURE OF THE PICK-UP1. Block Diagram of the PICK-UP(HOP-8511T)

37

1141312111098

234567

GN

D

RW

BV

S0

MON1SLGRfregIAPCISLOPAGNDENRSET

SCLKSDIOSEN

BUSYNCNCO

UT1

OU

T1G

ND

VS

OV

SO

OU

T2O

UT2

VS

0

NR

ZN

RZB

GN

DG

ND

GH

06560B2C

H

LDD

GN

D

LDD

GN

D

LNGN

D

AG

ND

AG

ND

AC

T

GN

DLD

D

CLK

BC

LKV

SL

VS

A

A1:P

A2:M

A3:N

A4:O

B1:B

+GB

2:A+H

B3:E

+JB

4:D+K

VC

DB4

B2

B4

B3

B2

B1

A2

A3

A4

A1

P KJ

Gb

AB

EHO

NM

A2

A3

RF+

RF-

IC#01

IC#04

IC#02

LM20BIM7

IC#05

R5

C8

C7

0.01

R7 0

L210nH

10mH

R16 100

C1

C2 0.1u

0.1u

R15

100

C5

1u

C10

0.1u

C9

0.1u

L310nHC15

1u

WR

FR

FNO

M

GND

Vcc

LD+

TR AF

AF+

AF-

TR-

TR+ Tilt+

Tilt-

TILT

LD-

LOW

:AC

TIVE

HIG

H:S

LEE

P F E Vc

FE4

FE3

FE2

FE1

GN

D

R1

6.2k(1%

)

C3

4700

R2

2.7k

R3

0

R4

390(1%

)

C61000p

C14

1000P

LDD

GN

D

1

2.2k10kR

6

C11

0.1u

VR

1_100K

VR

2_100K

NJM

12984

NJM12984

C

E

CP2860

R11

27k

R12

R90

R10

27k

VC

C

GN

D

STB

SW

SW CD:LOW

AVCC(+5V)

AVCC(+5V)

DVD:HIGH

OU

TX

00TO

P_V

IEW

X00

X00

x.xk

x.xk

x.xk0.1

0.1

CP

0054AH

VR

EF

NC

VR

3_680

VR4_680

for DVD

for CD

CD

0

DVD

0IN

IC#07

IC#06

IC#08

IC#09

IC#10

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AV

CC

(+5V)

AV

CC

(+5V)

R8

10kBY

G144R

E

AG

ND

AG

ND

AV

CC

(+5V)

CP

0036AA

VR

EF

B1

TOP

_VIE

W

B3

A1

A4

SW

1

32

1

45

6

109876

2345

451 2 3

9

10 3231

3029

2827

26

252423222120191817

1112

1314

1516

8 7 6 5 4 3 2 1

7

89

101112131415

65432

116

C

E

813

4

21

34

21

23

4

76

5

JR2FP

C C

ON

NE

CTIO

N

54 TAC

T+

53 TAC

T-

52 FAC

T+

51 FAC

T-

50 TILT+

49 TILT-

48 AG

ND

47 AV

CC

46 A4

45 A1

44 B3

43 B1

42 VC

21

41 B4

40 B2

39 A2

38 A3

37 RFIP

36 RFIN

35 WR

F

34 RF (C

D)

33 FE4

32 FE3

31 FE2

30 FE1

29 E

28 F

27 VC

165

26 THE

RM

25 FMS

W(C

D)/D

VD

SLE

EP

24 F MO

N

23 VC

25

22 LPS

LDD

DR

V

21 LPS

1

20 LPS

2

19 IAP

C

18 LNG

ND

17 EN

A

16 SLG

15 VS

L33

14 VS

A5

13 VS

O

12 SR

F

11 BU

SY

10 SE

N

9 SD

IO

8 RW

B

7 MO

NITO

R

6 SC

LK

5 LNG

ND

4 NR

ZB

3 NR

Z

2 CLK

B

1 CLK

Pin no

Connection

Actuator

5ch OR

ICw

ith DIFF A

mp

for RF

CD

-R_H

OE

Monitor

for AP

C

LEN

S_S

EN

DV

DLD

Driver

(with H

F)

54 Pin P

itch=0.5mm

2. Pick up Pin Assignment

38

No. Signal Name I/O Signal Description

1 CLK I Clock for NRZ code input.2 CLKB I LVDS3 NRZ I NRZ laser data (H=mark, L=space)4 NRZB I NRZ laser data (L=mark, H=space)5 LDD GND ground connection6 SCLK I Serial control clock7 MONITOR O Monitor output8 RWB I Write enable for NRZ laser data(L=write, H-read)9 SDIO I Serial data for parameters and control10 SEN I Serial control enable.11 BUSY I RAM busy signal12 SRF I signal OEIC gain control (H=high gain, L=low gain)13 VSO power supply for output driver (+5V)14 VSA5 power supply for PLL (+5V)15 VSL33 power supply for logic (+3.3V)16 SLG I Land/groove input selects (H=land, L=groove)17 ENA I fast chip enable input18 LDD GND ground connection19 IAPC I lapc input20 LPS2 O Lens position sensor 2 signal output21 LPS1 O Lens position sensor 1 signal output22 LPS LED DRV I Lens position sensor LED(Cathode)23 VC25 APC amplifier reference voltage input (+2.5V)24 F MON O APC amplifier output25 FM SW(CD/DVD sleep) I APC amplifier gain control (H=DVD, L=CD)26 THERM O output voltage for controlling temperature27 VC165 reference voltage input(+1.65V)28 F O signal Hologram Unit output F29 E O signal Hologram Unit output E30 EF1 O signal Hologram Unit output EF131 EF2 O signal Hologram Unit output EF232 EF3 O signal Hologram Unit output EF333 EF4 O signal Hologram Unit output EF434 RF O signal Hologram Unit output RF35 WRF O signal Hologram Unit output WRF36 RFIN O signal OEIC output RF-37 RFIP O signal OEIC putput RF+38 A3 O signal OEIC putput A339 A2 O signal OEIC output A240 B2 O signal OEIC putput B241 B4 O signal OEIC putput B442 VC21 reference voltage input (+2.1V)43 B1 O signal OEIC output B144 B3 O signal OEIC output B345 A1 O signal OEIC output A146 A4 O signal OEIC output A447 AVCC power supply for OEIC (+5V)48 AGND ground connection49 TILT- I Tilting Actuator drive signal -50 TILT+ I Tilting Actuator drive signal +51 FACT- I Focusing Actuator drive signal -52 FACT+ I Focusing Actuator drive signal +53 TACT- I Tracking Acutuator drive signal -54 TACT+ I Tracking Actuator drive signal +

* When connector no.5(TILT+) is + polarity, the objective rotate C.W from sub-bar toward main-bar.

* Connector left side is no.1 and right side is no.54.

3. Signal detection of the P/U

1) Focus Error Signal ==> (A+C)-(B+D)This signal is generated in RF IC (IC101 : HD15372TF) and controls the pick-up’s up and down to focuson Disc.

2) Tracking Error Signal (DPP Method) ==> (A+D)-(B+C)- k x (EF1+EF4)-(EF2+EF3)This signal is generated in RF IC (IC101 : HD15372TF) and controls the pick-up’s left and right shift tofind to track on Disc.

3) RF Signal ==> (A+B+C+D)This signal is converted to DATA signal in DSP IC (IC701 : HD6203FDV/BPV).

39

Pick-Up module

Photo Diode Tracking

Focusing

Infrared Iaser

k[(F+H) - (E+G)]

(A+D) - (B+C)

(A+D) - (B+C) - k[(F+H) - (E+G)]

Offset

TE

Tp

Sub2

Main

Tp/2 Sub1

Track Center

F,E

D,CA,B

H,G

40

IC801 M

PU

WR

GA

TE

2

RFPD

SHO

pticalPick-up

LD

Driver

Write

Strategy

FsDA

CW

DA

C

IAPC

LPF&

Gain

DSP

WFPD

SH

FMO

N

LSR

ON

RW

APC

buffer

2.5VR

EF

GC

A

S/H

B/H

+-36

S/HM

UX

AM

P

APC

DA

C(R

ED

A/W

RD

A)

SCL

K , SD

AT

A , L

DB

USY

, WD

EN

16

3213

3114

373233

848988

PG101

IC101 (H

D153721T

F)IC

701 (HD

62604FDV

)

BC

NT

9 10T

CPH

36

2732

85R838

SIGN

924R

834

49,46,44,45

99,95,97,96

SIGN

926

DESCRIPTION OF CIRCUIT1. ALPC (Automatic Laser Power Control) Circuit1-1. Block Diagram

41

1-2. ALPC (Automatic Laser Power Control) CircuitALPC function DVD/CD anlaog front-end IC(IC101 HD153721TF) is for constant power control purpose. Based on the

accurate power sensor(FMON) in P/U, ALPC feedback loop maintains constant power level against laser diode’stemperature variation.

The ALPC loop amplifies(10x) the FMON signal to enhance the accuracy of read power level control. Swithching ofamplification is made by combination of a logical WRGATE2 signal and a logical RWAPC signal.

There are two set of APCDAC, which are used at different term to monitor different power level. Generally, the one is usedat reading and the other one is used at writing. The logical WRGATE2 signal which is switched between reading and writingchanges the two APCDAC.

The ALPC loop supplies same currency (IAPC) to Laser Diode Driver(LDD) during reading and writing.

There is another ALPC which controls Full-Scale-DAC (FsDAC). FsDAC determines scale of WDAC of Laser Diode Driver.MPU monitors write-power level of FMON signal and changes FsDAC directly to maintain constant write-power level. Thereare two write power signal. The one is based on S/H signal and the other one is based on B/H(Bottom-Hold) signal. Thewrite power levels are monitored as digital levlels which are converted by built-in Anlog-Digital Converter in DSP. The MPUmonitors each write power level and calculates proper setting of FsDAC, and changes value through serial interfacebetween LDD and DSP.

42

2. Focus Circuit

2-1. Block Diagram

DiscMotor unit

OpticalPick-up

HOP-8511T

A1~A4

B1~B4

(EF1~EF4)

(EF1~EF4) DVD : (B1+B3)-(B2+B4)CD : (EF1+EF3)-(EF2+EF4)

HAVC LS to V14

FEO

FE

FE1R701

C703

GNDADC Focusing Compensator

DAC

FOD

FODR625

IC601

BD7905

FACT+

FACT-

FACT+FACT-

IC101

HD153721U

IC701HD62604

CTL1

CTL2

DRVCTL1

DRVCTL2

GND

C628VC1.65V

FCIN

DVD : A1+A2+A3+A4CD : EF1+EF2+EF3+EF4

LPF G

HAVCLS to

0.8V

PE

PE

4

LPF G

101

102

3

27

28

39

53

27

22

23

46

45

2-2. Focus Servo

The aim of Focus Servo is to maintain the distance between object lens of P/U and disc surface, so that thedetected RF signal(A1, A2, A3, A4, B1, B2, B3, B4, EF1, EF2, EF3, EF4) can be maximized.

Focus Error Signal(FE) generates from focus error detection block in RF IC(HD153721) using Double kniteEdge method (DVD), spot size Detection method(CD). Focus Gain and path can be changed at the RF IC(HD153721) according to the disc, and the resulting outputFE(HD153721 3pin) is input to DSP IC(HD153721 27pin).The Focus Search operation is using FE, PE Signal, therefore check FE, PE signals when Focusing is failed.

The role of DSP IC(HD62604) is Focus Digital Controller. The operation path is as follows; FE Signal is input to DSP IC(HD62604 27pin), and after A/D Conversion, Digital Equalizer Block and D/AConversion in HD62604, the output signal FOD(HD62604 39pin) is input to Drive IC(BD7905 53pin).The drive output signal FCS+/FCS- generated according FCIN(BD7905 53pin), and drives focus actuator in theP/U unit.

43

3. Tracking & Sled Circuit3-1-1. Block Diagram (Tracking Following)

DiscMotor unit

OpticalPick-up

HOP-8511T

A1~A4

(F, E) TEI

R706

C708

GND

ENC1

SLIN2

SLIN1

TVN

TVP

TE

ADC TrackingCompensatorDAC

TRD

TACT+TACT-

IC101HD153721

IC701

IC602

HD62604

BU2507S-DAC

MPPO

(A+D)-(B+C)

G

HAVCLS to V14

5

3341

LPF

LPF

SPPO

DVD : (A1+A4)-(A2+A3)CD : (EF1+EF2)-(EF3+EF4)-K*(E-F)

SledCompensatorPWM

TVN

19

TVP

ENC1

18

15A+

A-

B+

B-

SLED MOTORUnit

TRDR624

IC501

BD7907

TACT+

TACT-

CTL1

CTL2

MUTE2

MUTE1

VC1.65V

TRKIN52

27

22

23

48

47

SLIN128

SLIN229

SLIN1

SLIN2

A-

B-

37

36

A+

B+

35

34

SLO1+

SL01-

SLO2+

SLO2-

C627

GND

C619

C618

R635

R630

2

13

3-1-2. Block Diagram (Seek)

44

DiscMotor unit

OpticalPick-up

HOP-8511T

A1~A4

SUMF

RFIP

(EF1~EF4)

(F, E)

C102

TACT+TACT-

IC101HD153721MPPO

(A+D)-(B+C)

G

HAVCLS to V14

5LPF

LPF

SPPO

K*(F+H)-(E+G)

A+

A-

B+

B-

SLED MOTORUnit

(A+D)-(B+C)

K*(F+H)-(E+G)

G

HAVCLS to V14

LPF

LPF

48

76

78

EQ

MIRR

DET

AGCTOP

HOLD

60 59

BOTTOMHOLD

-

+

-

-

+

+

TE1

MIRRTOPH MIRRBOTH

C118

GND

39 TZC

MIRR

TEIN

VREF1

VREF1

TVDN

DAC

TrackingCompensator

IC701HD62604

33

SledCompensator

ADC

100

24MUX

ShortSeek

Algorithm

LoogSeek

Algorithm

PWM 18

41

19

TRD

TVDP

Track Counterand Timer

R706

C708

GND

MIRR

TE1

TZC

TE

IP2MIRR

C117

GND

7

45

3-2-1. Tracking Servo

The aim of tracking servo is to make laser beam trace the data track on disc.

Tracking Error(TE) Signal is generated from tracking error detected block in HD153721 using DPP(DifferentialPush-Pull) Method(CD) and PP(Push-Pull) Method(DVD).DPP Method uses not only main beam(EF1~EF4) but also side beam(E, F) for correcting DC offset generatedin Push-Pull Method.

The remaining procedure of TE signal processing in HD62604 is similar to Focus Servo.The role of DSP IC(HD62604) is Tracking Digital Controller.TE Signal is input to DSP IC(HD62604 33pin), and after A/D Conversion, Digital Equalizer Block and D/AConversion in HD62604, the output signal TRD(HD62604 41pin) is input to Drive IC( 23pin).

The drive output signal TRK+/TRK- generated according TKIN(BD7905 52pin), and drives tracking actuator inthe P/U unit.

3-2-2. Sled Servo

The working distance of tracking actuator is too short to cover whole disc radius.Sled Servo make P/U move by little and little so that the laser beam keep tracing the data track on disccontinuously when tracking actuator reaches the working limit.

TE Signal is input to DSP IC(HD62604 33pin), and after A/D Conversion, Digital Tracking Equalizer Block,Digital Sled Compensator Block and PWM Conversion in HD62604, the output signal TVDN, TVDP(HD6260418, 19pin) is input to SDAC(BU2507), After that to Drive IC (BD7905 28, 29pin) after Low-Pass filtering.The PWM output signal A+, A-, B+, B- generated according to SLIN1, SLIN2, and drives the sled motor.

4. Spindle Circuit4-1-1. Block Diagram(FGCAV Servo)

46

DiscMotor unit

OpticalPick-up

HOP-8511T

XTALOControl Clock

Generator

IC701HD62604

127

MUX

PWM

DMO

20

Motor KickREG

CAV FD+

CAV PD

SFG

VCK4M

VCK4M 126

R610

C606

SPIN

IC601

BD7905

U

V

MUTE2

MUTE1

VC1.65

24

22

23

9

11

HU+

2 HU-

21

C601

HV+

HV-

3

4

HW+

HW-

5

6

1

27

SPIN

SFG

CTL2

CTL1

C602

C603

SPIN

FG

W 18

XTALI

17

R854

3.3V

X70233.8688MHz

4-1-2. FG CAV Servo

1) CD 24x CAV : CD-RW2) CD 32x CAV : CD-R, CD-ROM3) DVD 8x CAV : DVD+RW, DVD+R, DVD-ROM dual4) DVD 12x CAV : DVD-ROM(single)

When drive read PRESS CD, Closed Session CD-R/RW, the spindle motor is controlled using FG CAV SpindleServo. FG signal(BD7905 21pin) input to FGIN in DSP IC(IC701 17pin).The spindle controller in DSP IC uses FGIN as spindle rotation frequency feedback, therefore the FG CAVSpindle Servo doesn't work well if FG generation is abnormal.

The spindle controller PWM output signal DMO(IC701 20pin) input to SPIN in Drive IC(BD7905 24pin) after Low-Pass Filtering. The PWM output signal U, V, W signal(BD7905 9,11,18) drives Spindle Motor using Hall Sensor Output signal(HU+, HU-, HV+, HV-, HW+, HW-) and SPIN, and FG pulse output is generated as 18 pulses/rotation.

4-2-1. Block Diagram (Wobble CLV Servo)

47

DiscMotor uni t Optical

Pick-upHOP-8511T

IC101HD153721TF

HPFS/H

-

+

WBLSH

C107

86

87

88

89

95

96

97

98

HPF AGC2

HPFBPF AGC3

HPF

HPF47

35WBLSH

21 22

AGC1

23

VREF

WAG1 WAG2 WAG3

SA

SB

SC

SD

MA

MB

MC

MD

+

-

C108 C109

ADO

BCO

IC701HD62604

MUX

PWM

SPD

PH

SP20

Motor KickREG

94C606

R610

SPD

WOBSIG

4-2-2. Wobble CLV Servo DVD-RAM: 2x, 3x / DVD-R: 4x, 2x, 1x / DVD+R: 4x, 2.4x / DVD-RW: 1x, 2x/ DVD+RW: 2.4x / CD-R 4x, 8x, 12x, 16x, 20x, 24x / CD-RW: 4x, 8x, 12, 16x

When drive write DVD-RAM/R/RW/+R/+RW/CD-R/CD-RW, the spindle motor is controlled using Wobble CLVSpindle Servo.

The WOBSIG signal(HD153721 47pin) input to DSP IC(HD62604 94pin). The DSP Controller in HD62604 usesWOBSIG as linear velocity feed back, therefore the Wobble CLV Spindle Servo doesn’t work well whenWOBSIG signal is abnormal.

The spindle controller PWM output signal SPD (HD6260420pin) input to SPIN in Drive IC(BD7905 24pin) afterLow-Pass Filtering. The PWM output signal U,V, W signal(BD7905 9,11,18) drives Spindle Motor using Hall Sensor Output signal(HU+, HU-, HV+, HV-, HW+, HW-) and SPIN.

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTIONIC101 (HD153721TF) : RF AMP Analog Signal Processor

Pin Assignment

48

75

AG

FU

74

AG

HP

F

73

VC

C1

72

EQ

HP

F

71

EQ

OS

/RR

F/W

RF

70

EQ

OP

69

EQ

ON

68G

ND

167

IRE

FE

66

EQ

FC

F

65 64

SU

BO

/LP

PM

ON

63

SU

BI/L

PP

SIG

62

TO

PH

61

BO

TH

60

MIR

RH

PF

59

MIR

RT

OP

H

58

MIR

RB

OT

H

57

VD

D

56

MR

ST

B

55

SD

EN

54

SD

ATA

53

SC

LK

52

DF

T

51

VC

C4

50 MCLK

49 IP1/LPPOUT

48 IP2/MIRR

47 WOBSIG

46 RDGATE

45 LO_ZB/SPDSH

44 IDGATE

43

BLANK42

RECD141

PWDETO40

TZC39

GND438

MPDSH/SPDSH

37

RFPDSH

36

WFPDSH

35

WGATE

34

RLDON

33

SPBLVL/TISH2

32

LNDTRK

31

WBLSH

30

GND529

BHC28

VCC527

AWOBSIG26

RFHLD/TISH1

76

77

SUMF

78RFIP

79RFIN

80IREFT

81VREF1

82VCC2

83HAVC

84

SA

85

SB

86

SC

87

SD

88

TRP

89

TRN

90

FOP

91

FON

92

MA

93

MB

94

MC

95

MD

96

GND2

97

LPSIN1

98

LPSIN2

99

100

FE PE

TE

WR

FIN

TE

IN

SIG

M

BC

EN

T

PH

BE

TA/T

CE

BH

BE

TA/T

IE

VC

C3

FV

RE

F

FM

D

GN

D3

AT

ES

T

RR

EF

LDO

UT

VR

DC

VR

DC

2N/P

WR

MO

N

VR

DC

N

WA

G1

WA

G2

WA

G3

WO

BF

CF

HD153721TF(TOP VIEW)

AG

FR

HAVC2

LPS

_A

LPS

_B

SRVREF

SUMF2

Block Diagram

49

RFIP

RFIN

SUMFA

GH

PF

RF SUM/SUB

(RGA)

RFAGC

RFEQ

IDDET

PickI/F

TE

DPD

PE

HFSUM

LE

FE

WRF

SIGM

VREF

APC

0.068u

0.068uHP2

LO

_ZB

/

RD

GA

TE

RFH

LD

/

AG

FU

AG

FR

HP

EQ

HPF

IDG

AT

E

EQ-AUTO

IRE

FE

EQ

FCF

EQOP

EQON

EQOS/RRF/WRF

MA

MB

MC

MD

SA

SB

SC

SD

TRP

TRN

FOP

FON

HAVC

S// H

MPDSH/

4

4

FOPFON

MUX

2

SUBO/LPPMON

SUBI /LPPSIG

MUX

Wobble

AGC1

AGC2SUB BPF AGC3

F0-CNT.

COMP

LPP

MUX

BHC

IP1/LPPOUTD

WOBSIG

WAG3

WAG1

WAG2

WBLSH

MCLK

WOB

2

S

S / H

S / H

/ H

TE“TE

TRP/N

BALANCE

BALANCE FE

PEHFPE

TZC TZC

TEIN

mclk

IREFT

VREF1

RRF

WRF

RECDRECD1

BLANK

MIRRDEFECT

TOPH

BOTH

DFT

RECD

TIE SPBLVL/TISH2

PHBETA/TCEBHBETA/TIE

SerialCont.Reg.

MRSTB

SDEN

SCLK

SDATA

OPC

BCENT

SPBLVL

SIGM

WGATE

RLDON

WFPDSH

RFPDSH

FMD

FVREF

PWR

MO

N

VR

DC

N

VR

DC

RR

EF

PWD

ET

O

BHOUT

3.3V power

Digitalpower RF system power

Analog power

PowerCont.

0.01

u

10u

20k(*1)

0.068u0.033u

0.33u

0.33u

0.22u

12k(*2)

3300p 0.1u

3900p1500p

D

D

D

LO_ZB/SPDSH

D

D

D

D

D

D

D

D

D

D

D

D

D

D/A

D

D

DDDD

SUBP,N

IP2/MIRR

SUBW

BPO

MIRR, DEFECT

EQOP/N

BPO

2200p

SPDSH

RRFWRF

SPD

SH

TIS

H1

RFHLD/TISH1

RFHLD/TISH1

VR

DC

2N/

VC

C3

GN

D3

-- - -

VC

C2

GN

D2

VC

C1

GN

D1

VC

C4

GN

D4

VC

C5

GN

D5

VD

D

VREF1

-

4700p

15,000p

VREF1

VREF1

LD

OU

T

-

GCAOUT

MIRRTOPH

MIRRBOTH

MIRRHPF

1.65V

LPSIN1

LPSIN2

WRFINMUX

AWOBSIG

WOBFCF

VREF1

HAVC2-SRVREF

OPC

SRVREF

LO_ZB/SPDSH

PWWMON

DLNDTRK

mclk

mclk

mclk

SHPE

LPS_A

LPS_B

ATEST

SUM

F282

00p

680k

3.3u

0.068u

*3300p/0.068u

RF system power RF system power

0.068u

0.47u

0.22u 0.033u

0.033u

LPF

toLPF,A/D

toLPF,A/DtoLPF,A/D

toLPF,A/D

toLPF,A/D

toLPF,A/D

toLPF,A/D

toLPF,A/D

toLPF,A/D

*HPF fc=1kHz

toA/D

LPF

0.1u

50

• Pin Description

Pin no. Pin Name Type Function

1 LPS-A Analog-Output Lens shift signal output port.

2 LPS-B Analog-Output Lens shift signal output port.

3 FE Analog-Output Focus error output port.

4. PE Analog-Output PE output.

5 TE Analog-Output Tracking error output port.

6 WRFIN Analog-Input WRF signal input port.

7 TEIN Analog-Input TZC detection TE signal input port.

8 SIGM Analog-Output Analog signal monitor output port.

9 BCENT Analog-Output OPC center signal output port.

10 PHBETA/TCE Analog-Output OPC top hold level signal & APC light sampling signaloutput/Tilt servo detection output port.

11 BHBETA/TIE Analog-Output OPC bottom hold level signal & R-OPC light samplingsignal output/Tilt servo detection output port.

12 VCC3 Power Power.

13 FVREF Analog-Input APC Reference voltage input port.

14 FMD Analog-Input APC monitor diode input.

15 GND3 Ground Ground.

16 LDOUT Analog-Output APC Read laser driver control port.

17 RREF Analog-Output APC Read setting reference voltage output port.

18 VRDC2N/PWRMON External-capacitor required APC Read laser driver control filter connecting port/SHmonitor output.

19 VRDCN External-components required APC Read laser driver control filter connecting port.

20 VRDC External-components required APC Read laser driver control filter connecting port.

21 WAG1 External-capacitor required WOBBLE AGC detector capacity connecting port.

22 WAG2

23 WAG3

24 WOBFCF External-capacitor required OB-BPF Automatic control External capacityconnecting port.

25 ATEST Analog-Output Analog test signal output port.

26 AWOBSIG Analog-Output Analog level Wobble signal output port.


28 BHC External-capacitor required External capacity connecting port for LPP bottom hold.


30 LNDTRK Digital-Input Balance control mode selecting.

31 SPBLVL/TISH2 Digital-Input R-OPC WRF signal sampling pulse input port/Tilt servodetection sampling pulse input port.

32 RFPDSH Digital-Input APC Read laser driver output control.

33 WFPDSH Digital-Input Ground[Digital].

34 MPDSH/SPDSH Digital-Input Pick-Up input sampling pulse input port.

35 WBLSH Digital-Input WOBBLE sampling pulse input port.

36 WGATE Digital-Input Read/Write control input port.

51


37 RLDON Digital-Input APC Read laser driver output control.

38 GND4 Ground Ground[digital].

39 TZC Digital-Output Tracking zero cross signal digital output port.

40 PWDETO Digital-Output Laser diode over power detection output port.

41 RECD1 Digital-Output Write/non-write detection output port.

42 BLANK Digital-Output Write/non-write detection output port/BD detectionoutput port.

43 RFHLD/TISH1 Digital-Input RF hold control signal input port.

44 IDGATE Digital-Input ID Select pulse input port.

45 LO_ZB/SPDSH Digital-Input Low-z [inversion] pulse input port.

46 RDGATE Digital-Input Read gate signal input port.

47 WOBSIG Digital-Output WOBBLE signal output port.

48 IP2/MIRR Digital-Output ID detection signal output port/Mirror detection outputport.

49 IP1/LPPOUT Digital-Output ID detection signal output port/LPP detection outputport.

50 MCLK Digital/Analog-Input Main clock input/Equalizer Automatic control clockinput/LPP output port.

51 VCC4 Power Power[digital].

52 DFT Digital-Output Defect detects output port.

53 SCLK Digital-Input Serial clock input port.

54 SDATA Digital-Input/Output Serial data output port.

55 SDEN Digital-Input Serial enable input port.

56 MRSTB Digital-Input Master-reset inversion input port.

57 VDD Power Digital output [power supply 3.3V].

58 MIRRHPF External-capacitor required Mirror envelops detection HPF capacity connectingport.

59 MIRRBOTH External-capacitor required Mirror envelops detection bottom hold capacityconnecting port.

60 MIRRTOPH External-capacitor required Mirror envelops detection top hold capacity connectingport.

61 BOTH External-capacitor required Envelops detection bottom hold capacity connectingport.

62 TOPH External-capacitor required Envelops detection top hold capacity connecting port.

63 SUBI/LPPSIG Analog-Input HPF input for ID detection / HPF input port for LPPdetection.

64 SUBO/LPPMON Analog-Output HPF output for ID detection / HPF output port for LPPdetection.

65 EQFCF External-capacitor required Automatic control External capacity connection for RFEqualizer.

66 IREFE External-resistor required External resistor connection for RF Equalizer setting.


52


68 EQON Differential-Output RF Equalizer differential output port.

69 EQOP Differential-Output RF Equalizer differential output port.

70 EQOS/RRF/WRF Analog-Output RF Equalizer single output port.

71 RQHPF External-capacitor required AGC-DET input high path filter capacity connectingport.


73 AGHPF External-capacitor required High path filter capacity connection for AGC.

74 AGFU External-capacitor required AGC filter connecting port.

75 AGFR External-capacitor required AGC filter connecting port.

76 SUMF Analog-Input/ SUM RF input/SUM differential AMP DC filterconnecting port.

77 SUMF2 Analog-Input SUM RF input.

78 RFIP Differential-Input RF differential input port.

79 RFIN Differential-Input RF differential input port.

80 IREFT External-resistor required External resistor connecting port for reference currentsetting.

81 VREF1 Analog-Output 2.1V reference bias voltage output port.


83 HAVC Analog-Input Pick-Up reference voltage input port.

84 HAVC2 Analog-Input Pick-Up reference voltage input port.

85 SRVREF Analog-Input DSP power voltage [3.3V] input.

86 SA Analog-Input Sub beam 4D input port.

87 SB

88 SC

89 SD

90 TRP Differential-Input Tracking error differential direct input port.

91 TRN

92 FOP Differential-Input Focus error differential direct input port.

93 FON


95 MA Analog-Input Main beam 4D input port.

96 MB

97 MC

98 MD

99 LPSIN1 Analog-Input Lens shift signal input port.

100 LPSIN2 Analog-Input Lens shift signal input port.

External-capacitor required

53

IC701 (HD62604FDV) : Encoder, Decoder & DSP Singal Processor

1.1 Pin Layout

1SCLK

256S

DATA

255R

D0

254R

D15

253R

D1

252R

D14

251V

SS

IO250

VC

CIO

249R

D2

248R

D13

247R

D3

246R

D12

245R

D4

244R

D11

243R

D5

242R

D10

241V

SS

IO240

VC

CIO

239R

D6

238R

D9

237R

D7

236R

D8

235D

QM

L234

DW

EB

233D

QM

U232

DC

AS

B231

VS

SIO

230V

CC

IO229

RA

MC

LK228

VS

S227

VD

D226

DR

AS

B225

DC

KE

224R

A13

223R

A11

222R

A9

221R

A10

220R

A10

219R

A8

218V

SS

IO217

VC

CIO

216R

A0

215R

A7

214R

A1

213R

A6

212R

A2

211R

A5

210R

A3

209R

A4

208T

ES

TB

207T

ES

T0

206T

ES

T1

205D

AS

PB

204C

S3F

XB

203C

S1F

XB

202D

A2

201D

A0

200P

DIA

GB

199V

CC

IO198

VS

SIO

197D

A1

196IO

CS

16B195

HIN

TR

Q194

DA

CK

B193

IOR

DY

2RFDEN3WDEN4UDBUSY5VCCIO6VSSIO7TRDP8TRDN9TLDP10TLDN11VDD12VSS13FODP14FODN

18TVDP19TVDN20SPD21PWN22DEFECT23BLANK24TZC25TEST326TEST2

32VCCA

38VSSA

44VSSA

46VCCA

61VCCA62VSSA

27FE

15ENC1

192 ZIORB191 ZIOWB190 DREQ189188

DATA15VDD

187 VSS

183 VCCIO182 VSSIO

178 VSSIO

174 VCCIO173 VSSIO

169 VSSIO

165 VCCIO164 VSSIO

162 VSS161 VDD

152 VSSIO151 VCCIO

160 CPU0159 CPU1158 CPU2157 CPU3156 CPU4155 CPU5154 CPU6153 CPU7

150 A0149 A1148 A2147 A3146 A4145 A5144 A6143 A7142 A8141 A9140 A10139 CSB138 CPRDB137 CPWRB136 INT2B135 INT1B134 INT1B133 ADGATEB132 FOK131 STANDBYB130 MRSTB129 DOUT128

VS

SA

127X

CO

126X

CI

106LN

DT

RK

105W

RS

TOP

104S

RF

2103

WR

GAT

E

100IP

2MIR

R99

IP1LP

PIN

98R

FH

LD97

IDG

ATE

96LO

WZ

B95

RD

GAT

E94

WO

BS

IG93

LSR

ER

R92

TC

SH

SP

BLV

89R

FP

DS

H88

WF

PD

SH

87M

PD

SH

86W

BLS

H85

WR

GAT

E2

84LS

RO

N83

FE

MC

K

80W

RC

KR

AM

125V

CC

A124

VS

SA

123R

OU

T122

VC

CA

121LO

UT

120A

DIP

VR

B119

VC

CA

114V

SS

A

112V

CC

A

107V

SS

A

102V

SS

IO101

VC

CIO

91V

SS

90V

DD

82V

SS

IO81

VC

CIO

78V

SS

A77

VC

CA

68V

CC

A

66V

SS

A

118A

DIP

VR

1117

AD

IPV

RT

186 DATA0185 DATA14184 DATA1



172 DATA10171 TATA5170 DATA9


163 HRSTB

16ENC217SFG

28PE29SF30GFTIBH31BCENT

33TE34LPSAGT35LPSB36TCPH37ST

39FOD40DAVC41TRD42MONANA043MONANA1

45VISTRB

47DCLPF048DRLPF049DCLPF150DRLPF151DCLPF252DRLPF253JFH54JFF055JFF156DFF057DFF158VREF3359EFMN60EFMP

116A

DIP

NN

115A

DIP

INP

113A

DIPA

GN

I

111D

CLK

B110

DC

LD109

NR

Z1B

108N

RZ

1

79V

IRE

F2

76R

2CLP

F2

75R

2RLP

F2

74R

2RLP

F2

73R

2CLP

F1

72R

2RLP

F0

71R

2CLP

F0

70R

1RLP

F69

R1C

LPF

67V

IRE

F1

65V

RE

FC

63VIBIAS64 VREF

: Analog

HD62604FDVTop View

: Standard Input/Ouptut: 5V Tolerant Input/Output: Power/Earth

1.2 Block Diagram

54

DataSlicer

VREFVREF33 BIAS

Ref-PLL

ADIPDetector

DataStrobe

Demodulate

DAC

ADC*2

Servo

CD-ROMDecoder

DVDPI-ECU

DVDPO-ECU

DRAMControl

MCIF

ATAPI

AUDIO

DRAMInterFace

ClockGenerator

TestControl

Serial IF

VIBIAS

EFMPEFMN

JFHDCLPF[2:0]DRLPF[2:0]

VISTRB

IP1LPPINIP2MIRR

RDGATELOWZBIDGATERFHLD

R1CLPFR1RLPF

ADCADIPINP

LPPDetector

WobbleGeneratorWOBSIG

JitterCounter

CD-DSP

CAVAUDIO

Modulator

NRZI,NRZIB LVDSDCLK,DCLKBWRGATE[1:2]

SRFWRSTOP

Sample

Hold

SPBLVLWBLSHMPDSH

WFPDSHRFPDSHSPRFTR

CDCD-ROMEncoder

LSRON

SFG

MONANA[1:2]FETE

LPSAGTPE

TZCBLANK

SFST

TCPHGFTIBH

LPSBBCENT

FODDAVC

TRD

ENC[1:2]/SLB[P:N]

DEFECT

TLD[P:N]TVD[P:N]/SLA[P:N]

TRD[P:N]FOD[P:N]

XCIXCO

WRCKRAM

SDATARFDEN

SCLK

WDENLDBUSY

FEMCK

STANDBYB

TEST[3:0]

MRSTB

TESTB

ROUTDOUT

LOUT

DVDDescramble

DVDScramble

Auth

BCA

SSEQ

MSEQ

RA[13:0]

DWE

RD[15:0]

DRASDCAS

RAMCLK

DQMUDQML

DACK

CS3FXB

DREQ

CS1FXBPDIAG

DASPB

DA2

IOCS16B

IORDY

ZIOWB

HINTRQ

HRSTB

ZIORB

DATA [15:0]

DA1DA0

ADGATEBINT0B,INT1B,INT2BFOKCPWRBCPRDBCSBA[10:0]D[7:0]

JFF[1:0]DFF[1:0]

TCSHSPBLV

LSRERR

DCKE

R2CLPF[2:0]R2RLPF[2:0]

VIREF[1:2]

55

Pin No. Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name

1 2B SCLK 33 4L TE 65 2W VREFC 97 11U IDGATE

2 2C RFDEN 34 1M LPSAGT 66 3W VSSA 98 12Y RFHLD

3 2D WDEN 35 3L LPSB 67 4W VIREF1 99 11V IP1LPPIN

4 1B LDBUSY 36 2L TCPH 68 2Y VCCA 100 11W IP2MIRR

5 2E VCCIO 37 4M ST 69 5W R1CLPF 101 12U VCCIO

6 3E VSSIO 38 1N VSSA 70 5V R1RLPF 102 13Y VSSIO

7 1C TRDP 39 3M FOD 71 3Y R2CLPF0 103 12V WRGATEB

8 3D TRDN 40 2M DAVC 72 4V R2RLPF0 104 12W SRF2

9 1D TLDP 41 4N TRD 73 4Y R2CLPF1 105 13U WRSTOP

10 4E TLDN 42 1P MONANA0 74 5U R2RLPF1 106 14Y LNDTRK

11 2F VDD 43 3N MONANA1 75 6W R2RLPF2 107 13V VSSA

12 3F VSS 44 2N VSSA 76 6V R2CLPF2 108 13W NRZI

13 1E FODP 45 4P VISTRB 77 5Y VCCA 109 14U NRZIB

14 4F FODN 46 1R VCCA 78 6U VSSA 110 15Y DCLK

15 2G ENC1 47 3P DCLPF0 79 7W VIREF2 111 14V DCLKB

16 3G ENC2 48 1T DRLPF0 80 7V WRCKRAM 112 16Y VCCA

17 1F SFG 49 4R DCLPF1 81 6Y VCCIO 113 15U ADIPAGNI

18 4G TVDP 50 2P DRLPF1 82 7U VSSIO 114 14W VSSA

19 2H TVDN 51 3R DCLPF2 83 8W FEMCK 115 15V ADIPINP

20 3H SPD 52 1U DRLPF2 84 8V LSRON 116 17Y ADIPINN

21 1G PWM 53 4T JFH 85 7Y WRGATE2 117 16U ADIPVRT

22 4H DEFECT 54 2R JFF0 86 8U WBLSH 118 15W ADIPVR1

23 1H BLANK 55 4U JFF1 87 8Y MPDSH 119 17U VCCA

24 3J TZC 56 1V DFF0 88 9V WFPDSH 120 18Y ADIPVRB

25 2J TEST3 57 2U DFF1 89 9W RFPDSH 121 17W LOUT

26 4J TEST2 58 1W VREF33 90 9U VDD 122 19Y VCCA

27 1J FE 59 3V EFMN 91 9Y VSS 123 18V ROUT

28 3K PE 60 2T EFMP 92 10V TCSHSPBLV 124 16W VSSA

29 2K SF 61 3T VCCA 93 10W LSRERR 125 16V VCCA

30 4K GFTIBH 62 3U VSSA 94 10U WOBSIG 126 17V XCI

31 1K BCENT 63 2V VIBIAS 95 10Y RDGATE 127 18W XCO

32 1L VCCA 64 1Y VREF 96 11Y LOWZB 128 20Y VSSA

1.3 Pin Table

56

Pin No. Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name Pin

No.

Ball

No.

Pin Name

129 19W DOUT 161 17K VDD 193 19B IORDY 225 10D DCKE

130 19V MRSTB 162 20J VSS 194 18B DACKB 226 9A DRASB

131 19U STANDBYB 163 18K HRSTB 195 17B HINTRQ 227 10C VDD

132 20W FOK 164 19K VSSIO 196 19A IOCS16B 228 10B VSS

133 19T ADGATEB 165 17J VCCIO 197 16B DA1 229 9D RAMCLK

134 18T INT0B 166 20H DATA7 198 16C VSSIO 230 8A VCCIO

135 20V INT1B 167 18J DATA8 199 18A VCCIO 231 9C VSSIO

136 18U INT2B 168 19J DATA6 200 17C PDIAGB 232 9B DCASB

137 20U CPWRB 169 17H VSSIO 201 17A DA0 233 8D DQMU

138 17T CPRDB 170 20G DATA9 202 16D DA2 234 7A DWEB

139 19R CSB 171 18H DATA5 203 15B CS1FXB 235 8C DQML

140 18R A10 172 19H DATA10 204 15C CS3FXB 236 8B RD8

141 20T A9 173 17G VSSIO 205 16A DASPB 237 7D RD7

142 17R A8 174 20F VCCIO 206 15D TEST1 238 6A RD9

143 19P A7 175 18G DATA4 207 14B TEST0 239 7C RD6

144 18P A6 176 20E DATA11 208 14C TESTB 240 5A VCCIO

145 20R A5 177 17F DATA3 209 15A RA4 241 6D VSSIO

146 17P A4 178 19G VSSIO 210 14D RA3 242 7B RD10

147 19N A3 179 18F DATA12 211 13B RA5 243 6C RD5

148 18N A2 180 20D DATA2 212 13C RA2 244 4A RD11

149 20P A1 181 17E DATA13 213 14A RA6 245 5D RD4

150 17N A0 182 19F VSSIO 214 13D RA1 246 6B RD12

151 20N VCCIO 183 17D VCCIO 215 13A RA7 247 4D RD3

152 18M VSSIO 184 20C DATA1 216 12C RA0 248 3A RD13

153 19M CPU7 185 19D DATA14 217 12B VCCIO 249 4B RD2

154 17M CPU6 186 20B DATA0 218 12D VSSIO 250 2A VCCIO

155 20M CPU5 187 18C VSS 219 12A RA8 251 3C VSSIO

156 18L CPU4 188 19E VDD 220 11C RA10 252 5B RD14

157 19L CPU3 189 18E DATA15 221 11B RA9 253 5C RD1

158 17L CPU2 190 18D DREQ 222 11D RA12 254 4C RD15

159 20L CPU1 191 19C ZIOWB 223 11A RA11 255 3B RD0

160 20K CPU0 192 20A ZIORB 224 10A RA13 256 1A SDATA

57

1.4 Pin FunctionIt corresponds to the following signs as a pin I/O specification.

AI : Analog InputAO : Analog OutputAIO : Analog Input/OutputI : Standard InputO : Standard OutputTO : Standard Three State OutputIO : Standard Input/Output

IOU : Standard Input/Output with Pull Up5I : 5V Tolerant Input5O : 5V Tolerant Output5TO : 5V Tolerant Three State Output5IO : 5V Tolerant Input/OutputPW : Power Supply PinGND : Earth Pin

1.4.1 DataStrobe Pin List

Pin Name Pin No. Ball No. I/O Destination Function

EFMP

EFMN

60

59

2T

3V

AI AFE EFM Signal Input Pin(Difference input)

DFF1

DFF0

57

56

2V

1V

AO External Capacitor Duty Feedback-LPF connecting port

JFF1

JFF0

55

54

4U

2R

AO External

Components

Jitter Feedback-LPF connecting port

JFH 53 4T AO External Capacitor Jitter Feedback-BPF connecting port

VREF33 58 1W AO External Capacitor Reference Voltage Output Pin of EFM Slice

DCLPF2

DRLPF2

DCLPF1

DRLPF1

DCLPF0

DRLPF0

51

52

49

50

47

48

3R

1U

4R

2P

3P

1T

AO External

Components

Loop filter for Data PLL

VISTRB 45 4P AO External Resistance Resistance Connected for Control Current of

Data PLL

R1CLPF

R1RLPF

69

70

5W

5V

AO External

Components

Loop filter for Reference PLL1

R2CLPF2

R2RLPF2

R2CLPF1

R2RLPF1

R2CLPF0

R2RLPF0

76

75

73

74

71

72

6V

6W

4Y

5U

3Y

4V

AO External

Components

Loop filter for Reference PLL2

VIREF1 67 4W AO External Resistance Resistance Connected for Control Current of

Reference PLL1

VIREF2 79 7W AO External Resistance Resistance Connected for Control Current of

Reference PLL2

VIBIAS 63 2V AO External Resistance Resistance Connected for Reference Current of

bias system

VREF

VREFC

64

65

1Y

2W

AO External Capacitor Reference Voltage Output Pin of PLL

MONANA1

MONANA0

43

42

3N

1P

AO External

Components

Analog Signal Monitor of Data Strobe

58

1.4.2 Servo Pin List


FE 27 1J AI AFE Focus Error Input Pin

TE 33 4L AI AFE Tracking Error Input Pin

LPSAGT 34 1M AI AFE Lens Positioning A & GT Signal Input Pin

PE 28 3K AI AFE PE Signal Input Pin

SF 29 2K AI External

Components

Focus Shock Signal Input Pin

ST 37 4M AI External

Components

Tracking Shock Signal Input Pin

TCPH 36 2L AI AFE Tracking center / PHBETA

GFTIBH 30 4K AI AFE A reverse focusing /tilt error / BETA bottom hold

BCENT 31 1K AI AFE BETA Center

LPSB 35 3L AI AFE Lens Positioning B

FOD 39 3M AO DRVR Focus Control Signal Output Pin

TRD 41 4N AO DRVR Tracking Control Signal Output Pin

DAVC 40 2M AO External Capacitor Reference Voltage Output Pin of Servo DAC

TZC 24 3J I AFE Input Pin for Tracking Zero Crossing Signal

Detection

BLANK 23 1H I AFE Input Pin for BLANK Detection

FODP

FODN

13

14

1E

4F

TO DRVR Focus Drive Signal Output

TRDP

TRDN

7

8

1C

3D

TO DRVR Tracking Drive Signal Output Pin

TLDP

TLDN

9

10

1D

34E

TO DRVR Tilt Drive Signal Output Pin

ENC1/SLBP

ENC2/SLBN

15

16

2G

3G

5IO DRVR Encode Pulse Input Pin

This terminal can set the ENCODE pulse input

and the stepping motor control output by the

register.

TVDP/SLAP

TVDN/SLAN

18

19

4G

2H

TO DRVR DC Motor Control Output Pin

This terminal can set the DC motor slider control

output and the stepping motor control output by

the register.

SPD 20 3H TO DRVR Spindle Control Output Pin

PWM 21 1G TO Reference PWM

SFG 17 1F 5I DRVR Spindle FG Input Pin

DEFECT 22 4H I AFE DEFECT Detection Input Pin

59

1.4.3 DRAM Interface Pin list


RA[13:0] 224,222,

223,220,

221,219,

215,213,

211,209,

210,212,

214,216

10A,11D,

11A,11C,

11C,12A,

13A,14A,

13B,15A,

14D,13C,

13D,12C

O DRAM DRAM Address

RD[15:0] 254,252,

248,246,

244,242,

238,236,

237,239,

243,245,

247,249,

253,255

4C,5B,

3A,6B,

4B,7B,

6A,8B,

7D,7C,

6C,5D,

4D,4B,

5C,3B

IOU DRAM DRAM Data

DRASB 226 9A O DRAM DRAM Low address strobe

DCASB 232 9B O DRAM DRAM Column address strobe

DWEB 234 7A O DRAM DRAM Write enable

DQMU

DQML

233

235

8D

8C

O DRAM DRAM DQ Mask enable

DCKE 225 10D O DRAM DRAM Clock enable

RAMCLK 229 9D O DRAM DRAM Clock

60

1.4.4 ATAPI Interface Pin List


HRSTB 163 18K 5I ATAPI ATA Drive reset

DA2

DA1

DA0

202

197

201

16D

16B

17A

5I ATAPI ATA Address

DATA[15:0] 189,185,

181,179,

176,172,

170,167,

166,168,

171,175,

177,180,

184,186

18E,19D,

17E,18F,

20E,19H

20G,18J,

20H,19J,

18H,18G,

17F,20D,

20C,20B

5IO ATAPI ATA Data

CS1FXB

CS3FXB

203

204

15B

15C

5I ATAPI ATA Tip selection

IOCS16B 196 19A 5TO ATAPI ATA16bitpI/O

HINTRQ 195 17B 5TO ATAPI ATA interruption request

DASPB 205 16A 5IO ATAPI ATA drive -- active

PDIAGB 200 17C 5IO ATAPI ATA drive diagnosis

DREQ 190 18D 5TO ATAPI ATA DMA request

DACKB 194 18B 5I ATAPI ATA DMA Acknowledge

IORDY 193 19B 5TO ATAPI ATA I/O channel ready

ZIORB 192 20A 5I ATAPI ATA I/O Read

ZIOWB 191 19C 5I ATAPI ATA I/O Write

61

1.4.5 Encoder Interface Pin List


WRGATE2 85 7Y O AFE Write Control Signal Output Pin for AFE

WBLSH 86 8U O AFE Wobble signal sampling pulse

MPDSH 87 8Y O AFE Main beam sampling pulse

WFPDSH 88 9V O AFE The sampling pulse for laser control

RFPDSH 89 9W O AFE The sampling pulse for laser control

TCSHSPBLV 92 10V O AFE The terminal of a VFO1 track center signal sample

/ hold pulse it can change TCSH (VFO1 track

center signal sample & hold pulse) and SPBLV

(sampling pulse for Running OPC) by register

setup.

LSRERR 93 10W I AFE Laser Error Signal Input Pin

WOBSIG 94 10U I AFE Wobble Signal Input Pin

RDGATE 95 10Y O AFE PLL Input change signal

LOWZB/SPDSH 96 11Y O AFE The terminal of an input impedance change

control signal / sub beam sampling pulse it can

change LOWZB (input impedance change control

signal) and SPDSH (sub beam sampling pulse) by

register setup.

IDGATE 97 11U O AFE ID / data change signal

RFHLD 98 12Y O AFE The terminal of VFO3 flow part sample hold signal

it can change RFHLD (VFO3 flow part sample &

hold pulse), a track center S/H signal, and a focal

offset S/H signal by register setup.

IP1LPPIN 99 11V I AFE LPP [ a PID area discernment signal] input signal

IP2MIRR 100 11W I AFE MIRR [ a PID area discernment signal] input signal

NRZI

NRZIB

108

109

13W

14U

AO LDD After modulation NRZI output (differential) -- this

terminal serves as a LVDS output.

DCLK

DCLKB

110

111

15Y

14V

AO LDD NRZI synchronous clock (differential) -- this

terminal serves as a LVDS output.

LSRON 84 8V O LDD Laser On/Off signal Output Pin

WRGATEB 103 12V O LDD Write Control Signal Output Pin for LD

SRF2 104 12W O OPIC I-V amplifier gain change

WRSTOP 105 13U I LDD Write Stop Signal Input Pin

LNDTRK 106 14Y O LDD

AFE

land / groove change

ADIPINP 115 15V AI AFE The input for ADIP detection

ADIPINN 116 17Y AI External

Components

Reference voltage input terminal

ADIPAGNI 113 15U AO External Capacitor ADC conversion control voltage output terminal

ADIPVRT 117 16U AO External Capacitor ADC conversion reference voltage output terminal

ADIPVR1 118 15W AO External Capacitor ADC reference voltage output terminal

ADIPVRB 120 18Y AO External Capacitor ADC conversion reference voltage output terminal

62

1.4.6 Serial Communication Interface Pin List


SDATA 256 1A IO LD

AFE

IF serial data for RF,LDD

SCLK 1 2B O LD

AFE

IF serial transmission clock for RF,LDD

RFDEN 2 2C O AFE IF transmission signal for RF

WDEN 3 2D O LD IF transmission signal for LDD

LDBUSY 4 1B I LD IF transmission busy signal for LDD

1.4.7 Audio Interface Pin List


DOUT 129 19W TO ATAPI Audio Digital Output Pin

LOUT

ROUT

121

123

17W

18V

AO ATAPI Audio Analog Output Pin

1.4.8 Clock Generator Pin List


XCI 126 17V I X’TAL X ’tal Oscillation Input Pin

XCO 127 18W IO X’TAL X ’tal Oscillation Output Pin

WRCKRAM 80 7V I Oscillation Module X ’tal Oscillation Input Pin

FEMCK 83 8W O AFE AFE Master Clock Output Pin

1.4.9 Microcomputer Interface Pin List


A[10:0] 140,

141,142,

143,144,

145,146,

147,148,

149,150

18R,

20T,17R,

19P,18P,

20R,17P,

19N,18N,

20P,17N

I MPU MPU address bus

CPU[7:0] 153,154,

155,156,

157,158,

159,160

19M,17M,

20M,18L,

19L,17L,

20L,20K

IO MPU MPU data bus

CPWRB 137 20U I MPU MPU write-in pulse

CPRDB 138 17T I MPU MPU read-out pulse

CSB 139 19R I MPU MPU tip selection

INT0B 134 18T O MPU MPU interruption (only for DSP)

INT1B 135 20V O MPU MPU interruption (only for RAM Control& Servo)

INT2B 136 18U O MPU MPU interruption (only for ATAPI)

FOK 132 20W O MPU Focus OK flag

ADGATEB 133 19T O MPU The trigger signal for the MPU built-in ADC

63

1.4.10 LSI/TEST Control Pin List


MRSTB 130 19W I LSI master reset

STANDBYB 131 19U I LSI analog module standby

TESTB 208 14C I When it is made TEST mode selection

TESTB=LOW, TMON [3:0] serves as a test

control input terminal. Therefore, please do not

usually set this terminal to Active at the time of

operation.

TEST[3:0] 25,26,

206,207

2J,4J,

15D,14B

O _ By the register, a test monitor can be set up,

as shown in the following table.

T * SEL[3:0] TEST0 TEST1 TEST2 TEST3 Remarks

0 Servo monitor 0 Servo monitor 1 Servo monitor 2 Servo monitor 3

1 Data strobe 0 Data strobe 1 Data strobe 2 Data strobe 3

2 Audio 0 Audio1 Audio 2 Audio 3

3 DVD

modulation 0

DVD

modulation 1

DVD

modulation modulation 0 2

DVD

4 DVD-R/CD-R0 DVD-R/CD-R1 DVD-R/CD-R2 DVD-R/CD-R3

5 DVD+RW0 DVD+RW1 DVD+RW2 DVD+RW3

6 PI/C1 PI/C1 PI/C1 PI/C1

7 PO/C2 PO/C2 PO/C2 PO/C2

8 SLOCK SLOCK SLOCK SLOCK

9 DSYNC DSYNC DSYNC DSYNC

10 CLVCK CLVCK CLVCK CLVCK

11 BLEND BLEND BLEND BLEND

12 SYWINCOR SYWINCOR SYWINCOR SYWINCOR

13 PLL HIGH PLL HIGH PLL HIGH PLL HIGH

14

15

T * SEL : It corresponds to TEST3, TEST2, TEST1, and TEST0, and an individual setup the whole terminal is possible.

64

1.4.11 Power Pin List


VCCIO 5,81,

101,151,

165,174,

183,199,

217,230,

240,250

2E,6Y,

12U20N,

17J,20F,

17D,18A,

12B,8A,

5A,2A

PW _ Power supply (for Digital I/O 3.3V)

VCCA 32

46

61

68

77

112

119

122

125

1L

1R

3T

2Y

5Y

16Y

17U

19Y

16V

PW _ Power supply (for Servo ADC/DAC Block 3.3V)

for DPLL Block 3.3V

for SLICE Block 3.3V

for RPLL1&BIAS Block 3.3V

for RPLL2 Block 3.3V

for LVDS Block 3.3V

for ADIP ADC Block 3.3V

for Audio LPF Block 3.3V

for X’tal & PLL Block 3.3V

VDD 11,90,

161,188,

227

2F,9U,

17K,19E,

10C

PW _ Power supply(for Digital Logic 1.5V)

VSSIO 6,82,

102,152,

164,169,

173,178,

182,198,

218,231,

241,251

3E,7U,

13Y,18M,

19K,17H,

17G,19G,

19F,16C,

12D,9C,

6D,3C

GND _ Ground (for Digital I/O)

VSSA 38

44

62

66

78

107

114

124

128

1N

2N

3U

3W

6U

13V

14W

16W

20Y

GND _ Ground (for Servo ADC/DAC Block)

for DPLL Block

for SLICE Block

for RPLL1&BIAS Block

for RPLL2 Block

for LVDS Block

for ADIP ADC Block

for Audio LPF Block

for X’tal & PLL Block

VSS 12,91,

162,187,

228

3F,9Y,

20J,18C,

10B

GND _ Ground (for Digital Logic)

IC601 (BD7905BFS) : CD-ROM/DVD-ROM 6CH ACTUATOR DRIVER

Block Diagram

65

1 14 15 16 17 18 19 20 21 22 23 24 25 26 272 3 109 12 131164 5 7 8

54 41 40 39 38 37 36 35 34 33 32 31 30 29 2853 52 4546 43 42444951 50 48 47

PRELOGIC

FF

FFLIMIT

CurrentLIMIT

HALLBIAS

FG REVERSEDETECT

OSCPolarityCOMP

LIMITOSC

PRELOGIC

STBY/BRAKE

CONTROL

LEVELSHIFT

LEVELSHIFT

LEVELSHIFT

TSD

PRE LOGIC

+

-

+

-

67k

67k

188k

47k112.5k

75k

47k

47k

+-

+-

+

-

+

-

117.5k

117.5k

47k

47k

FG

DV

CC

HU

+

HU

-

HV

+

HV

-

HW

+

HW

-

HB

PG

ND

1 U

SP

VM1 V

GN

D

GN

D

GN

D

GN

D

GN

D

PG

ND

2 W

SP

VM2

SP

RN

F

FG

CT

L1

CT

L2

SP

IN

DG

ND

LDIN V

C

FC

IN

TK

IN

VC

C

LDO

+

LDO

-

TK

O+

TK

O-

FC

O+

FC

O-

AV

M

GN

D

GN

D

GN

D

GN

D

GN

D

AG

ND

SLO

1+

SLO

1-

SLO

2+

SLO

2-

SP

CN

F

SLR

NF

2

SLR

NF

1

SLV

DD

SLI

N2

SLI

N1

No Pin name Function1 HU+ HU+ signal input 2 HU- HU- signal input3 HV+ HV+ signal input4 HV- HV- signal input5 HW+ HW+ signal input6 HW- HW- signal input7 HB Bias for hall sensor8 PGND1 Spindle power GND19 U Spindle driver output U10 SPVM1 Spindle power supply input11 V Spindle driver output V 12 GND GND13 GND GND14 GND GND15 GND GND16 GND GND17 PGND2 Spindle power GND218 W Spindle driver output W19 SPVM2 Spindle power supply input20 SPRNF Spindle driver current power detection input21 FG FG signal output22 CTL1 Driver logic control input123 CTL2 Driver logic control input224 SPIN Spindle driver control input25 SPIN PWM GND26 LDIN Loading input27 Vc Reference voltage control input

No Pin name Function28 SLIN1 Motor driver input129 SLIN2 Motor driver input230 SLVDD Motor power supply 31 SLRNF1 Motor driver current power detection input132 SLRNF2 Motor driver current power detection input133 SPCNF Spindle driver filter port34 SLO2- Motor driver inverted output235 SLO2+ Motor driver non-inverted output136 SLO1- Motor driver inverted output137 SLO1+ Motor driver non-inverted output138 AGND BLT Motor driver power -GND39 GND GND40 GND GND41 GND GND42 GND GND43 GND GND44 AVM Actuator driver power supply45 FCO- Focus driver inverted output46 FCO+ Focus driver non-inverted output47 TKO- Tracking driver inverted output48 TKO+ Tracking driver non-inverted output49 LDO- Loading driver inverted output50 LDO+ Loading driver non-inverted output51 Vcc BTL free Loading driver power supply52 TKIN Tracking driver input53 FCIN Focus driver input54 DVcc PWM power supply control

Pin Description

Input/Output circuit diagram

66

Three-phase motor driver output

Hall signal input Splindle driver feedback filter pin

PWM driver output SLED1, 2

BTL driver input FO, TK, LD PWM driver input SLED1, 2 PWM driver input Spindle

BTL driver output FO, TK BTL driver output LD

Spindle driver current detection input Hall bias

FG signal output

10

8 17

19

18 11 9

3

1

5

54pin 54pin 54pin

4

2

6

31 32

35

37

34

36

45

47

46

48

51pin 51pin44pin

49 50

51pin 51pin51pin

7

54pin

21

54pin

52

26

53

51pin

51pin

47kΩ

Reference voltage input

28

29

30pin

54pin

47kΩ

33

54pin

10kΩ

24

54pin

54pin

112.5kΩ

Control signal input

22

23

54pin

54pin

50kΩ

50kΩ

50kΩ

20

51pin

312.5Ω

27

51pin

×3ch ×2ch

10kΩ

50kΩ

50kΩ

112.5kΩ

47kΩ 10kΩ 150kΩ

67

IC801 (µPD703101AGJ) : Microprocessor

Pin Assignment

INTP103/D MARQ3 / P07 1INTP102/D MARQ2 / P06 2INTP101/D MARQ1 / P05 3INTP100/D MARQ0 / P04 4

TI10/P03 5TCLR10/P02 6

TO101/P01 7TO100/P00 8

VSS 9IN TP113/DMAAK3/P17 10IN TP112/DMAAK2/P16 11IN TP111/DMAAK/1P15 12IN TP110/DMAAK0/P14 13

TI11/P13 14TCLR11/P12 15

TO111/P11 16TO110/P10 17

INTP123/TC3/P107 18INTP122/TC2/P106 19INTP121/TC1/P105 20INTP120/TC0/P104 21

TI12/P103 22TCLR12/P102 23

TO121/P101 24TO120/P100 25

ANI7/P77 26ANI6/P76 27ANI5/P75 28ANI4/P74 29ANI3/P73 30ANI2/P72 31ANI1/P71 32ANI0/P70 33

AVDD 34AVSS 35

AVREF 36

A16/ P60108A17/ P61107A18/ P62106A19/ P63105A20/ P64104A21/ P65103A22/ P66102A23/ P67101HVDD100CS0/RAS0/ P8099CS1/RAS1/ P8198CS2/RAS2/P8297CS3/RAS3/ P8396CS4/RAS4/IOWR/P8495CS5/ RAS5/IORD/P8594CS6/ RAS6/P8693CS7/RAS7/P8792LCAS/LWR/ P9091UCAS/ UWR/ P9190RD/P9289WE/P9388BCYST/P9487OE/P9586HLDAK/P9685HLDRQ/P9784VSS83REFRQ/PX582WAIT/PX681CLKOUT/PX780TO150/P12079TO151/P12178TCLR15/P12277TI15/P12376INTP150/P12475INTP151/P12574INTP152/P12673

VD

D14

4D

0/P

40

143

D1/

P4

114

2D

2/P

42

141

D3/

P4

314

0D

4/P

44

139

D5/

P4

513

8D

6/P

46

137

D7/

P4

713

6V

SS

135

D8/

P5

013

4D

9/P

51

133

D10

/P52

132

D11

/P53

131

D12

/P54

130

D13

/P55

129

D14

/P56

128

D15

/P57

127

HV

DD

126

A0/

PA

012

5A

1/P

A1

124

A2/

PA

212

3A

3/P

A3

122

A4/

PA

412

1A

5/P

A5

120

A6/

PA

611

9A

7/P

A7

118

VS

S11

7A

8/P

B0

116

A9/

PB

111

5A

10/

PB

211

4A

11/

PB

311

3A

12/

PB

411

2A

13/

PB

511

1A

14/

PB

611

0A

15/

PB

710

9

NM

I/P20

37P

2138

TX

D0

/SO

0/P

2239

RX

D0/

SI0

/P23

40S

CK

0/P

2441

TX

D1

/SO

1/P

2542

RXD

1/S

I1/P

2643

SC

K1

/P27

44V

DD

45IN

TP1

33/S

CK

2/P

3746

INT

P132

/SI2

/P36

47IN

TP1

31/S

O2/

P35

48IN

TP1

30/P

3449

TI1

3/P

3350

TC

LR13

/P32

51T

O13

1/P

31

52T

O13

0/P

3053

INT

P143

/SC

K3/

P11

754

INT

P142

/SI3

/P11

655

INT

P141

/SO

3/P

115

56IN

TP1

40/P

114

57T

I14/

P11

358

TC

LR14

/P11

259

TO

141/

P11

160

TO

140/

P11

061

CV

DD

62X

263

X1

64C

VS

S65

CK

SE

L66

MO

DE

067

MO

DE

1M

OD

E2

MO

DE

3

68 69 70R

ESE

T71

INT

P15

3/S

FT

RG

/P12

772

Block Diagram

68

PC

CPU

ALU

ParrelShifter

4kB

ROM

Main

RAM

INTC

RPU

UART0/CSI0

BRG0

UART1/CSI1

BRG1

CSI2

BRG2

CSI3

SIO

ADC

CG

NMI

INTP100- I NTP103, INTP110- I NTP113, INTP120- I NTP123, INTP130- I NTP133, INTP140- I NTP143, INTP150- I NTP153

TO100, TO101,TO110, TO111,TO120, TO121,TO130, TO131,TO140, TO141,TO150, TO151

TCLR10-TCLR15

TI10-TI15

SO0 /TXD0

SI0/RXD0SCK0

SO1/TXD1

SI1/ RXD1SCK1

PX

5-P

X7

SI2SCK2

SO3

SI3SCK3

ANI0-ANI7

AVREF

AVSS

AVDD

ADTRG

PB

0-P

B7

PA

0-P

A7

P1

20-

P12

7

P1

10-

P11

7

P1

00-

P10

7

P90

-P97

P80

-P87

P70

-P77

P60

-P67

P50

-P57

P40

-P47

P30

-P37

P21

-P27

P20

P10

-P17

P00

-P07

HV

DD

HLDRQ

HLDAK

SO2

CS0-CS7/RAS0/RAS7

IOWR

IORD

REFRQ

BCYST

WE

RD

OE

UWR/UCAS

LWR/LCAS

WAIT

A0-A 23

D0- D15

DMARQ0-DMARQ3

DMAAK0-DMAAK3

TC0 - TC3

CKSEL

CLKOUT

X1

X2

CVDD

CVSS

MODE0-MODE3

RESET

VDD

VSS

DRAMC

DRAMC

BCU

DAMC

PAGEROM

CONTROLLER

Multiplexer

CommandKey

SystemRegister

GeneralRegister

Port

SystemController

A0-A23 : Address Bus

ADTRG : A/D Trigger Input

ANI0-ANI7 : Analog Input

AVDD : Analog Power Supply

AVREF : Analog Reference Voltage

AVSS : Analog Ground

BCYST : Bus Cycle Start Timing

CKSEL : Clock Generator Operating Mode Select

CLKOUT : Clock Output

CS0-CS7 : Chip Select

CVDD : Clock Generator Power Supply

CVSS : Clock Generator Ground

D0-D15 : Data Bus

DMAAK0-DMAAK3 : DMA Acknowledge

DMARQ0-DMARQ3 : DMA Request

HLDAK : Hold Acknowledge

HLDRQ : Hold Request

HVDD : Power Supply for External Pins

INTP100-INTP103, : Interrupt Request from Peripherals

INTP110-INTP113,

INTP120-INTP123,

INTP130-INTP133,

INTP140-INTP143,

INTP150-INTP153

IORD : I/O Read Strobe

IOWR : I/O Write Strobe

LCAS : Lower Column Address Strobe

LWR : Lower Write Strobe

MODE0-MODE3 : Mode

NMI : Non-Maskable Interrupt Request

OE : Output Enable

P00-P07 : Port 0

P10-P17 : Port 1

P20-P27 : Port 2

P30-P37 : Port 3

P40-P47 : Port 4

P50-P57 : Port 5

P60-P67 : Port 6

P70-P77 : Port 7

P80-P87 : Port 8

P90-P97 : Port 9

P100-P107 : Port 10

P110-P117 : Port 11

P120-P127 : Port 12

PA0-PA7 : Port A

PB0-PB7 : Port B

PX5-PX7 : Port X

RAS0-RAS7 : Row Address Strobe

RD : Read Strobe

REFRQ : Refresh Request

RESET : Reset

RXD0, RXD1 : Receive Data

SCK0-SCK3 : Serial Clock

SI0-SI3 : Serial Input

SO0-SO3 : Serial Output

TC0-TC3 : Terminal Count Signal

TCLR10-TCLR15 : Timer Clear

TI10-TI15 : Timer Input

TO100, TO101, : Timer Output

TO110, TO111,

TO120, TO121,

TO130, TO131,

TO140, TO141,

TO150, TO151

TXD0, TXD1 : Transmit Data

UCAS : Upper Column Address Strobe

UWR : Upper Write Strobe

VDD : Power Supply for Internal Unit

VSS : Ground

WAIT : Wait

WE : Write Enable

X1, X2 : Crystal

69

• Pin Description

Pin Assignment

70

Pin no. Pin name I/O I/O Setting Symbol Description

1 P07 I/O I SFG SFG interruption demand

2 P06 I/O I INT1 DSP interruption demand (RAM CTL/SRV system)

3 P05 I/O I INT2 DSP interruption demand (ATAPI system)

4 P04 I/O I INT0 DSP interruption demand (DSP)

5 P03 I/O O FM_SW Front monitor signal substitution

6 P02 I/O O Blank port


8 P00 I/O O AMUTE Audio Mute signal

9 Vss O VSS GND

10 P17 I/O I EJECTSW EJECTSW interruption demand

11 P16 I/O I FOK FOK interruption demand

12 P15 I/O I RECD1 R Media system Non-recorded detection



15 P12 I/O I HEATRUN Off line heat run test setup Input

16 P11 I/O I CSEL ATAPI CSEL

17 P10 I/O I CSW1 Cartridge detection signal (extraction history)

18 P107 I/O I CSW2 Cartridge detection signal (protection)

19 P106 I/O I CSW3 Cartridge detection signal (Cartridge detection)



22 P103 I/O I LIMIT Slider Inner circumference Limit SW input




26 P77 I DRVTEMP Driver thermal signal

27 P76 I PWWMON W-APC front monitor

28 P75 I PWRMON R-APC front monitor

29 P74 I TEMP Temperature sensor

30 P73 I SIMG_AFE RF envelope

31 P72 I TACTM Tracking Driver output Moniter(- side)

32 P71 I BCENT BCENT/BHOUT/APCGCAOUT

33 P70 I TACTP Tracking Driver output Moniter(+side)

34 AVdd I AVDD A+3.3V(A/D power supply)

35 AVss O AVSS GND (Grounding for A/D)

36 AVref I AVREF A+3.3V(A/D reference voltage input)

37 P20 I XNMI WakeUp Interruption signal

38 P21 I/O O FANEN Control of FAN for cooling

39 P22 I/O O SO0 Serial data output

40 P23 I/O I SI0 Serial data input

71


41 P24 I/O O XSCK0 Serial clock output




45 Vdd I VDD +3.3V

46 P37 I/O I LDIN Loader in sensor

47 P36 I/O I LDOUT Loader out sensor

48 P35 I/O O DRVTMUTEB Tilt Driver Control

49 P34 I/O I Blank port









57 P114 I/O O DRV12 For 12cm Spindle Driver sensitivity change

58 P113 I/O O DRV8 For 8cm Spindle Driver sensitivity change




62 CVdd I CVDD A+3.3V(The power supply for Clock circuits)

63 X2 O X2 Oscillation element input terminal

64 X1 I X1 Oscillation element output terminal

65 CVss O CVSS GND ( Grounding for Clock circuits)

66 CKsel I CKSEL GND ( Clock PLL/Direct Mode Change)

67 MODE0 I MODE0 Vdd (CPU Data-BusWidth selection terminal)

68 MODE1 I MODE1 Vdd (CPU Data-BusWidth selection terminal)

69 MODE2 I MODE2 GND

70 MODE3 I MODE3 GND (FROM rewriting voltage input terminal)

71 XRESET I XRESET Power On Reset signal input terminal

72 P127 I/O I ADGATE DSP AD translation demand signal (RF system)

73 P126 I/O O DRVCTR1 6ch Driver Control

74 P125 I/O O DRVCTR2 6ch Driver Control

75 P124 I/O O STNBYB DSP Wakeup/Standby change control

76 P123 I/O O MRSTB AFE/PLL/DSP LSI Reset signal

77 P122 I/O O SLEEPHD LDD Sleep control

78 P121 I/O O STNBYON NMI Mask/Mask release for WakeUp Control

72



80 PX7 I/O O (CLKOUT) For Bus evaluation

81 PX6 I/O O Blank port

82 PX5 I/O O Blank port

83 Vss O VSS GND

84 P97 I/O O EEPRCE EEPROM Chip Select


86 P95 I/O O DSLADJ2 DSL Adjustment/EQ Boost Filter change single

87 P94 I/O O (XBCYST) For Bus evaluation

88 P93 I/O O DSLADJ Encoder output Loop Back Mute signal

89 P92 I/O O XRD Read Strobe


91 P90 I/O O XLWR Lower Byte Write Strobe

92 P87 I/O O XCS7 DSP3 Chip Select(1Wait)

93 P86 I/O O XCS6 DSP3 Chip Select(2Wait)



96 P83 I/O O LEDG1 LED

97 P82 I/O O XCS2 SRAM Chip Select

98 P81 I/O O XCS1 FROM Chip Select(Main Part)

99 P80 I/O O XCS0 FROM Chip Select(Core Part)

100 HVdd I VDD +3.3V




104 P64 I/O O A20 Address Bus 20





109 PB7 I/O O A15 Address Bus 15








117 Vss O VSS GND

118 PA7 I/O O A7 Address Bus 7



73







126 HVdd I VDD +3.3V

127 P57 I/O O D15 Data Bus 15








135 Vss O VSS GND









144 Vdd I VDD +3.3V

TROUBLESHOOTING GUIDE

74

MPUIC801

MPUIC801

MPUIC801

MPUIC801

MPUIC801

DSPIC701

DSPIC701

DSPIC701

AFEIC101

IC107IC108

AFEIC101

Pickup

Pickup

LDDriver

FrontMonitor

IC103IC104IC105

AFEIC101

DSPIC701

#10

Pin#86,88

Pin#77

Pin#86-98

#31

#33

DriverIC601

#47

#49

C131 Pin#65

#14

#16

FFC

FFC45-49

FFC

FFC

FFC

Pickup

Pickup

FFC

Setting

Setting

Setting

Setting Setting

FE:R701,C703

Pin#27pin#28

LDDriver

FE:R706,C708

FE:R702,C704

TACT-:

TACT+:

ADJUST BLOCK DIAGRAM

(01) Laser Power Adjust (using RD Power/WR Power/Erase Power)

(02) High Frequency Adjust

(03) Data Slice/Equalizer Boost/Raw Slice/ Equalizer Frequency Adjust

(04) Circuit Offset Adjust

(05) Tracking Driver Offset Adjust

75

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

DVD-Dual Disc

Pin#86-98

FFC

Setting

(Signal Amp)

Setting

FE:R701,R740

Focus:#45-46

Slider FPCSlider:#34-37

C703

R625,C628 #53

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

All Disc

All Disc

Pin#86-98

FFC

Setting Setting

FE:R706,R741

Tracking#47-48


C708

R624,C627 #52

MPUIC801

DSPIC701

AFEIC101

DriverIC601

IC602IC508

Pickup

All Disc

Pin#99-100

FFC

Setting Setting

LPSA:R707,C709

#47,48

LPSB:R708,C710

R624,C627

#52

#33

MPUIC801

DSPIC701

AFEIC101

DriverIC601

PickupPin#86-98

#3

#3

#4

#5

#1,2

FFC

Setting Setting

FE:R701,R740

PE:R702,C704Focus:#45-46

C703

R625,C628 #53

(06) Focus Amp. Adjust for DVD-Dual

(07) Focus Amp. and Total Amp. Adjust

(08) Tracking Amp. Adjust

(09) Lens DAC/Lens Position Adjust

76

All Disc

MPUIC801

DSPIC701

AFEIC101

DriverIC601

PickupPin#

86-98

#3

#5

FFC

Setting Setting

FE:R701,R740

TE:R706,R741C708

Focus:#45-46Tracking:#47-48


C703

R624, C627 #52

R625, C628 #53

DVD-RAM Disc

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

Pin#78-79

#30

#72 #133

#27-28#8

FFC

Setting Setting

SIGMON:R836, C812Slider FPC

Slider:#34-37

DVD-ROM Disc

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

Pin#86-98,78-79

(PI/C1) #3

FFC

Setting Setting

FE:R701,R740C703


DVD-RAM Disc

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

Pin#86-98,78-79

(PID Amp) #8

FFC

Setting Setting

SF:R703,C705


(10) Servo Loop Gain Adjust

(11) Unwritten Slice Level Adjust for DVD-RAM

(12) Focus Offset Adjust for DVD-ROM, CD-R/RW

(13) Focus Offset Adjust for DVD-RAM (PID Amp)

77

MPUIC801

DSPIC701

AFEIC101

DriverIC601

Pickup

DVD-RAM DiscPin#86-98,78-79

FFC

Setting

(PI Error)

Setting

C727,728


#68,69

MPUIC801

DSPIC701

AFEIC101

DriverIC601

PickupDVD-RAM DiscPin#

86-98,78-79

FFC

Setting

(Signal Level)

Setting

TCPH:R709,C711



TIE:R704,C706

#10

#11

MPUIC801 DSP

IC701

AFEIC101

DriverIC602IC603

DriverIC601

Pickup

DVD-R/RW DiscPin#86-98,78-79

Pin#86-98,78-79

FFC

Setting

(Tracking Amp)

Setting

TE:R706,R741C708

TE:R624,C627

Tilt:IC602#6-7

#52

Pin#15,18,1

TILT#41

#5

TE:#47-48

MPUIC801

DSPIC701

AFEIC101

DriverIC601

PickupDVD-R/RW Disc

FFC

Setting

(Focus Offset)

Setting

FE:R701,R740

FE:#45-46

C703

FER625, C628 #53

#5

#11

(14) Focus Offset Adjust for DVD-RAM (Data Error Pulse)

(16) Tilt Adjust for DVD-R/RW, DVD+R/RW, CD-R/RW

(17) Focus Deviation Adjust

(15) Tilt Adjust for DVD-RAM

78

Pin#86-98,78-79MPU

IC801

MPUIC801

MPUIC801

DSPIC701

AFEIC101

DSPIC701

DriverIC601

DriverIC601

Pickup

Pickup

DVD-R/RW Disc

FFC

FFC

FFC

Setting

Setting

Setting

(Tracking Amp)

(Driver Offset)

Setting

TE:R706,R741

TE:#47-48


C708

TE:R624, C627

(Temp.Information)

#52

#29

#41

#5

Spindle

SPD:R610,C606

#20 #24 Pin#9,11,18

Pin#1-6

#21#17 FG

Pin#86-98,78-79MPU

IC801 DSPIC701

AFEIC101

DriverIC601

Pickup

DVD+R Disc

FFC

Setting

(ADIP Count)

Setting

WobSIG


#94 #47 #47

Pin#86-98,78-79MPU

IC801 DSPIC701

AFEIC101

DriverIC601

Pickup

DVD-R/RW Disc

FFC

Setting

(DID Count)

Setting

C727,728


#68,69

#49

(18) Focus Offset Adjust for DVD-R/RW, DVD+R/RW, CD-R/RW

(19) Lens Sensitivity Adjust

(20) Spindle Offset Adjust

(21) ADIP BPF/Read Timing Adjust for DVD+R/RW

(22) Focus Offset Adjust for DVD-R/RW, DVD+R/RW(DID)

79

MPUIC801

DSPIC701

DriverIC602

DriverIC601

Slider/Spindle

Spindle FFC

Setting Setting


#2,13

#28-29

R630,R635

#22

Pin#86-98MPU

IC801 DSPIC701

AFEIC101

DriverIC601

Pickup

All Disc

FFC

Setting Setting

FE:R701,R740

Focus:#47-46Tracking:#47-48


C703

TE:R706,R741C708

PE:R706,C704

R625,C628

R524,C627

#53

#5

#4

#3

#52

(23) RTZ TimeOut Fail

(24) Focus Servo/Tracking Servo Fail

80

No. Error Code Contents of fail Fail Analysis Block DiagramSSB Byte8,9

1 28xx LP Adjust NG. 1) Check Pickup FFC Connection. No.012) Check solder of IC101circumference.

(pin#10, 14, 16, L101, L103) 3) Check solder of IC103,IC104,IC105.4) Exchange Pickup(LDD, Front Monitor). 5) Exchange IC101(AFE).6) Exchange IC801(MPU).7) Exchange IC701(DSP).

2 48xx High Frequency Adjust NG. 1) Check Pickup FFC Connection. No.022) Exchange Pickup (LDD part).3) Exchange IC701(DSP).

3 4C0x to 4C4x Data Slice Adjust NG. 1) Check solder of IC101circumference. No.03(pin# 77, IC107, IC108, L101, L103)

2) Exchange IC101(AFE).3) Exchange IC701(DSP).

4 4C5x to 4C7x EQ Boost Adjust NG. 1) Check solder of IC101circumference. (pin# 77, IC107, IC108, L101, L103)


5 4C80 RAW Slice Level Adjust NG. 1) Check solder of IC101circumference. (pin# 77, IC107, IC108, L101, L103)


6 4CAx EQ Auto Frequency Adjust NG. 1) Check solder of IC101circumference. (pin# 77, 65, IC107, IC108, L101, L103)

2) Exchange IC101(AFE).

Detail Error Code & Fail Analysis

1. Laser Power Initial Adjust

(Exchangelow/high byte)

Byte8: xxhByte9: 28h

81


1 42xx Circuit Offset Adjust NG. 1) Check Pickup FFC Connection. No.042) Check solder of IC101circumference .

(pin#3,4,5 pin#86-98, FE_Servo: R701, R740, C703 TE_Servo: R706, R741, C708 PE_Servo: R702, C704)

3) Exchange IC101(AFE).4) Exchange Pickup.5) Exchange IC701(DSP).

2 43xx Tracking Driver Offset Adjst NG. 1) Check solder of IC601circumference. No.05 (pin#47-48. R621, R744, R745,R833, R835, C809, C810)

2) Check solder of IC801circumference.(pin#26-36)

3) Check Pickup FFC Connection.4) Exchange IC601(Driver).5) Exchange IC801(MPU).

3 452x Focus Amp Adjust NG. 1) Check DVD-Dual Disc. No.06(DVD-DL Only) 2) Check Pickup FCC Connection.

3) Check solder of IC101circumference.(pin#3,4,5 pin#86-98, FE_Servo: R701, R740, C703)

4) Check Slider FPC Connection.5) Exchange IC101(AFE).6) Exchange IC601(Driver).7) Exchange IC701(DSP).

4 450x Focus Amp Adjust NG. 1) Check Pickup FFC Connection. No.07451x Total Amp Adjust NG. 2) Check solder of IC101circumference.454x (pin#3,4,5 pin#86-98,

FE_Servo: R701, R740, C703 PE_Servo: R702, C704)

3) Exchange Pickup.4) Exchange IC101(AFE).5) Exchange IC701(DSP).

5 458x Tracking Amp Adjust NG. 1) Check Pickup FFC Connection. No.082) Exchange Pickup.3) Check solder of IC101circumference.

(pin#3,4,5 pin#86-98, TE_Servo: R706, R741, C708)


6 45Ax Lens DAC Adjust NG. 1) Check Pickup FFC Connection. No.092) Exchange Pickup.3) Check solder of IC101circumference.


4) Check solder of IC701circumference. (R707,R708,C709,C710)

5) Exchange IC508.6) Exchange IC602.7) Exchange IC101(AFE).8) Exchange IC701(DSP).

2. Adjusting Error during Disc Load Sequence (Lead in Error)

82


7 46xx Lens Position Adjust NG. 1) Check Pickup FFC Connection. No.092) Exchange Pickup.3) Check solder of IC101circumference.


4) Check solder of IC701circumference. (R707,R708,C709,C710)

5) Exchange IC508.6) Exchange IC602.7) Exchange IC101(AFE).8) Exchange IC701(DSP).

8 47xx Servo Loop Gain Adjust NG. 47XA: Disc Unmatch(Exchange Disc). No.101) Check Pickup FFC Connection.2) Exchange Pickup (Signal Noisy).3) Check solder of IC101circumference.

(pin#3,4,5 pin#86-98, FE_Servo: R701, R740, C703TE_Servo: R706, R741, C708)

4) Exchange IC101(AFE).5) Exchange IC701(DSP).6) Exchange IC601(Driver).

9 49xx Unwritten Slice Level Adjust NG. 4906: RAM Disc NG (Exchange Disc). N0.11£¤RAM Only£' 4902: IC801-pin#72,IC701-pin#133.

1) Check solder of IC101circumference.(pin#3,4,5 pin#86-98)

2) Exchange IC101(AFE).3) Exchange IC801(MPU).4) Exchange IC701(DSP).

10 4Axx Focus Offset Adjust NG. 4A08: Disc Unmatch(Exchange Disc). No.12(DVD-ROM,CD-R/RW) 1) Check Pickup FFC Connection.

2) Exchange Pickup.3) Exchange IC701(DSP).

11 4A5x Focus Offset Adjust NG. 1) RAM Disc NG (Exchange RAM Disc) No.134A6x £¤RAM Only for PID£' 2) Exchange Pickup

3) Exchange IC101(AFE)4) Exchange IC701(DSP)

12 4A8x Focus Offset Adjust NG. 4A88: RAM Disc NG (Exchange RAM Disc). No.14£¤RAM Only for Data£' 1) Exchange Pickup.

2) Exchange IC101(AFE).

13 4B0x Tilt Adjust NG(RAM Only). 1) Check Pickup FFC Connection. No.152) Exchange Pickup.3) Check solder of IC101circumference.

(pin#10,11 R709,C711,R704,C706)4) Exchange IC101(AFE).5) Exchange IC701(DSP).

14 4B8x Tilt Adjust NG(DVD-/+ R/RW). 1) Check Pickup FFC Connection. No.162) Exchange Pickup.3) Check solder of IC602 and IC603_

circumference.4) Exchange IC602 or IC603.5) Check solder of IC701 circumference.6) Exchange IC7017) 7) Exchange Slider Motor.

83


15 4Cxx Data Slice Adjust NG. 4C88/4C89: RAM Disc NG No.14 (RAM Only) (Excahnge RAM Disc).

2) Exchange Pickup.3) Exchange IC101(AFE).4) Exchange IC701(DSP).

16 4Dxx Focus Deviation Adjust NG. 1) Check Pickup FFC Connection. No.172) Exchange Pickup.3) Check solder of IC701circumference.4) Exchange IC701(AFE).

17 182x Home Position Adjust NG. 1) Check FFC Connection. No.2301xx (DVD-SL Only) 2) Check Slider FPC Connection.

3) Exchange Slider Motor.4) Check solder of IC101circumference.5) Exchange IC101(AFE).

18 51xx Focus Balance Adust NG. 1) Check Pickup FFC Connection. No.07(DVD-SL Only) 2) Exchange Pickup.

3) Check solder of IC101circumference.(pin#3,4,5 pin#86-98, FE_Servo: R701, R740, C703)


19 52xx Focus Offset Adjust NG. 1) Check Pickup FFC Connection. No.18(DVD-R/RW, +R/RW) 2) Exchange Pickup.

3) Check solder of IC101circumference.(pin#3,4,5 pin#86-98, TE_Servo: R706, R741, C708)

4) Exchange IC101.

20 54xx DPP Amp Adjust NG. 1) Check Pickup FFC Connection. No.08(CD Disc Only) 2) Exchange Pickup.

3) Check solder of IC101circumference.(pin#3,4,5 pin#86-98, TE_Servo: R706, R741, C708)


21 55xx Lens Shift/ Tilt Adjust NG. 1) Check Pickup FFC Connection. No.16(CD Disc Only) 2) Exchange Pickup.

3) Check solder of IC602 and IC603 circumference.

4) Exchange IC602 or IC603.5) Check solder of IC701 circumference.6) Exchange IC701.

22 56xx Focus Level Adjust NG. 1) Check Pickup FFC Connection. No.072) Exchange Pickup.3) Check solder of IC101circumference.

(pin#3,4,5 pin#86-98,PE_Servo: R702, C704)


84


23 57xx HFPE Amp/Gain Adjust NG. 1) Check Pickup FFC Connection. No.152) Exchange Pickup.3) Check solder of IC101circumference.

(pin#10,11 R709,C711,R704,C706)4) Exchange IC101(AFE).5) Exchange IC701(DSP).

24 58xx Lens Sensitivity Adjust NG. 1) Check Pickup FFC Connection. No.192) Exchange Pickup.3) Check solder of IC801circumference.4) Exchange IC801(MPU).

25 59xx Spindle Offset Adjust NG. 1) Check Spindle FFC Connection. No.202) Check solder of IC601circumference.

(pin#34-37)3) Exchange IC601(Driver).4) Exchange Spindle Motor.5) Check solder of IC701circumference.6) Exchange IC701(DSP).

26 5Axx ADIP read timing Adjust NG. 5A01: Check DVD+R Disc (Exchange Disc) . No.211) Check Pickup FFC Connection.2) Exchange Pickup.3) Exchange IC101(AFE).4) Exchange IC701(DSP).

27 5Bxx Tracking reverses Adjust NG. 1) Check Pickup FFC Connection. No.072) Exchange Pickup.3) Check solder of IC701circumference.



28 5Cxx Signal Amp Error. 1) Check Pickup FFC Connection. No.072) Exchange Pickup.3) Check solder of IC701circumference.



29 5Dxx Focus Offset Adjust NG. 1) Check Pickup FFC Connection. No.22(DVD-R/RW,+R/RW in Data) 2) Exchange Pickup.

3) Check solder of IC101circumference.4) Exchange IC101.5) Check solder of IC701circumference.6) Exchange IC701.7) Exchange Slider Moter.

85


1 2503,2504 RTZ Timeout(Sled Timeout). 1) Check Slider FPC Connection. No.232) Check solder of IC601 circumference .

(pin#28-29, 34-37)3) Check solder of IC602 circumference.

(pin#2,13 R630, R635, C618, C619)4) Exchange Slider Motor.

2 2020,2021 Focus Fail. 1) Check Pickup FFC Connection. No.242) Exchange Pickup. 3) Check solder of IC601circumference.4) Exchange IC601(Driver) 5) Check solder of IC101circumference.

(pin#3,4,5 pin#86-98, FE_Servo: R701, R740, C703)


3 2101,2102 Tracking Fail. 1) Check Pickup FFC Connection. No.242) Exchange Pickup. 3) Check solder of IC601circumference.4) Exchange IC601(Driver). 5) Check solder of IC101circumference.

(pin#3,4,5 pin#86-98, TE_Servo: R706, R741, C708).


4 2000~2010 Spindle Fail. 1) Check Spindle FFC Connection. No.202) Check solder of IC601circumference.

(pin#34-37)3) Exchange IC601(Driver).4) Exchange Spindle Motor.5) Check solder of IC701circumference.6) Exchange IC701(DSP).

3. Loading Sequence Error (Lead in Error)

86

Line-in : 12V TH501SW_reg

IC501

Line-in : 5V TH502IC504

3.3V Reg.

12P

HD62604_3.3V_analog

6ch_DRIVE(SPDL,SLED,LOAD)_VM_12V

IC5051.5V Reg.

HD153721_VCC_5.0V analog

pick_up VSO_4.2V (PDD)

pick_up VSA_5.0V (LDO)

AUDIO_amp_5.0V

OP-amp_5.0V(APC)

P_RESET(IC506) R separation

Tilt_DRIVE_VM_5V

P_RESET R spearation

HD62604_3.3V_digital_IO

HD153721_3.3V_IO

pick_up VSL_3.3V

MPU_V850_3.3V_digital

6ch_SRV_DAC_3.3V_analog

SD-RAM_3.3V_VDD

S-RAM_3.3V_VDD

FL-ROM_3.3V_VDD

EEP-ROM_3.3V_VDD

HD62604_1.5V_digital(core)

5AREG

MPU_V850_3.3V_analog

6ch_DRIVE(Fo,Tr)_VM_5V & DVcc

HD153721_3.3V_srvref

L502

L501

*SW

OP-amp_5.0V(Vref)

L103

*SW

HD153721_VCC4_5.0V digitalL101

L104

pick_up AVCC_5.0V(OEIC)

L102

STANBYON

R513

5P

3.3D

0

L506Tr_SW

L702 3.3D_L

L801 3.3D

L701 3.3A_L

L802 3.3A

L601 3.3A

L703

Power Supply System Diagram

87

No Circuit/IC Signal Signal/Level mesurement-point (IC-pin or Device)

1 Power supply Line-12V 12V PG901-56

2 Line-5V 5V PG901-53

3 (IC501) reg-5.0V 5V L502

4 (IC504) reg-3.3V 3.3V 3

5 (IC505) reg-1.5V 1.5V 5

6 MPU VDD : 3.3V 3.3V 45, 62, 100, 126, 144

7 (IC801) Clock-5MHz 5.0MHz 63, 64

8 PSRST 3.3V(High) 71

9 NMI 3.3V(High) 37

10 Flash-ROM VDD : 3.3V 3.3V 37

11 (IC802) CS Active-Low 26

12 XRD read-CK 28

13 S-RAM VDD : 3.3V 3.3V 8

14 (IC803) CS Active-Low 30

15 SD-RAM VDD : 3.3V 3.3V 1, 7, 13, 25, 38, 44

16 (IC702)

17 DSP VDD : 1.5V 1.5V 11, 90, 161, 188, 227

18 (IC701) VCC(D) : 3.3V 3.3V 5, 81, 101, 151, 165, 174, 183, 199, 217, 230, 240, 250

19 VCC(A) : 3.3V 3.3V 46, 61, 77

20 Clock-34MHz 33.8688MHz 126, 127

21 MRSTB (3.3V)High 130 (MPU-76)

22 STANBYB (3.3V)High 131 (MPU-75)

23 AFE VCC : 5V 5V 12, 27, 54, 72

24 (IC101)

25 OP-amp VCC : 5V 5V 4

26 (IC508) VC165 1.65V 8

27 VC25 2.5V 1

28 VC21 2.1V 7

29 SRV-DAC VCC : 5V 5V 8

30 (IC602) VDD : 3.3V 3.3V 7

31 RESET (3.3V)High 4

32 6ch-DRV DVCC : 5V 5V 54

33 (IC601) VCC : 12V 12V 51

34 VC : 1.65V 1.65V 27

35 Tilt-DRV VCC : 5V 5V 8

36 (IC603) VC : 1.65V 1.65V 2

37 STBY (GND) Low 1 (Low: on / High:off)

38 EEP-ROM VCC : 3.3V 3.3V 8

39 (IC804) Pull-up 3.3V 3, 7

40 Pick-up AVCC : 5V 5V 8

41 VC21 2.1V 13

42 VC165 1.65V 28

43 VC25 2.5V 32

44 VSL33 : 3.3V 3.3V 40

45 VSA5 : 5V 5V 41

46 VSO : 5V 5V 42

* When there are twe or more power supply pins of LSI, first of all, it checks by random one pin.

PCB Poor Analysis - Check list

88

1. Self-Diagnostic Function by LED Blink.

• Basic operation: MPU accesses each peripheral (inside, exterior) device, and discover a defect by theability of a read/write of data to be performed correctly. Since MPU operates by the program with a built-inFlash-ROM, when abnormalities are in MPU, Flash-ROM, and these Data-Bus & control signals, this self-diagnostic function cannot be used. In such a case, the case where LED does not light up at all at the timeof a power supply injection is almost the case.

• MPU: DSP, S-RAM (1Mb), and Flash-ROM (16Mb) are connected to the exterior Bus of MPU. Even if theMPU-Bus terminal of DSP short-circuits, it is sufficient and the Bus terminal of S-RAM short-circuits, itbecomes impossible for MPU to read the right program data from Flash-ROM, and stops for this reason,turning on LED at all. On the other hand, like S-RAM, the own poor device of DSP, and the open state of IC-pin, when [poor] not influencing Bas of MPU, it can detect correctly and becomes blink of LED according tothose defects.

• DSP: DSP has MPU-IF, SD-RAM-IF, ATAPI-IF, LDD-serial-IF, AFE-serial-IF, and an AFE control signal asDigital-IF. As Analog-IF, it has the slice circuit of RF signal from AFE, PLL, the objects ADC and DAC forSERVO, and ADC for ADIP detection. Among these, own poor Digital of DSP, MPU-IF, SD-RAM-IF, andAFE-serial-IF can detect by this self-diagnostic function.

• AFE: Poor detection of AFE is restricted to detection of a limitation-item. Since the greater part of thefunction is analog signal processing, AFE serves as a register in AFE, and a check, which accepts it, serialIF in the logical digital examination from MPU. In addition, serial-IF for AFE control is performed via DSP.This is writing in the Write command and setting data, and is automatically transmitted to the predeterminedregister of DSP. Conversely, when it leads the register information on AFE, the read command can bewritten in the predetermined register of DSP, and the value of an AFE register can be read by reading theread register of DSP after that. Therefore, serial [between the poor register of AFE, and AFE and DSP],when there is LED blink with poor AFE — the defect of IF or the defect of the register for AFE of DSP isconsidered.

• SD-RAM: SD-RAM is not connected with direct MPU-Bus. SD-RAM is connected with DSP. Therefore,when the SD-RAM itself is poor, and abnormalities are in Bus and the control signal between DSP and SD-RAM, SD-RAM is detected as NG.

• EEP-ROM: If EEP-ROM diagnosis reads address 7FF, will be 5A Written in and will read it, if 5A is written, itis not OK, and it is not written, and 5A can be read, it OKs, and if it cannot read, it will be judged to be NG(LED blink). Although Correspondence FW is after L038, in the state mounted since the early stages FW ofFlash-ROM were L02B, it cannot perform poor detection of EEP-ROM. Poor detection of EEP-ROM isattained by D/L [FW].

• Refer to the contrast table of the number of times of blink of LED, and a poor part.

• The self-diagnostic function by this LED blink is carried out in the state of a set without a PCB independentor loading Disc.

HW Self- Diagnostic function

89

2. LED does not blink at all at the time of a power supply injection. Eject-SW does not react.(1) Is it normal to the exterior Bus (Data-Bus, Address-Bus, control signal system) of MPU?

Viewing — check: -- a short circuit, opening, etc.

• The device connected to the exterior Bus of MPU, and its signal list

=> It repairs, when abnormalities are discovered.

(2) Does the power supply circuit operate normally?When the abnormalities in external input 12V, 5V, regulator 5V, regulator 3.3V, and regulator 1.5V => arediscovered, an external power supply, a power supply cable, and Regulator IC are exchanged. Since aproblem is in a load side when not improving, even if it carries out the => above mentioned exchange, a JR2power-supply system figure is made reference, and poor portions, such as a short circuit of a power supplypart, are found out and repaired.

(3) Is the clock of MPU oscillated correctly?Checked the ceramic oscillation element’s X801 both-ends and MPU (63), (64) 5MHz oscillating. When 3.3Vpower supply is correctly supplied to =>MPU and the clock is not oscillating correctly, it is the defect of MPU,or an oscillation element defect, and part exchange is performed in order of MPU and X801.

(4) The defect of Flash-ROMAlthough the clock of MPU is oscillating correctly and the power supply circuit is also outputting normalvoltage, when LED does not blink at all at the time of a power supply injection and Eject-SW does not react,either, poor Flash-ROM is the most doubtful.=> Flash-ROM (IC802) are exchanged.

Note: Before Flash-ROM exchange, all CS signals of the external device of MPU connection, an Addresssignal, and a Data signal are observed on a waveform level, and since the but most amount of work and thespecial knowledge which can raise the discovery accuracy of a poor part are necessities, recommendationis impossible.

(5) Even if it performs the above-mentioned repair, when not improving, the disconnection and the short circuit,which cannot be discovered, can be considered in viewing of PCB. Moreover, partial breakage (although aclock is oscillated, somewhere in insides do not operate.) of MPU can be considered. In this case, theexternal device connected after [of MPU / MPU] exchange is exchanged in order. When not improving by =>above, the possibility that a PCB pattern is faulty is high, and judges repair to be difficult.

Peripheral device Flash -ROM S-RAM DSP

[Bus/Signal] (IC802) (IC803) (IC701)

Address A1~A20 A0~A15 A0~A10

Data D0~D15 D0~D7 D0~D7

CS* XCS0&XCS1 XCS2 XCS6 & XCS7

WCK XWRL XWRL XWRL

RCK XRD XRD XRD

90

3. Motor, Abnormalities in Actuator SystemThe drive circuit of a motor & actuator consists of the three ICs IC601 (BD7905BFS), IC603 (BA5962FVM)and IC602 (BU2507FV). The work of each IC is as follows.

(1) IC601(BD7905BFS) : 6ch driverSpindle motor driver: 180 degree electronically Type, an analog input, a PWM drive, a Vm=12V.Stepping motor driver X2: analog input, a PWM drive (differential), a Vm=12V Loading motor driver: analog input / output (differential), a Vm=12VFocus actuator driver: analog input / output (differential), a Vm=5V Tracking actuator driver: analog input / output (differential), Vm=5V

A motor & actuator and its correspondence pin

A control mode setup by the control terminal

(2) IC603(BA5962FVM) : 1ch-BTL DriverActuator driver: An analog input / output (differential), Vm=5VInput : (3)IN1, Reference , (2)BIAS 1.65V , Output : (7)OUT+ (6)OUT- (1)STNBY : Low=on / High=off

(3) IC602(BU2507FV) : 6ch-10bit -The DA converterThe serial data supplied from DSP is received and DA output of 6ch is performed.CH1 : (13)AO1 Stepping motor control signal 1CH2 : (2)AO2 Stepping motor control signal 2CH3 : (3)AO3 Actuator control signalCH4 : (5)AO4 Loading motor control signalCH5 : (6)AO5 Reference signal (voltage)CH6 : (9)AO6 Lens position sensor current standard voltage

In addition, the output dynamic range of this DA converter is 0V-3.3V.

Signal/CH SPDL-MT STEP-MT Load-MT Focus-ACT Track-ACT

Input (24)SPIN (28)SLIN1 (26)LDIN (53)FCIN (52)TKIN

(29)SLIN2

Reference (27)VC 1.65V (27)VC 1.65V (27)VC 1.65V (27)VC 1.65V (27)VC 1.65V

Output (9)U (37)SLO1+ (50)LDO+ (46)FCO+ (48)TKO+

(11)V (36)SLO1- (49)LDO- (45)FCO- (47)TKO-

(18)W (35)SLO2+

(34)SLO2-

CTL1(22) CTL2(23) SPDL SLED Focus Track Load

Low Low off off off off off

High Low off off off off on

- High on on on on off

92

12VGND5V

Deviceconfiguration

jumperMASTERSLAVECSEL

Host IDE

HeadphonesJack

Analog

audio

LED

BUFFER RAM (2MByte)

K4S1616220 or Equivalent(SAMSUNG)

Disc

RST ICBD4838FVE-TR

(RHOM)

Loadingmotor

Slidemotor

Discmotor

Unitmechanism

Tray DetectSW

EjectSW

LimitSW

MicroprocessorV850E/MSI 96KB-ROM

PD703100(NEC)

3.3V Reg. ICPQ33DZ01ZP

(SHARP)

Front End LSI

HD153721TF

100pin-TQFP

(HITACHI)

Tilt Act. Driver

BA5962FVM

(RHOM)

SRAM (1Mbit)

PD441000LGUor Equivalent

EEPROM (4kB)AT25320

or Equivalent

Flash-ROM (2MByte)

MBM29LV160BEor Equivalent

1.5V Reg. ICPQ1X151M2ZP

(SHARP)

5.9V SW_Reg.ICPQ01CZ41H2ZP

(SHARP)

OPU:HOP-8511T(HITACH ME)

InterfaceconnectorDVD/CD DSP

(DVD/CD/Servo/ATAPI)HD62604FDV256pin LQFP

(HITACHI)

DVD-codecCD-codec

LPP/ADIP decorderServo DSPATAPI-I F

6ch-DriverBA7902CFS

SPDL/SLED/Fo/Tr/L D

(RHOM)

SRV DAC6ch

BU2507FV(ROHM)

PU

BLOCK DIAGRAM

lg_gsa-4040b

Documents

slider fpc

capacitor

components

nrzi channel

center hole

performing

capacitor

data processing