Visvesvaraya Technological University, Belgaum Project Work II (EC8P2) Report on LINE FOLLOWING ROBOT Submitted in partial fulfillment of the requirement of VIII semester ELECTRONICS & COMMUNICATION Engineering by AMITHASH E. PRASAD (1GA01EC002) Under the guidance of Internal Guide B. N. Manjunatha Reddy Assistant Professor Dept. of E&C, GAT Department of Electronics and Communication Engineering Global Academy of Technology, Bangalore-98 2005
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Visvesvaraya Technological University, Belgaum
Project Work II (EC8P2) Report
on
LINE FOLLOWING ROBOT
Submitted in partial fulfillment of the requirement of VIII semester ELECTRONICS & COMMUNICATION Engineering by
AMITHASH E. PRASAD (1GA01EC002)
Under the guidance of
Internal Guide B. N. Manjunatha Reddy
Assistant Professor
Dept. of E&C, GAT
Department of Electronics and Communication Engineering
Global Academy of Technology, Bangalore-98
2005
GLOBAL ACADEMY OF TECHNOLOGY (National Education Foundation)
Rajarajeshwari Nagar, Ideal Home Township, Off. Mysore Road, Bangalore – 560098.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
CERTIFICATE Certified that the project work entitled LINE FOLLOWING ROBOT carried out by Mr
Amithash E, Prasad USN 1GA01EC002 a bonafide student of 8th Semester in partial
fulfillment for the award of Bachelor of Engineering in Electronics and Communication of
Visvesvaraya Technological University, Belgaum, during the year 2005. It is certified that
the corrections/suggestions indicated for Internal Assessment have been incorporated in the
Report department library. The project report has been approved as it satisfies the academic
requirements in respect of project work prescribed for the said degree.
Signature of the Guide Signature of the HOD Signature of the Principal
(B. N. Manjunatha Reddy) (Prof.N. Narasimha Swamy) (Dr.T.R.Seetharam)
External Viva
Name of the Examiners Signature with date
1.
2.
ACKNOWLEDGEMENT An endeavor over long period can be successful only with advice and guidance of many well
wishers.
My sincere thanks to the management and Dr. T. S. Seetharam, principal, Global Academy
of Technology, for providing me the opportunity to conduct my project work.
I am highly indebted to N.Narasimha Swamy, H.O.D, Electronics & Communication
Department, GAT for his assistance and constant source of encouragement.
I wish to express my profound and deep sense of gratitude to H. S. Manjunatha Reddy,
Assistant professor, Department of Electronics and Communication, Project Co-ordinator, for
sparing his valuable time to extend help in every step of my project work.
I whole heartedly express my thanks to, B. N. Manjunatha Reddy, Assistant Professor,
Electronics & Communication Department, GAT for sparing time to go through every tiny
detail and give his valuable suggestions to make this project and report a success.
I would also like to thank the staff of E& C Dept for their generous guidance.
I’d like to thank Prof. A. J. Menon, Instrumentation department, IISC, Bangalore, for his
valuable support and guidance throughout the project.
Last but not the least we would like to thank our friends and family for their help in every
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LINE FOLLOWING ROBOT
Three speeds are used for the line following robot and their corresponding duty cycles are 0%, 50% & 96%. These calculations are shown below. For 0% duty cycle the value to be loaded is obviously zero, For 50 % duty cycle,
PWM duty cycle = 200μ s10050
× = 100 sμ .
100 μ s = [DCx] •0.25 sμ • 1
DCx = 400 = 110010000b
Thus, clear the bits DCxB1 & DCxB0 and load 1100100b i.e. 100 into the CCPRxL
register.
For 96 % duty cycle,
PWM duty cycle = 200μ s10096
× = 192 sμ .
192 μ s = [DCx] •0.25 sμ • 1
DCx = 768 = 1100000000b
Thus, clear the bits DCxB1 & DCxB0 and load 11000000b i.e. 192 into the CCPRxL
register.
4.1.8. THE IR SENSORS
The MOC7811 consists of an infrared emitting diode (λ = 950nm) and an NPN
silicon phototransistor mounted to face each other on a converging optical axis in a black
plastic housing. The phototransistor responds to radiation from the emitting diode only
when no object is present within its field of view. This sensor is physically modified so
that the emitter and detector face the same direction and thus the modified sensor serves
the purpose of an optical-reflective sensor. The sensor has a focal length of 8mm, thus the
surface must be at an optimum distance of 1.6cm. The original and modified sensors are
shown below.
Figure 4.7: LEFT: Original sensor, RIGHT: modified sensor
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LINE FOLLOWING ROBOT
Figure 4.8: Reflective sensor
If a reflective (white) surface is present at the optimal distance (d = 1.6cm) then
the reflected waves will strike the detector which on radiation will start to conduct. The
circuit diagram is shown in the figure below.
Figure 4.9: The sensor
The drop across the emitter when forward biased is around 1.4V. According to the
data sheets, to have sustained radiation, a max of 40mA must flow through to avoid
damage. A safe margin is allowed and a current of 16mA is considered for the design.
IdVdVccR −
=
for, Vcc = 5V
Vd = 1.4V
Id = 16mA
R is calculated to be approximately 220Ω .
For the emitter, the collector resistor was determined experimentally on a trial and
error basis. It was decided to use a value of 56 Ωk . For this value, the potential across the
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LINE FOLLOWING ROBOT
detector is normally 4.6V, when an object reflects the rays towards the detector, then the
potential drops to 0.6V. The output is obviously analog in nature.
4.1.9. COMPARATOR
A comparator is a circuit which compares a signal voltage applied at one input of
an op-amp with a known reference voltage at the other input, and produces either a high
or a low output voltage, depending on which input is higher. The input / output
characteristics of a comparator is as shown.
Figure 4.10: Comparator transfer characteristics.
The sensor circuit is redrawn using the comparator, and this is shown below.
Figure 4.11: Sensor circuit redrawn with the comparator
The reference voltage is generated by the 20k POT and given to all the
comparators to the non-inverting input. When the respective sensor is on the line, the
emitted light is absorbed by the line and the transistor is the cut-off mode, thus a potential
of 4.6V is given to the inverting input which is greater than Vref (which is chosen to be
2.5V), thus the output of the comparator goes low. When the sensor is not on the line
(reflective white surface) the potential across the detector is usually 0.6V. Thus the output
of the comparator goes high (the non-inverting input has a greater potential). Thus the
output of the comparator goes low only when the sensor is over the line. The comparator
is open collector, and hence a pull-up resistor of 10 Ωk is required at the output.
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LINE FOLLOWING ROBOT
4.1.10. SENSOR ARRAY
7 sensors are totally used. They are in the form shown in the figure below, also
their outputs are also shown. The top view is chosen as it would be easier to infer the
process involved.
Figure 4.12: The sensor array
The sensors are mounted on a separate board along with the biasing resistors and a
2 pin connector supplies the power to the sensor array. And the output of each sensor is
connected to the main board via an 8 pin connector to the comparators on the main board.
4.1.11. THE PRIORITY ENCODER
This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2.
The priority encoding ensures that only the highest order data line is encoded. The
extreme sensors are given to the higher order inputs so that they are given a higher
priority compared to the inner sensors so that no required turn is left out of the priority
process. This is shown in the figure shown below. The truth table is also shown.
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LINE FOLLOWING ROBOT
As can be noticed from the truth table, the 74HC148 is an active low priority
encoder. The chip has an active low enable (EI) input which is always grounded. If the
robot is not on any line, all the input lines will be high, thus the GS line will go high. This
pin is used as the input to the microcontroller for it to decide if it is on a line or not. The
0’th input is always connected to +Vcc = 5V thus allowing the other inputs to generate an
output from 0 to 6. The chip used is 74HC148 which is a high speed CMOS priority
encoder.
Figure 4.13: The priority encoder
4.1.12. THE NO SURFACE LOGIC
Figure 4.14: The no surface logic
Noticing the placement of the sensors A, B & G, it can be noticed that under no
conditions will all of them detect a line (go low). This will only happen when the line is
too thick, or when the robot is lifted off the surface. Only when all the lines go low, will
the NOR gate’s output go high. This line is used by the microcontroller to sense a surface.
The NOR gate used is the 74HCT27 which is a high speed CMOS gate.
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LINE FOLLOWING ROBOT
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4.1.13. MICROCONTROLLER SENSOR INPUTS
Thus totally the microcontroller gets 5 inputs from the sensor circuitry, 3 (A2 – A0)
decide what to do when on the line, The GS output tells whether the robot is on the line or
not, and finally the NO_SURFACE output from the NOR gate tells the microcontroller
whether the robot sees a surface or not. Below is the complete description about what
each input mean and what needs to be done.
NS GS
A2
A1
A0
STATE IN
ACTION
1 X
X
X
X
No surface is detected
Stop the motors
0 1
X
X
X
No line is detected
Execute the no line code (specially designed algorithm)
0 0
0
0
0
A detects the line
Sharp turn left
0
0
0
0
1
B detects the line
Sharp turn right
0
0
0 1
0
C detects the line
Turn left
0
0
0
1
1
D detects the line
Turn right
0
0
1
0
0
E detects the line
Move left
0
0 1 0 1 F detects the line Move right
0
0 1 1 0 G detects the line Go straight
0 0 1 1 1 Forbidden state Software reset the processor
The process involved is taken care of the software. The comparator outputs could have
been directly connected to the microcontroller and all these operations could have been
accomplished in software. But considering that the software would require at least a few
LINE FOLLOWING ROBOT
tens of micro seconds whereas the hardware accomplishes the same in say a 100ns. Thus
due to speed considerations, the present design was arrived at.
4.2. PROCESS EXPLANATION
Figure 4.15: The line following process.
As shown in the figure above, is a typical situation involved. At every sampled
time the commands executed by the microcontroller is also shown. From the above
figure, it should be clear about the software requirements.
If no line is seen, the microcontroller just follows the previous action. This
process is continued till either 5 seconds elapse or a line is reached. If a line is not
reached within 5 seconds (software controlled), the microcontroller shifts into “line find”
mode. In this mode, the robot takes a right turn and starts rotating about a fixed point. The
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LINE FOLLOWING ROBOT
radius is continuously incremented every second. Thus the robot follows the path of a
spiral. This process is continued till either a line is reached or till the robot has achieved a
maximum radius of curvature (is traveling in straight line) when the process is reset and
the robot is made to turn in the starting circle, but now at a different point. This is the
algorithm with minimum complexity considering speed requirements.
Figure 4.17: Spiral movement during line find mode.
The surface is sampled every 2.1ms using the timer 0 interrupt routine. This
implies that the line is sampled 476 times in a second. From observations, the robot
travels at a maximum speed of around 10cm/sec. In other words, 47.6 samples are taken
per cm, or 4.76 samples per mm. This is more than ever required! Due to the fact that the
robot can remember and follow the previous task when its sensors do not see a line,
enables the robot to trace a sharp turn, even if in case the robot runs off the line while
making the turn.
Figure 4.18: Robot’s line approximation
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LINE FOLLOWING ROBOT
4.3. FLOW CHART
START
• Initialize ports appropriately • Set CCP1 & CCP2 modules as
PWM. • Initialize PWM period to 200 sμ . • Initialize timer 0 to overflow
This document contains device specific information.Additional information may be found in the PICmicro™Mid-Range Reference Manual (DS33023), which maybe obtained from your local Microchip Sales Represen-tative or downloaded from the Microchip website. TheReference Manual should be considered a complemen-tary document to this data sheet, and is highly recom-mended reading for a better understanding of the devicearchitecture and operation of the peripheral modules.
There are four devices (PIC16F873, PIC16F874,PIC16F876 and PIC16F877) covered by this datasheet. The PIC16F876/873 devices come in 28-pinpackages and the PIC16F877/874 devices come in40-pin packages. The Parallel Slave Port is notimplemented on the 28-pin devices.
The following device block diagrams are sorted by pinnumber; 28-pin for Figure 1-1 and 40-pin for Figure 1-2.The 28-pin and 40-pin pinouts are listed in Table 1-1and Table 1-2, respectively.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1.
RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog reference voltage.
RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analogreference voltage.
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave selectfor the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3/PGM 24 24 I/O TTL RB3 can also be the low voltage programming input.
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6/PGC 27 27 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock.
RB7/PGD 28 28 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc. DS30292C-page 47
PIC16F87X
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following fea-tures:
• 8-bit timer/counter
• Readable and writable• 8-bit software programmable prescaler• Internal or external clock select
• Interrupt on overflow from FFh to 00h• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module andthe prescaler shared with the WDT.
Additional information on the Timer0 module is avail-able in the PICmicro™ Mid-Range MCU Family Refer-ence Manual (DS33023).
Timer mode is selected by clearing bit T0CS(OPTION_REG<5>). In Timer mode, the Timer0 mod-ule will increment every instruction cycle (without pres-caler). If the TMR0 register is written, the increment isinhibited for the following two instruction cycles. Theuser can work around this by writing an adjusted valueto the TMR0 register.
Counter mode is selected by setting bit T0CS(OPTION_REG<5>). In Counter mode, Timer0 willincrement either on every rising, or falling edge of pinRA4/T0CKI. The incrementing edge is determined bythe Timer0 Source Edge Select bit, T0SE(OPTION_REG<4>). Clearing bit T0SE selects the ris-ing edge. Restrictions on the external clock input arediscussed in detail in Section 5.2.
The prescaler is mutually exclusively shared betweenthe Timer0 module and the Watchdog Timer. The pres-caler is not readable or writable. Section 5.3 details theoperation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-ister overflows from FFh to 00h. This overflow sets bitT0IF (INTCON<2>). The interrupt can be masked byclearing bit T0IE (INTCON<5>). Bit T0IF must becleared in software by the Timer0 module Interrupt Ser-vice Routine before re-enabling this interrupt. TheTMR0 interrupt cannot awaken the processor fromSLEEP, since the timer is shut-off during SLEEP.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
MUX
CLKOUT (= FOSC/4)
SYNC2
CyclesTMR0 Reg
8-bit Prescaler
8 - to - 1MUX
MUX
M U X
WatchdogTimer
PSA
0 1
0
1
WDTTime-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
MUX
0
1 0
1
Data Bus
Set Flag Bit T0IFon Overflow
8
PSAT0CS
PRESCALER
PIC16F87X
DS30292C-page 48 2001 Microchip Technology Inc.
5.2 Using Timer0 with an External Clock
When no prescaler is used, the external clock input isthe same as the prescaler output. The synchronizationof T0CKI with the internal phase clocks is accom-plished by sampling the prescaler output on the Q2 andQ4 cycles of the internal phase clocks. Therefore, it isnecessary for T0CKI to be high for at least 2Tosc (anda small RC delay of 20 ns) and low for at least 2Tosc(and a small RC delay of 20 ns). Refer to the electricalspecification of the desired device.
5.3 Prescaler
There is only one prescaler available, which is mutuallyexclusively shared between the Timer0 module and theWatchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for theWatchdog Timer, and vice-versa. This prescaler is notreadable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructionswriting to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assignedto WDT, a CLRWDT instruction will clear the prescaleralong with the Watchdog Timer. The prescaler is notreadable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0, when the prescaler isassigned to Timer0, will clear the prescalercount, but will not change the prescalerassignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 21 : 41 : 81 : 161 : 321 : 641 : 1281 : 256
1 : 11 : 21 : 41 : 81 : 161 : 321 : 641 : 128
Bit Value TMR0 Rate WDT Rate
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCUFamily Reference Manual (DS33023) must be executed when changing the prescaler assignment fromTimer0 to the WDT. This sequence must be followed even if the WDT is disabled.
2001 Microchip Technology Inc. DS30292C-page 55
PIC16F87X
7.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and apostscaler. It can be used as the PWM time-base forthe PWM mode of the CCP module(s). The TMR2 reg-ister is readable and writable, and is cleared on anydevice RESET.
The input clock (FOSC/4) has a prescale option of 1:1,1:4, or 1:16, selected by control bitsT2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.Timer2 increments from 00h until it matches PR2 andthen resets to 00h on the next increment cycle. PR2 isa readable and writable register. The PR2 register isinitialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bitpostscaler (which gives a 1:1 to 1:16 scaling inclusive)to generate a TMR2 interrupt (latched in flag bitTMR2IF, (PIR1<1>)).
Timer2 can be shut-off by clearing control bit TMR2ON(T2CON<2>), to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available inthe PICmicro™ Mid-Range MCU Family ReferenceManual (DS33023).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2Sets Flag
TMR2 Reg
Output(1)
RESET
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by theSSP module as a baud clock.
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
2001 Microchip Technology Inc. DS30292C-page 57
PIC16F87X
8.0 CAPTURE/COMPARE/PWM MODULES
Each Capture/Compare/PWM (CCP) module containsa 16-bit register which can operate as a:
Both the CCP1 and CCP2 modules are identical inoperation, with the exception being the operation of thespecial event trigger. Table 8-1 and Table 8-2 show theresources and interactions of the CCP module(s). Inthe following sections, the operation of a CCP moduleis described with respect to CCP1. CCP2 operates thesame as CCP1, except where noted.
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is com-prised of two 8-bit registers: CCPR1L (low byte) andCCPR1H (high byte). The CCP1CON register controlsthe operation of CCP1. The special event trigger isgenerated by a compare match and will reset Timer1.
CCP2 Module:
Capture/Compare/PWM Register2 (CCPR2) is com-prised of two 8-bit registers: CCPR2L (low byte) andCCPR2H (high byte). The CCP2CON register controlsthe operation of CCP2. The special event trigger isgenerated by a compare match and will reset Timer1and start an A/D conversion (if the A/D module isenabled).
Additional information on CCP modules is available inthe PICmicro™ Mid-Range MCU Family ReferenceManual (DS33023) and in application note AN594,“Using the CCP Modules” (DS00594).
TABLE 8-1: CCP MODE - TIMER RESOURCES REQUIRED
TABLE 8-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
CaptureCompare
PWM
Timer1Timer1Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base
Capture Compare The compare should be configured for the special event trigger, which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
bit 5-4 CCPxX:CCPxY: PWM Least Significant bitsCapture mode: UnusedCompare mode: UnusedPWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits0000 = Capture/Compare/PWM disabled (resets CCPx module)0100 = Capture mode, every falling edge0101 = Capture mode, every rising edge0110 = Capture mode, every 4th rising edge0111 = Capture mode, every 16th rising edge1000 = Compare mode, set output on match (CCPxIF bit is set)1001 = Compare mode, clear output on match (CCPxIF bit is set)1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. DS30292C-page 61
PIC16F87X
8.3 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin pro-duces up to a 10-bit resolution PWM output. Since theCCP1 pin is multiplexed with the PORTC data latch,the TRISC<2> bit must be cleared to make the CCP1pin an output.
Figure 8-3 shows a simplified block diagram of theCCP module in PWM mode.
For a step-by-step procedure on how to set up the CCPmodule for PWM operation, see Section 8.3.3.
FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM
A PWM output (Figure 8-4) has a time-base (period)and a time that the output stays high (duty cycle). Thefrequency of the PWM is the inverse of the period(1/period).
FIGURE 8-4: PWM OUTPUT
8.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-ister. The PWM period can be calculated using the fol-lowing formula:
When TMR2 is equal to PR2, the following three eventsoccur on the next increment cycle:
• TMR2 is cleared• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)• The PWM duty cycle is latched from CCPR1L into
CCPR1H
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to theCCPR1L register and to the CCP1CON<5:4> bits. Upto 10-bit resolution is available. The CCPR1L containsthe eight MSbs and the CCP1CON<5:4> contains thetwo LSbs. This 10-bit value is represented byCCPR1L:CCP1CON<5:4>. The following equation isused to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at anytime, but the duty cycle value is not latched intoCCPR1H until after a match between PR2 and TMR2occurs (i.e., the period is complete). In PWM mode,CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch areused to double buffer the PWM duty cycle. This doublebuffering is essential for glitch-free PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-catenated with an internal 2-bit Q clock, or 2 bits of theTMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWMfrequency is given by the formula:
Note: Clearing the CCP1CON register will forcethe CCP1 PWM output latch to the defaultlow level. This is not the PORTC I/O datalatch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,CCP1 pin and latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit timer is concatenated with 2-bit internal Qclock, or 2 bits of the prescaler, to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscaler (see Section 7.1) isnot used in the determination of the PWMfrequency. The postscaler could be usedto have a servo update rate at a differentfrequency than the PWM output.
Note: If the PWM duty cycle value is longer thanthe PWM period, the CCP1 pin will not becleared.
log(FPWM
log(2)
FOSC )bits=Resolution
PIC16F87X
DS30292C-page 62 2001 Microchip Technology Inc.
8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuringthe CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to theCCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing theTRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear.
Add W and fAND W with fClear fClear WComplement fDecrement fDecrement f, Skip if 0Increment fIncrement f, Skip if 0Inclusive OR W with fMove fMove W to fNo OperationRotate Left f through CarryRotate Right f through CarrySubtract W from fSwap nibbles in fExclusive OR W with f
111111
1(2)1
1(2)111111111
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,ZZZZZZ
Z
ZZ
CC
C,DC,Z
Z
1,21,22
1,21,2
1,2,31,2
1,2,31,21,2
1,21,21,21,21,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCFBSFBTFSCBTFSS
f, bf, bf, bf, b
Bit Clear fBit Set fBit Test f, Skip if ClearBit Test f, Skip if Set
Add literal and WAND literal with WCall subroutineClear Watchdog TimerGo to addressInclusive OR literal with WMove literal to WReturn from interruptReturn with literal in W Return from SubroutineGo into standby modeSubtract W from literalExclusive OR literal with W
1121211222111
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,ZZ
TO,PD
Z
TO,PDC,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCUFamily Reference Manual (DS33023).
L293DL293DD
PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES
600mA OUTPUT CURRENT CAPABILITYPER CHANNEL1.2A PEAK OUTPUT CURRENT (non repeti-tive) PER CHANNELENABLE FACILITYOVERTEMPERATURE PROTECTIONLOGICAL ”0” INPUT VOLTAGE UP TO 1.5 V(HIGH NOISE IMMUNITY)INTERNAL CLAMP DIODES
DESCRIPTIONThe Device is a monolithic integrated high volt-age, high current four channel driver designed toaccept standard DTL or TTL logic levels and driveinductive loads (such as relays solenoides, DCand stepping motors) and switching power tran-sistors.To simplify use as two bridges each pair of chan-nels is equipped with an enable input. A separatesupply input is provided for the logic, allowing op-eration at a lower voltage and internal clamp di-odes are included.This device is suitable for use in switching appli-cations at frequencies up to 5 kHz.
The L293D is assembled in a 16 lead plasticpackaage which has 4 center pins connected to-gether and used for heatsinkingThe L293DD is assembled in a 20 lead surfacemount which has 8 center pins connected to-gether and used for heatsinking.
June 1996
BLOCK DIAGRAM
SO(12+4+4) Powerdip (12+2+2)
ORDERING NUMBERS:
L293DD L293D
1/7
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VS Supply Voltage 36 V
VSS Logic Supply Voltage 36 V
Vi Input Voltage 7 V
Ven Enable Voltage 7 V
Io Peak Output Current (100 µs non repetitive) 1.2 A
Ptot Total Power Dissipation at Tpins = 90 °C 4 W
Tstg, Tj Storage and Junction Temperature – 40 to 150 °C
DesignGear series C533 &C528 contains Brassgears and steel pinions to ensurelonger life and better wear and tear properties. The gears are fixed onhardened steel spindles polished to a mirror finish.These spindles rotatebetween bronze plates which ensures silent running. The output shaftrotates in a sintered bushing. The whole assembly is covered with aplastic ring. All the bearings are permanently lubricated and thereforerequires no maintenance. The motor is screwed to the gear box frominside. Any small standard motor can be used in combination with thegear box. However the most popular ones are mentioned in the tablebelow. .
3 IStandard small DC motor Dia 33 availiable in 6 V,9 Vor 12VDC
" anyposition150
." 25
'1 54.00,4.76,5.00,6.00,6.35 &7.00 (others on request)-15...+55 . . .,...,... .
Standard Data
GearTorqueCombination motor
MountingWeightAxial thrust
Radial torque
Lateral torque
Output shafts
Ambient' temperature operation
kg-cm
gm"C'" kg
kgkg-cm
eJ.C
Transmission ratios
Motor Data
"'.
/ I~nos.8 Bp,.tappingsOn17PCD
\4 nos. 8BA \
On 17.0PCD
- ---~'-- J -~O~O~~.~~J--GEAr~.~~AD (533(5:;;:.
_--nn__---
.,mm,I .---~ o.
- ._d~ ~., ,--"---
25 I 28.1 i! n-I :i 2J~L---i
'"a.
"0---(5:;;:
MOTOR DC 25 GEAR HEAD (528,
01"I -'-, Q G'
'-..1
----
I
.29.L._. JI
ji
-,_..1
26.1
47.9
""-,, '0.. .,.
Motor Voltage ' '. Direction Speed Torque. .D03 6 CW or ACW 2400 30 gm-cm
D03 6 I Reversible 2400 30 gm-cm
D03 12 CW or ACW 2400 50 gm.cm
003 12 Reversible 7500 25 gm-cm
DC25 2.5 Reversible 2200 3.2 gm-cm
DC25 6 Reversible 8500 4.0 gm-cm
Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 13Publication Order Number:
LM339/D1
LM339, LM239, LM2901,LM2901V, NCV2901,MC3302
Single Supply QuadComparators
These comparators are designed for use in level detection, low−levelsensing and memory applications in consumer, automotive, andindustrial electronic applications.
Features
• Pb−Free Packages are Available*
• Single or Split Supply Operation• Low Input Bias Current: 25 nA (Typ)• Low Input Offset Current: ±5.0 nA (Typ)• Low Input Offset Voltage• Input Common Mode Voltage Range to GND• Low Output Saturation Voltage: 130 mV (Typ) @ 4.0 mA• TTL and CMOS Compatible• ESD Clamps on the Inputs Increase Reliability without Affecting
Device Operation
*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.
PDIP−14N, P SUFFIXCASE 646
1
14
SOIC−14D SUFFIX
CASE 751A1
14
PIN CONNECTIONS
32
1�
�
�
�
1
2
3
4
5
6
7
14
8
9
10
11
12
13
Output 2
− Input 1
Output 1
Output 3
Output 4
+ Input 1
− Input 2
+ Input 2
+ Input 4
− Input 4
+ Input 3
− Input 3
VCC GND
�
�
�
�
4
(Top View)
See detailed ordering and shipping information in the packagedimensions section on page 7 of this data sheet.
ORDERING INFORMATION
See general marking information in the device markingsection on page 8 of this data sheet.
General DescriptionThe MM74HC148 priority encoder utilizes advanced sili-con-gate CMOS technology. It has the high noise immunityand low power consumption typical of CMOS circuits, aswell as the speeds and output drive similar to LB-TTL.
This priority encoder accepts 8 input request lines 0–7 andoutputs 3 lines A0–A2. The priority encoding ensures thatonly the highest order data line is encoded. Cascading cir-cuitry (enable input EI and enable output EO) has beenprovided to allow octal expansion without the need forexternal circuitry. All data inputs and outputs are active atthe low logic level.
All inputs are protected from damage due to static dis-charge by internal diode clamps to VCC and ground.
LM78XXSeries Voltage RegulatorsGeneral DescriptionThe LM78XX series of three terminal regulators is availablewith several fixed output voltages making them useful in awide range of applications. One of these is local on cardregulation, eliminating the distribution problems associatedwith single point regulation. The voltages available allowthese regulators to be used in logic systems, instrumenta-tion, HiFi, and other solid state electronic equipment. Al-though designed primarily as fixed voltage regulators thesedevices can be used with external components to obtain ad-justable voltages and currents.
The LM78XX series is available in an aluminum TO-3 pack-age which will allow over 1.0A load current if adequate heatsinking is provided. Current limiting is included to limit thepeak output current to a safe value. Safe area protection forthe output transistor is provided to limit internal power dissi-pation. If internal power dissipation becomes too high for theheat sinking provided, the thermal shutdown circuit takesover preventing the IC from overheating.
Considerable effort was expanded to make the LM78XX se-ries of regulators easy to use and minimize the number ofexternal components. It is not necessary to bypass the out-
put, although this does improve transient response. Input by-passing is needed only if the regulator is located far from thefilter capacitor of the power supply.
For output voltage other than 5V, 12V and 15V the LM117series provides an output voltage range from 1.2V to 57V.
Featuresn Output current in excess of 1An Internal thermal overload protectionn No external components requiredn Output transistor safe area protectionn Internal short circuit current limitn Available in the aluminum TO-3 package
Voltage RangeLM7805C 5V
LM7812C 12V
LM7815C 15V
Connection Diagrams
Metal Can PackageTO-3 (K)
Aluminum
DS007746-2
Bottom ViewOrder Number LM7805CK,LM7812CK or LM7815CK
See NS Package Number KC02A
Plastic PackageTO-220 (T)
DS007746-3
Top ViewOrder Number LM7805CT,LM7812CT or LM7815CT