Lesson Plan

J. S. S. ACADEMY OF TECHNICAL EDUCATION, MAURITIUS

B. E: FEB 2011- MAY 2011-EVEN SEMESTER

LESSON PLAN

Name of the faculty : Mr. Chiniah Aatish No. of Students: 8

Semester/Branch : B.E –VIII SEMESTER

Subject/Subject Code : ACA - Advanced Computer Architecture

Holidays Planned Date

Topics Covered Actual Date of Completion

No. of Classes

Executed Date

Remarks

Unit 1:

5th February

FUNDAMENTALS OF COMPUTER DESIGN: Introduction; Classes of computers;

1 hour

12th February

FUNDAMENTALS OF COMPUTER DESIGN: Defining computer architecture; Trends in Technology

1 hour

19th FUNDAMENTALS OF 1 hour

February COMPUTER DESIGN: Power in Integrated Circuits and cost; Dependability

26th February

FUNDAMENTALS OF COMPUTER DESIGN: Measuring, reporting and summarizing Performance;

1 hour

5th March FUNDAMENTALS OF COMPUTER DESIGN: Quantitative Principles of computer design

1 hour

Unit 2:

PIPELINING: Introduction; Pipeline hazards; Implementation of pipeline;

3 Hours

PIPELINING: What makes pipelining hard to implement?

3 Hours

Unit 3: INSTRUCTION –LEVEL PARALLELISM – 1: ILP: Concepts and challenges; Basic Compiler Techniques for exposing ILP;

3 hours

Reducing Branch costs with prediction; Overcoming Data hazards with Dynamic scheduling; Hardware-based speculation.

4 hours

Unit 4: INSTRUCTION –LEVEL PARALLELISM – 2: Exploiting ILP using multiple issue and static scheduling; Exploiting ILP using dynamic scheduling, multiple issue and speculation;

3 hours

Advanced Techniques for instruction delivery and Speculation; The Intel Pentium 4 as example.

4 hours

Unit 5: MULTIPROCESSORS AND THREAD –LEVEL PARALLELISM: Introduction; Symmetric shared-memory architectures; Performance of symmetric shared–memory multiprocessors;

3 hours

Distributed shared memory and directory-based coherence; Basics of synchronization; Models of Memory Consistency.

4 hours

Unit 6: REVIEW OF MEMORY HIERARCHY: Introduction; Cache performance;

3 hours

Cache Optimizations, Virtual memory.

3 hours

Unit 7: MEMORY HIERARCHY DESIGN:

3 hours

Introduction; Advanced optimizations of Cache performance;

Memory technology and optimizations; Protection: Virtual memory and virtual machines.

3 Hours

Unit 8: HARDWARE AND SOFTWARE FOR VLIW AND EPIC: Introduction: Exploiting Instruction – Level Parallelism Statically; Detecting and Enhancing Loop-Level Parallelism; Scheduling and structuring code for parallelism; Hardware support for exposing parallelism;

3 hours

Scheduling and structuring code for parallelism: Hardware support for exposing parallelism; Predicated instructions; Hardware support for compiler

4 hours

speculation; The Intel IA-64 Architecture and Itanium Processor; Conclusions.

Revision 2 hours

IA Test Date:

Test No. Date

1 14th,15th,16th March 2011

2 21st, 22nd,23rd April 2011

3 19th,20th,21st May 2011

4

Total Number of Teaching Hours:

Total Number of teaching hours as per VTU Schedule: 52

Total Number of teaching hours as per Lesson Plan : 54

Text Books:

1. Structured Computer Organization (5th Edition) Andrew S. Tanenbaum. ISBN-13: 978-0131485211

2. Computer System Architecture (3rd Edition) M. Morris Mano. ISBN-13: 978-0131755635

Reference Books:

1. Computer Architecture: A Quantitative Approach, 4th Edition by John L. Hennessy and David A. Patterson

2. The Essentials of Computer Organization And Architecture by Linda Null

3. Computer Organization and Architecture: Designing for Performance (8th Edition) by William Stallings

Signature of the faculty Signature of the HOD Signature of the Principal