Leonardo Insight II - Design of PCB and MCM for high speed digital systemsPage 1 Design of PCB and MCM for high speed digital systems Torstein Gleditsch.

Leonardo Insight II - Design of PCB and MCM for high speed digital systemsPage 1

Design of PCB and MCM for high speed digital systems

Torstein Gleditsch

SINTEF Electronics and Cybernetics

The art of compromise


What this course is and what it is not

• This course is an introductory course to designing Printed Circuit Boards and Multi Chip Modules for high frequency digital applications.

• It will introduce you to the basic concepts of transmission lines and how utilize this theory into practical designs.

• It will introduce you to modeling of lines, drivers and receivers to help you get a better understanding of the effects of the different measures.

• It will not make you a proficient SPICE user.

• At last it will make you understand why high speed digital design is difficult and how to improve a design.


What is so special with high-speed digital

• Broad band – Must cover every frequency from DC to GHz

– No “Dirty tricks” possible

• Higher order harmonics is necessary for edge integrity.

• High number of critical signals

• Digital signals is more tolerant to distortion

• Switching create high currents in short periods


A digital signal

out

0.0n 10.0n 20.0n 30.0ntime [sec]

-1.0

1.0

3.0

5.0

6.0

Vol

tage

[V

olt]

• Frequency 50MHz

• Risetime 1ns ( 10% - 90% )

• Falltime 1ns ( 10% - 90% )

• Bandwidth 350MHz


Spectrum of a single pulseFFT(V(1))

0.0M 50.0M 100.0M 150.0M

FREQ [Hz]

0.0

0.1

0.2

0.3

0.4

Y A

xis

Tit

le [

Vol

t]

FFT(V(1))

0.0M 50.0M 100.0M 150.0M 200.0MFREQ [Hz]

0.0

0.1

0.2

0.3

0.4

Apl

itud

e [V

olt]

10 ns risetime 1 ns risetime


Spectrum of a pulse trainFFT(V(1))

0.0G 0.2G 0.4G 0.6G 0.8G 1.0GFREQ [Hz]

0.0

0.5

1.0

1.5

Am

plit

ude

[Vol

t]

FFT(V(1))

0.0G 0.2G 0.4G 0.6G 0.8G 1.0GFREQ [Hz]

0.0

0.5

1.0

1.5

Y A

xis

Tit

le [

Vol

t]


The effect of missing harmonics

0 2.5 5 7.5 10 12.5 15 17.5

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

0 2.5 5 7.5 10 12.5 15 17.5-1

-0.5

0

0.5

1

0 2.5 5 7.5 10 12.5 15 17.5

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

0 2.5 5 7.5 10 12.5 15 17.5

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1st harmonic only

1st and 3rd harmonic only

1st to 5th harmonic

1st to 21st harmonic


Why transmission line calculations

• Transmission line theory describe the behavior of the signals on a PCB or MCM

• Simple models like RC-calculation do not apply at higher frequencies

• It is possible to predict the quality of the signal.

• It is possible to experiment with different types of termination.


When do I have to take into account transmission lines effects

• Thumb rule: When the rise time is less 2.5 times the time delay of the signal on the trace. (Transit time)

• Another: If the trace length is larger than 1/7 of the largest wavelength of the signal. (At upper frequency edge)

• Example with two different effective dielectric constants

Risetime (ns)Risetime (ns)

Tra

ce le

ngth

(m

m)

Tra

ce le

ngth

(m

m)

0 1 2 3 4 5 60

100

200

300

400

0 0.5 1 1.5 20

20

40

60

80

100

120

140


Reflections from a 1ns risetime signal

40 mm non terminated line 300 mm non terminated line

l1outout

0.0n 10.0n 20.0n 30.0n

time [sec]

-4.0

-2.0

0.0

2.0

4.0

6.0

8.0

Y A

xis

Tit

le [

Vol

t]

l1outout

0.0n 10.0n 20.0n 30.0ntime [sec]

-4.0

-2.0

0.0

2.0

4.0

6.0

8.0

Y A

xis

Tit

le [

Vol

t]


Crosstalk

300 mm non terminated line40 mm non terminated line

l2outout1

0.0n 10.0n 20.0n 30.0ntime [sec]

-1.0

-0.5

0.0

0.5

1.0

1.5

Y A

xis

Tit

le [

Vol

t]

l2outout1

0.0n 10.0n 20.0n 30.0ntime [sec]

-1.0

-0.5

0.0

0.5

1.0

1.5

Y A

xis

Tit

le [

Vol

t]


Transmission Lines

A brief introduction


Basic Transmission Line Types

W

Hr

tant

W

t

H

Microstrip

Stripline


Dielectric constant (Relative permittivity) (r )

• Describe a materials ability to hold charge compared to vacuum when used in a capacitor.

• The permittivity of a vacuum is: 0 = 8.85419 ·10-10

• The permittivity of a material is: = 0 r

• If we put a dielectric material between two capacitor plates of area A and a distance D the capacitance in Farad is:

C= AD

[F]


Loss tangent ( tan )

• Describe the materials “resistance” to change of polarization

• is the conductivity of the dielectric at frequency . (S/m)

• is the permittivity of the material. (F/m)

tan =

2 f


Magnetic permeability ()

The magnetic permeability describe a magnetic property of a material. It is the ratio between the magnetic flux density (B) and the external field strength (H).

=B

H

The relative permeability of a material is the permeability relative to vacuum.

µ =µrµ0

µ0=4

107

[H/m]


Properties of glass reinforced materials

Material Dielectric constant( r )

Loss tangent( tan )

FR-4 4.0 0.02

Cyanate Esther 2.8 0.009

Polyimide 3.4 0.01

BismaleimideTriazin 2.9 0.011Teflon 2.2 0.0009


Basic transmission line diagram

DriverTransmission line

Termination resistor


Some Transmission Line Properties

• Signal velocity (m/s)– Influenced by dielectric constant of materials

• Impedance– Mostly influenced by dielectric constant of material, width of line

and distance to ground plane(s)

• Loss– Influenced by conductivity of conducting material, frequency of

signal and loss tangent of the material.

• Dispersion– Influenced by frequency dependant dielectric constant


The four describing parameters

• R Resistance per unit length [ohm / m]

• C Capacitance [ F / m ]

• L Inductance [ H / m]

• G Conductance [ S / m ]


Signal velocity ( )

• The signal velocity is measured in m/s• For a practical calculations the signal velocity is only dependant on the

relative dielectric constant r

• With c0 the velocity of light in vacuum, we get:

v=c0

r[m/s]


Impedance ( Z0 )

• Impedance is measured in Ohms

• Impedance describes the AC resistance a driver will see when driving a signal into a indefinitely long transmission line.

Z0=R+L jG+Cj

For a loss less line this simplifies to:

Z0=L

C

[ohm]

[ohm]


Loss ()

• Loss is measured in dB / m

• Loss is the reduction of signal voltage along a line due to resistance and leakage

• The resistive losses is due to resistance in conductor and ground plane.

• The dielectric losses is due to the energy needed to change polarization of the dielectric material.

• The radiation losses is the energy sent from the conductor acting as an antenna.


Resistive losses ( C )

The resistance is based on the cross-section of the conductor and the bulk resistivity of the conductor material:

R=1

t

=8,68589 R

2Z0

The loss factor is then calculated by:

[dB/m]

[ohm] = bulk conductivity [S/m]w = line width [m]t = line thickness [m]


Skin depth ( s )

At higher frequencies only a thin layer of the conductor transport the current. The thickness where the current density is reduced to 1/e is called the skin depth s.

s=1

µ f[m]


Resistance at higher frequencies

When the conductor is much thicker than the skin depth one have to substitute the skin depth for the thickness in the resistance formula:

[ohm]

The resistance has now become frequency dependent !

R=1

s

R=1

1

µ f


Dielectric loss ( D )

The dielectric loss D is due to the energy needed to change

the polarization of the dielectric material. The conductance is

then:

G=2 f C tan

D=

1

28,68589 G Z0

[S/m]

The dielectric loss is then:

[dB/m]


Radiation loss

• All lines are radiating more or less

• Radiation loss is often negligible from a signal integrity standpoint but important from a EMC standpoint.

• Radiation loss is difficult to calculate


Dispersion

• Dispersion is an effect caused by different velocities for the different frequency components. The result is a different phase change for each of the frequency components.

• The reason for this is that the dielectric constant of the material vary with frequency.

• Dispersion is one of many sources of signal distortion.

• It is not easy to calculate dispersion because the lack of frequency dependant material data.

• Dispersion may cause trouble when exact edge position is important.


Crosstalk

Crosstalk is coupling of a signal form one line to another

There are two key parameters used to describe crosstalk

Kf the forward crosstalk coefficient

Kb the backward crosstalk coefficient (normally the largest)

Td is the transit time delay

K f =-1

2

Lm

Z0- Cm Z0

Kb=-

LmZ0

- Cm Z0

4Td

( )


Reflections

outin1

0.0n 10.0n 20.0n 30.0n

time [sec]

-2.0

0.0

2.0

4.0

6.0

Y A

xis

Tit

le [

Vol

t]

r =Z1 - Z0

Z0 +Z1

In this case Z1 = R2 = 25 ohm, and Z0 = 50 ohm.

Then r = -0.333 => -1.66 overshoot


Via modeling

• Inductance and capacitance of via’s is difficult to calculate without 3D field analysis tools.

• A 1nH inductance and a 1pF capacitance can be used as a start

• Careful use of coaxial line equations can also give an indication of the values.


Building a good board

Some hints for the high performance designer


What is important for a good board

• Symmetrical around center

• Tolerant for etch variations (+/- 1 mil is not unusual)

• Lines spaced for acceptable crosstalk

• Standard dielectric thickness’

• Tolerant for variation in dielectric thickness

• Acceptable high loss. (The loss may be your friend)

• Acceptable total thickness

• Power and ground layers close together (typically 100um)


Laminate tolerances

Dictionary: Toleranse = Tolerance Tykkelse = ThicknessKlasse = Class Glassvevtype = Glass fabric type


Prepreg Tolerances


Impedance tolerance to line width

As line width increases, dependence on absolute tolerance decreases

Border lines on +-1mils absolute line width tolerance


Impedance tolerance to laminate tolerance


Minimum line widths vs. r and dielectric thickness

Curves on equivalent dielectricthickness


8 layer high-speed lay-up example 1

Dictionary:Kobber =Copper

rent = pure


8 layer high-speed lay-up example 2


Pack32

A desktop calculator for transmission lines


Idea behind the program

• Easy to use

• PC based ( Windows 95 or NT )

• Good enough results (better than textbook formulas)

• Easy to organize material, component and lay-ups

• Easy for the developers to add new functions.

• Data is stored one place, no tedious typing

• Fast, no calculation take more than one second


Workflow for transmission line analysis

1. Enter material data if not in database

2. Define a Lay-up

3. Calculate the line properties for a single line

4. Adjust Lay-up and re-calculate until satisfied

5. Calculate for double lines to check for crosstalk and dual line impedance.

6. Generate a SPICE model for a critical net in the design, single or double lines as appropriate

7. Simulate and adjust line parameters (width, spacing, lay-up)

8. Use the obtained parameters as design rules for your critical nets.


Material database

For transmission line calculation,

one need:

•Electrical conductivity

•Dielectric constant

•Dielectric loss factor

•Magnetic permeability

Sorry! You have not got the English version!


Lay-up definition

Sorry! Norwegian text!


Single line analysis

Stripline

Microstrip

Buried microstrip


Dual Line Analysis


Exercise

Design a lay-up with these properties:

• 50 Ohms impedance

• FR-4 Dielectric

• No Solder resist

• 4 Signal layers

• Two Power layers

• Two Ground layers

• No more than 3dB loss for a 10cm line at 1GHz

• Tolerant for +/- 1 mil etch error.


Analog simulation of digital signals

Time for sacrifice


The two main simulation approaches

• Time domain simulators– Easy to model nonlinear circuits such as digital drivers

– Has no possibility to handle frequency dependent parameters

– Convergence problems

– Relatively slow simulation

– Typical product: SPICE

• Frequency domain simulators – Easy to model circuits with frequency dependent parameters

– Only possible to model linear circuits

– Fast and easy convergence

– Typical product: HP-EEsof Series IV Linear simulator

What we really need does not exist


Aim-SPICE

• Based on Berkeley SPICE version 3.E1

• Good user interface

• Good post processor

• Cheap

• Student version is limited but usable

• Designed for Windows95 / NT

• Text based, no schematic editor


A SPICE example

First line

.MODEL LineModel LTRA L=460N C=94P R=10 LEN= .04

V1 in 0 PULSE(0,10,10n,1n,1n,10n,20n)

R1 in lin 50

O1 lin 0 out 0 LineModel

R2 out 0 50


General

• All values are in basic SI units [Ohm, Farad, Henry,Volt, Ampere]

• Postfixes are allowed: m = 10-3 , u= 10-6 , n= 10-9 , p= 10-12

k= 103 , meg= 106 , g= 109

• Element names must be unique and is interpreted by ASCII value

• Node names can be numbers or names and is interpreted by ASCII

• Node 0 is the system ground and MUST be connected.

• The first line MUST be the model name

• Blank lines are allowed

On the following pages some important elements is shown, refer to the online SPICE manual for details and more options.


Passive elements

ResistorRxxx <N1> <N2> <Value>

CapacitorCxxx <N1> <N2> <Value>

InductorLxxx <N1> <N2> <Value>


Transmission lines

Loss-less transmission line

Txxx <N1> <Gnd> <N2> <Gnd> <Z0=Value> [Td=Value]

Lossy transmission line.MODEL LineModel LTRA L=460N C=94P R=10 LEN= .04

Oxxx <N1> <Gnd> <N2> <Gnd> <Name>


Voltage sources

Voltage sourceVxxx <N+> <N-> <Type>

Some useful Types for transient analysis

For a pure DC source:DC <Value>

For a pulse train generator PULSE(<High voltage>,<Low voltage>,<Delay>,<Rise-

time>,<Fall-time>,<High time>,<Cycle time>)


Exercise

Simulate a 15cm long microstrip with these specs:

• 125 um wide

• 17.5um thick

• Dielectric is polyimide

• Dielectric thickness is 100um

• Source impedance is 70 Ohm

• Termination resistance is 50 Ohms

• Rise and fall times is 0.8ns, frequency is 200MHz

1. What is the maximum over / undershoot

2. Insert a capacitor of 50pF in parallel with the terminator, see what happens.


Subcircuits

SPICE have a nice feature called sub-circuits which work like subroutines.

The syntax is:

.SUBCKT <Name> <Node1> <Node2> ....[Node n]

<Spice code with the node names as I/O>

.ENDS

You call this subcircuit with

Xxxx <N1> <N2> ... [Nn] <Name>


Distributed models

An other way of simulating transmission lines is by using distributed models.

Selecting a high number of segments will give excellent results but may cause problems in initialization.

The Student version can only handle 10 of these segments due to the maximum of 50 elements.


PACK model generation

PACK can generate the models for you


Pack Generated Distributed Model


Exercise

Make a distributed model of the last exercise and compare results


Exercise

A board needs 60 Ohms lines in the inner layers.

Design a board for 60 Ohm lines and generate a single LTRA model of 5 cm.

Make a three segment line with a 60 Ohm driver.After the first segment the line splits into the two other segments. Each of the splits is terminated in 60 ohms.


Modeling of drivers and receivers

When is enough enough


Not all models have long hair and blue eyes

Driver models are difficult to obtain, usually you have three options:

1. Use vendor supplied SPICE models of the output stage

2. Use vendor supplied IBIS models

3. Roll your own simple models based on rise time and output impedance.


Vendor supplied SPICE models

• Difficult to obtain, vendors generally do not want to disclose their design.

• Most vendors require non disclosure agreement

• Difficult to run. Vendors usually use H-SPICE, board designers do not.

• Models are to detailed, unnecessary accuracy give slow simulation.

• Difficult to set the right environment for drivers etc.

So, vendor supplied SPICE models is generally not a good idea.


Vendor supplied IBIS models

IBIS solves most of the problems related to vendor models except:

• Not all SPICE simulators run IBIS models

• Not all vendors supply IBIS models, although this is rapidly increasing

IBIS models is sufficiently accurate for package and module simulation.

So, use IBIS models (If you can)


IBIS model


IBIS I/V curves (ABT 244)

-4 -2 0 2 4 6 8 10

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

-4 -2 0 2 4 6 8 10

-0.5

0

0.5

1

1.5

Pull-up curve

( Referenced to Vcc )

Y-axis: Current [A]

X-axis: Voltage [V]

Pull-down curve


IBIS viewing tool


Make your own models

• Simple models are sufficient to study transmission line effects and to develop design rules.

• They are not sufficient for optimizing a specific net.

• A very simple model:


Exercise

Study the supplier SPICE model of an “IBIS” driver.

Adjust the data to fit an SN74ALVCH16244

Compare with data sheets and the timing article


Routing of high speed signals

There is no easy way

( but some auto-routers are really good )


Main Issues for Routing

• Routing topologies and loading

• Impedance

• Rise and fall time degradation

• Signal Skew (Signal delay difference)

• First incident clocking

• Crosstalk

• Signal return path

• Termination


Point to Point Topology

• This is the ideal topology but not very efficient in that it requires a lot of extra buffers.

• Always use this topology for critical clock trees.

• Use low skew clock buffers

• Skew can be compensated with delay lines


Fan / Star topology

• This topology is routing efficient but put heavy load on the driver, especially where several lines fan out.

• Use drivers with low output impedance.

• Terminate properly at each receiver or reflections will propagate back and forth in the net.

• Be careful with the high power consumption of many terminated lines


T - Topology

• This split will cause a 33% negative reflection if all lines are of same impedance.

• All ends (also driver) should be terminated properly for larger nets

• The driver will have to drive twice the amount of DC into the termination resistors.


Daisy Chain

• The preferred topology for high speed digital.

• Terminate in both ends.

• Allow no stubs

• Keep tap load low.

• Keep distance between loads so high that the signal can recover.


Rise and fall time degradation

Any lossy transmission line acts as a filter which filters the high frequency components first. Since the high frequency components is damped more the signal will show slower rise times at the end of the line.


Signal skewSignal skew is the delay difference at inputs.

Keeping low signal skew in a clock system is a challenge and there are several effects to consider.

• Keep every signal trace equally long

• Use low skew drivers

• Rise time degradation may pose a problem in calculated delay daisy chains.

• Signals travel faster at outer layers, so trace lengths must be compensated. Or - use only inner layers.

• Poor decoupling influence rise time.

• Use only first incident clocking or better, reduce reflections to zero.


Signal return path

The high frequency signals follow a mirror image of the trace on the ground plane. Do not degrade this return by:

• Changing to layers which have another ground-plane without placing a ground-ground via close to the signal via. If the new reference plane is a power plane a low inductance decoupling is placed close to the signal via

• Using split reference planes.

• Using one small via for several returns, this may cause common mode problems.


How To Design Delay Lines

• Remember loss

• Use meander structure, be careful to avoid inductor effects.

• Keep meander lines at least 4 times the distance to ground plane apart to avoid distortion.

• Preferably use inner layers, this reduce distortion and keep inductance low.


Line Termination

Terminating lines driven with drivers that do not allow termination


Why terminate the signals

• Termination is a method to match the driver, line and receiver in such way that no reflections are generated.

• Generally the ideal would be to do a parallel termination in the line impedance

• Terminate critical lines that are longer than 1/3 of the rise time. On FR-4 this mean that a 1ns rise signal, the longest unterminated line is 5cm.

• Reflections can cause double trigging, if using non- terminated nets do not use data before the reflections have settled.


Series Termination

• Used to match driver impedance

• Slow rise and fall times (Some times good, for instance to achieve low crosstalk)

• Absorb reflections if matched to line


Parallel Termination

• The termination of choice for high speed digital, especially for ECL, PECL and other technologies intended for termination.

• High power consumption.

• 100% clean signals possible


RC Termination

• AC termination, better for technologies not intended for termination.

• Low power consumption (No DC consumption)

• Be careful with inductive capacitors, select capacitors with care.


Thevenin Termination

• Ideal for bus termination or lines with 3-State drivers.

• 330 Ohm & 220 Ohm is often used.

• Faster switching from 3-state

• Does NOT correctly terminate the line, reflections will occur


Diode Termination

• Kills large over and undershoot

• Not generally useful in high-speed systems. (A design needing this type of termination have probably greater problems elsewhere)


Power distribution and de-coupling

How to supply the right voltage at the right place at the right time


Power distribution

• The power and ground system serves two purposes. – First to serve as a return path for the signal.

– Second to supply the devices with power.

• The high frequency components of today is using a lot of power at a low voltage. The result is very high currents.

• A modern FPGA can draw several amperes the first nanosecond after switching.

• To meet these challenges one need a low inductance, low resistance and high capacitance power system.


Why Decoupling

• The high switching currents in today's components create a need for a local current supply with sufficient charge to avoid a severe voltage drop at the power pins.

• When these resources are exhausted on need larger supplies that are closer than the power supply.

• Closely spaced power planes give a good high frequency, low inductance decoupling but it can not hold much charge.


A Capacitor is Not a Capacitor

• A capacitor is a passive device dominated by capacitance.

• A 100nF capacitor can have C=84nF, L=1.3nH, R=0.13ohm

• A capacitor is often described with its resonance frequency

• Different dielectrics NPO, X7R or Z5U have different properties.

• Usually thin and wide X7R chips is the best choice for decoupling.

• To be sure on have to measure the inductance which is difficult

• To compare two capacitors of same nominal capacitance chose the one with the highest resonance frequency.

• So called high frequency capacitors is not necessarily less inductive

fres =1

2 LC


Selecting Decoupling Capacitors

Selecting a decoupling capacitor is not easy but some general

rules apply:

• Select the smallest value that is sufficient to decouple the device. If you do not know what is sufficient choose one 100nF capacitor for each power pin

• Use only chip capacitors, leaded capacitors is to inductive to be of any help.

• Decouple in levels with the smallest value (i.e. 100nF) close to the power pin, the medium values(i.e. 10F) evenly distributed, the higher values (i.e. 47F tantalum) close to the connector power pins.


Where to place decoupling capacitors

• Get as close as possible to power and ground pins.

• Keep distance to pin very SHORT and the trace WIDE.

• Set the via as close as possible to the capacitor, preferably in the pad.

• One capacitor for every power (and ground) pin is a good rule of thumb, you do not have to mount all of them in production if the system works with less.

• Calculate inductance. If too high - forget the capacitor.

• Do not forget to place decoupling capacitors close to termination resistors, it is important to keep the reference voltages steady.


Splitting power planes

• Be very careful with splitting ground planes.

• If you have to split, keep the split narrow and secure an AC return path.

• Splits act as slot antennas and will radiate heavily.

• Remember that digital signals are broad band and that filters are narrow band. Filters over the gap may cause problems.


Microstrip Over a Slotted Ground Plane

IEEE Circuits & Devices Nov. 1997

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Leonardo Insight II - Design of PCB and MCM for high speed digital systemsPage 1 Design of PCB and MCM for high speed digital systems Torstein Gleditsch.

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