Lectures on Memory Interface - · PDF fileLectures on Memory Interface. Lecture 2 ... • 8088 MP sends out a 20 bit memory address lines to 2716 EPROM that have 11 address connections

Designed and Presented by

Dr. Ayman Elshenawy Elsefy

Dept. of Systems & Computer Eng..

Al-Azhar University

Email : [email protected]

eaymanelshenawy.wordpress.com

Lectures on Memory Interface

Lecture 2Address Decoding

Lecture Objectives• Decode the memory address and use the outputs to select

various memory components.

• Use programmable logic devices (PLDs) to decode memory addresses.

Address Decoding

• To attach a memory device to the MP, it is necessary to

decode the address sent from the MP.

• Decoding makes enable the memory to select one memory

section or partition of the memory map at a time.

• Without an address decoder, only one memory device can

be connected to a MP, which make it virtually useless.

Why Decode Memory?• 8088 MP sends out a 20 bit memory address lines to 2716

EPROM that have 11 address connections while it is

writing or reading data.

• If only 11 address pins are connected to the memory, the

CPU will see only 2KB of memory instead of the 1MB.

• The decoder corrects the mismatch by decoding the address

pins that do not connect to the memory.

Simple NAND Gate Decoder• When the 2K × 8 EPROM is used, address connections

A0–A10 of the 8088 MP are connected to address inputs

A0–A10 of the EPROM.

• The remaining nine address pins (A11–A19) are connected

to the inputs of a NAND gate decoder.

• The decoder selects the one of the 2K-byte sections in

EPROM.

• In this circuit, a single NAND gate decodes the memory

address.

• The output of the NAND gate is a logic 0 whenever the

8088 address pins attached to its inputs (A11–A19) are all

logic 1s.

• The active low output of the NAND gate decoder is

connected to the input pin 𝐶𝐸 that enables the EPROM.

Simple NAND Gate Decoder

Simple NAND Gate Decoder• The OE is connected using the 𝑅𝐷 or 𝑀𝑅𝐷𝐶 from the MP.

• The IO/ 𝑀 control is connected from the processor.

• Recall that whenever is a logic 0, data will be read from

• the EPROM only if is also a logic 0. The pin is activated by

the 8088 signal or the (memory read control) signal of

other family members.• NAND gates are rarely used to decode memory because

each memory device requires its own NAND gate decoder

and NAND gate have high cost.

• If the 20-bit binary address, decoded by the NAND gate, is

written so that the leftmost nine bits (A11-A19) are 1’s and

the rightmost 11 bits (A0-A10) are don’t cares (X), the

actual address range of the EPROM can be determined.

Simple NAND Gate Decoder• The don’t cares are first written as 0s to locate the lowest

address and then as 1s to find the highest address.

• Example 10–1 also shows these binary boundaries as

hexadecimal addresses. Here, the 2K EPROM is decoded at

memory address locations FF800H–FFFFFH.

• Notice that this is a 2K-byte section of the memory and is

also located at the reset location for the 8086/8088

(FFFF0H), the most likely place for an EPROM in MP.

The 3-8 line decoder (74LS138)• One of the most common, although not only, integrated

circuit decoders found in many MP based systems

• Only one of the eight outputs ever goes low at any time.

• For any of the decoder’s outputs to go low, the three enable

inputs (𝐺2𝐴 , 𝐺2𝐵 , and G1) must all be active (𝐺2𝐴 and

𝐺2𝐵 logic 0 and G1 logic 1).

• Once the 74LS138 is enabled, the address inputs (C, B, and

A) select which output pin goes low.

• Imagine eight EPROM inputs connected to the eight

outputs of the decoder! This is a very powerful device

because it selects eight different memory devices at the

same time. Even today this device still finds wide

application.

The 3-8 line decoder (74LS138)

The 3-8 line decoder (74LS138)

Sample Decoder Circuit• The outputs of the decoder are connected to eight different

memory devices. The decoder selects eight 8Kbyte blocks

of memory for a total memory capacity of 64K bytes.

• All of the address connections from the 8088 MP are

connected to this circuit.

• The signal 𝑅𝐷 from the 8088 MP is connected to the

inputs 𝑂𝐸 of the EPROMs. This allows only the selected

EPROM to be enabled and to send its data to the MP

through the data bus whenever becomes a logic 0.

• In this circuit, a three-input NAND gate is connected to

address bits A17–A19. When all three address inputs are

high, the output of this NAND gate goes low and enables

input 𝐺2𝐵 of the 74LS138.

Sample Decoder Circuit• Input G1 is connected directly to A16.

• In other words, in order to enable this decoder, the first

four address connections (A19–A16) must all be high.

• The address inputs C, B, and A connect to MP address pins

A13–A15. These three address inputs determine which

output pin goes low and which EPROM is selected

whenever the 8088 outputs a memory address within this

range to the memory system.

Sample Decoder Circuit

Address range of the entire decoderThis is a 64K-byte span of the memory

the EPROM connected to output 0

the EPROM connected to output 1

Dual 2-4 decoder• contains two separate 2-to-4 line decoders—each with its

own address, enable, and output connections.

Dual 2-4 decoder• contains two separate 2-to-4 line decoders—each with its

own address, enable, and output connections.

Dual 2-4 decoder

Dual 2-4 decoder

This circuit uses a 128K × 8 EPROM (271000) and a 128K × 8 SRAM (621000).

The EPROM is decoded at memory locations E0000H–FFFFFH and the SRAM is decoded

at addresses 00000H–1FFFFH.

Dual 2-4 decoder• The EPROM is located at the top of the memory space and

the SRAM at the bottom.

• Output 𝑌0 of decoder U1A activates the SRAM whenever

address bits A17 and A18 are both logic 0s if the signal

IO/ 𝑀 is a logic 0 and address line A19 is a logic 0.

• This selects the SRAM for any address between 00000H

and 1FFFFH.

• The second decoder (U1B) is slightly more complicated

because the NAND gate (U4B) selects the decoder when

IO/ 𝑀 is a logic 0 while A19 is a logic 1. This selects the

EPROM for addresses E0000H through FFFFFH.

PLD Programmable Logic Decoders

• programmable logic device (PLD) can be used as decoder.

• simple PLD are PLA (programmable logic array), PAL

(programmable array logic), and GAL (gated array logic).

• Appeared in memory system and digital designs since the

early 1990s.

• The PAL and the PLA are fuse-programmed, as is the

PROM, and some PLD devices are erasable devices (as are

EPROMs). In essence, all three devices are arrays of logic

elements that are programmable.

• SPLD are used in memory decoding.

• Complex PLDs are also available, such as CPLDs (complex

programmable logic devices), FPGAs (field programmable

gate arrays), and FPICs (field programmable interconnect)

and are used in complete systems.

Combinatorial Programmable Logic Arrays

• This device, has 10 fixed inputs, two fixed outputs, and six pins

that are programmable as inputs of outputs. Each output signal is

generated from a seven-input OR gate that has an AND gate

attached to each input. The outputs of the OR gates pass through

a three-state inverter that defines each output as an AND/NOR

function.

• All of the fuses connect all of the vertical/horizontal

connections.

• Programming is accomplished by making fuses to connect

various inputs to the OR gate array. The wired-AND function is

performed at each input connection, which allows a product term

of up to 16 inputs. A logic expression using the PAL16L8 can

have up to seven product terms with up to 16 inputs NORed

together to generate the output expression. This device is ideal as

a memory address decoder because of its structure. It is also

ideal because the outputs are active low.

Combinatorial Programmable Logic Arrays

Combinatorial Programmable Logic Arrays

• A PAL is programmed with a software package such as

PALASM, the PAL assembler program. More recently, PLD

design is accomplished using HDL (hardware description

language) or VHDL (verilog HDL).

• The VHDL language and its syntax are currently the industry

standard for programming PLD devices.

VHDL Language

• Note that this program was developed by using a text editor such

as EDIT.

• Comments in VHDL programming begin with --.

• Library and use statements specify the standard IEEE library

using standard logic.

• Entity statement names the VHDL module(DECODER_10_17)

• Port statements define the in, out, and in-out pins used in the

equations for the logic expression, which appears in the begin

block. A19, A18, A17, and MIO are defined as input pins and

ROM and RAM are the output pins for connection to the pins on

the memory devices. The

• architecture statement merely refers to the version (V1) of this

design.

• The equation for the design are placed in the begin block. Each

output pin has its own equation.

Combinatorial Programmable Logic Arrays

VHDL Language

• The keyword not is used for logical inversion and the keyword

and is used for the logical and operation.

• In this case the ROM equation causes the ROM pin to become a

logic zero only when the

• A19, A18, A17, and MIO are all logic zeros (00000H–1FFFFH).

• The RAM equation causes the RAM pin to become a logic zero

when A18 and A17 are all ones at the same time that MIO is a

logic zero. A19 is connected to the active high CE2 pin after

being inverted by the PLD.

• The RAM is selected for addresses 60000H–7FFFFH.

VHDL Language

See Figure 10–19 for the PLD realization of Example 10–5.

Combinatorial Programmable Logic Arrays

• Comments in VHDL programming begin --.• The library and use statements specify the standard IEEE

library using standard logic.• The entity statement names the VHDL module, in this case

DECODER_10_17.• The port statements define the in, out, and in-out pins

used in the equations for the logic expression, whichappears in the begin block. A19, A18, A17, and MIO aredefined as input pins and ROM and RAM are the outputpins for connection to the pins on the memory devices.

• The architecture statement merely refers to the version(V1) of this design.

Combinatorial Programmable Logic Arrays

• The equations for the design are placed in the begin block. Each output pin has its own equation. The keyword not is used for logical inversion and the keyword and is used for the logical and operation.

• The ROM equation causes the ROM pin to become a logiczero only when the A19, A18, A17, and MIO are all logiczeros (00000H–1FFFFH).

• The RAM equation causes the RAM pin to become a logiczero when A18 and A17 are all ones at the same time thatMIO is a logic zero.

• A19 is connected to the active high CE2 pin after beinginverted by the PLD.

• The RAM is selected for addresses 60000H–7FFFFH. SeeFigure 10–19 for the PLD realization of Example 10–5.

Sheet 2

1. Why are memory address decoders important?2. Modify the NAND gate decoder to select the memory for address

range DF800H–DFFFFH.3. 19. Modify the NAND gate decoder in to select the memory for

address range 40000H–407FFH.4. When the G1 input is high and both 𝐺2𝐴 and 𝐺2𝐵 are low, what

happens to the outputs of the 74HCT138 3-to-8 line decoder?5. Modify the circuit of Figure 10–15 to address memory range

70000H–7FFFFH.6. Modify the circuit of Figure 10–15 to address memory range

40000H–4FFFFH.7. What is VHDL?8. What are the five major keywords in VHDL for the five major logic

functions (AND, OR, NAND, NOR, and invert)?9. Equations are placed in what major block of a VHDL program?10. Modify the circuit of Figure 10–19 by rewriting the PLD program to

address memory at locations A0000H–BFFFFH for the ROM.

Sheet 2