Lecture5 Manufacturing

7/31/2019 Lecture5 Manufacturing

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Digital Integrated Circuits EE141Manufacturing ProcessManufacturing Process

CMOSManufacturing

Process


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CMOS Process


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A Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process


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Circuit Layout


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The Manufacturing Process

For a great tour through the process and its different steps, check

http://www.fullman.com/semiconductors/semiconductors.html

http://bwrc.eecs.berkeley.edu/Classes/IcBook

For a complete walk-through of the process (64 steps), check the

Book web-page


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oxidation

optical

mask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

Photo-Lithographic Process


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Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

Photoresist

SiO2

UV-light

Patterned

optical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO

2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch


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CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers


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CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substratewith p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse ofthe active area mask

p+

p-epiSiO

2

3SiN4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)


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SiO2

(d) After trench filling, CMPplanarization, and removal ofsacrificial nitride

(e) After n-well andVTp adjust implants

n

(f) After p-well andVTn adjust implants

p


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(g) After polysilicon depositionand etch

poly(silicon)

(h) Aftern+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition ofSiO2insulator and contact hole etch.

SiO2


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(j) After deposition andpatterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of vias,

deposition and patterning ofsecond layer of Al.

AlSiO

2


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Advanced Metalization


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Advanced Metalization


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Jan M. Rabaey

Design Rules


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3D Perspective

Polysilicon Aluminum


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Design Rules

l Interface between designer and process

engineer

l Guidelines for constructing process masks

l Unit dimension: Minimum line width

scalable design rules: lambda parameter

absolute dimensions (micron rules)


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CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


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Layers in 0.25 m CMOS process


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Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or

6

2Hole


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Transistor Layou t

1

2

5

3

Transistor


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Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


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Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


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CMOS Inverter Layou t

A A

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A

A A


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Layout Editor


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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.


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Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

Dimensionless layout entities

Only topology is important

Final layout generated by

compaction program

Lecture5 Manufacturing

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