lecture4

Computer Orgnization

Rabie A. RamadanLecture 4

Processing Unit Design

CPU Register Set

ALU

Control Unit (CU)

Simple Execution Cycle The next instruction to be executed, whose address is obtained from

the PC, is fetched from the memory and stored in the IR.

The instruction is decoded.

Operands are fetched from the memory and stored in CPU registers, if needed.

The instruction is executed.

Results are transferred from CPU registers to the memory, if needed.

Register Set Fast memory locations

• General Purpose • Can be assigned by the programmer

• Special Purpose• Used only for specific functions

• Ex. PC to hold the address of instruction to be executed

Register Set Memory Access Registers

• Memory Data Register (MDR)• Memory Address Register (MAR)

Instruction Fetching Registers• Program Counter (PC)• Instruction Register (IR)

• To hold the fetched instruction

Condition Registers/Flags • Maintain status information.

• special program status word (PSW) register.

Special-Purpose Address Registers Index Register

• The address of the operand is obtained by adding a constant to the content of a register.

Stack Pointer• Push and Pop operations• Implemented in 80x86

Stack

DATAPATH Data Section of the CPU Performs certain operations on the data Local Bus

• Holds the data internally between registers System Bus

• Holds external data • Move data between registers and memory

One-bus Organization Simplest organization Slow – needs 2 cycles for two operand operations Two registers are needed to save the I/p data

Two-bus Organization Faster than one-bus

• Two operands can be fetched at the same cycle One register (A) might be needed for the o/p data

Two-bus Organization One bus for the I/P (in-bus) One bus for the O/P Additional register is needed to save one of the operands

• In-bus moves the data into registers • Out-bus moves the data out of registers

Three-Bus Organization Two buses are used for moving the data out of the registers (out

buses) One-bus as destination – move the data to the registers

Fetch instructions The contents of the PC are loaded into the MAR.

The value in the PC is incremented. (This operation can be done in parallel with a memory access.)

As a result of a memory read operation, the instruction is loaded into the MDR.

The contents of the MDR are loaded into the IR.

Fetch Example – One-bus OrganizationReads the

instruction from the memory

IR takes the instruction

data

Group Activity Show the same fetch on three-bus

organizations?

Fetch Example – Three-bus Organization

t0 MAR PCt1 MDR Mem[MAR]; PC PC + 4t2 IR MDR