Lecture14

S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 14: Power Dissipation

S. Reda EN160 SP’08

Power and Energy

• Power is drawn from a voltage source attached to the VDD pin(s) of a chip.

• Instantaneous Power:

• Energy:

• Average Power:

( ) ( )DD DDP t i t V

0 0

( ) ( )T T

DD DDE P t dt i t V dt

avg

0

1( )

T

DD DD

EP i t V dt

T T

S. Reda EN160 SP’08

Dynamic power

• Dynamic power is required to charge and discharge load capacitances when transistors switch.

• One cycle involves a rising and falling output.

• On rising output, charge Q = CVDD is required

• On falling output, charge is dumped to GND

• This repeats Tfsw times

over an interval of T

Cfsw

iDD(t)

VDD

S. Reda EN160 SP’08

Dynamic power dissipation

Vin Vout

CL

Vdd

Energy delivered by the supply during input 1 0 transition:

Energy stored at the capacitor at the end of 1 0 transition:

dissipated in NMOS during discharge (input: 0 1)

load capacitance (gate + diffusion +

interconnects)

S. Reda EN160 SP’08

Capacitive dynamic power

If the gate is switched on and off f01 (switching factor) times per second, the power consumption is given by

For entire circuit

where αi is activity factor [0..0.5] in comparison to the clock frequency (which has switching factor of 1)

2dynamic DDP CV f

S. Reda EN160 SP’08

Short circuit current

• When transistors switch, both nMOS and pMOS networks may be momentarily ON at once

• Leads to a blip of “short circuit” current.• < 10% of dynamic power if rise/fall times are

comparable for input and output

S. Reda EN160 SP’08

Dynamic power breakup

Interconnect51%

Gate34%

Diffusion15%

Total dynamic Power

[source: Intel’03]

S. Reda EN160 SP’08

Static (leakage) power

• Static power is consumed even when chip is quiescent.– Leakage draws power from nominally OFF

devices

0 1gs t ds

T T

V V V

nv vds dsI I e e

S. Reda EN160 SP’08

Techniques for low-power design

• Reduce dynamic power– : clock gating, sleep mode– C: small transistors (esp. on clock), short wires

– VDD: lowest suitable voltage

– f: lowest suitable frequency

Enable

Clock

Clock Gating

2dynamic DDP CV f

only reduce supply voltage of non critical gates

I1I2

I3

I4

I5

I

6

O1

O2

criticalpath

S. Reda EN160 SP’08

Dynamic power reduction via dynamic VDD scaling

• Scaling down supply voltage – reduces dynamic power– reduces saturation current

increases delay reduce the frequency

Dynamic voltage scaling (DVS): Supply and voltage of the circuit should dynamic adjust according to the workload of criticality of the tasks running on the circuits

2dynamic DDP CV f

S. Reda EN160 SP’08

Leakage reduction via adjusting of Vth• Leakage depends exponentially on Vth. How to control Vth?

– Remember: Vth also controls your saturation current delay

1. Oxide thickness 2. Body Bias

I1I2

I3

I4

I5

I

6

O1

O2

criticalpath

Sol1: statically choose high Vt cells for non critical gates

Sol2: dynamically adjust the bias of the body• idle: increase Vt (e.g. by applying –ve body bias on NMOS)• Active: reduce Vt (e.g.: by applying +ve body bias on NMOS)

S. Reda EN160 SP’08

Leakage reduction via Cooling

Impact of temperature on leakage current

S. Reda EN160 SP’08

Summary

We are still in chapter 4:

Delay estimationPower estimation Interconnects and wire engineering Scaling theory