Lecture03 Ee620 Pll Overview

7/29/2019 Lecture03 Ee620 Pll Overview

http://slidepdf.com/reader/full/lecture03-ee620-pll-overview 1/20

Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory

Broadband Circuit DesignFall 2012

Lecture 3: PLL Overview & Analysis



Agenda

2

• PLL Overview & Applications

• PLL Linear Model

• Phase & Frequency Relationships

• PLL Transfer Functions



References

• M. Perrott, High Speed Communication Circuits and Systems Course , MIT Open Courseware

• Chapter 2 of Phase-Locked Loops, 3 rd Ed., R.Best, McGraw-Hill, 1997.

• Chapter 2 of Phaselock Techniques, F. Gardner,

John Wiley & Sons, 2005.

3



PLL Block Diagram

4

[Perrott]

• A phase-locked loop (PLL) is a negative feedback systemwhere an oscillator-generated signal is phase ANDfrequency locked to a reference signal



PLL Applications

• PLLs applications•Frequency synthesis

•Multiplying a 100MHz reference clock to 10GHz

•Skew cancellation• Phase aligning an internal clock to an I/O clock

•Clock recovery• Extract from incoming data stream the clock frequency and

optimum phase of high-speed sampling clocks

•Modulation/De-modulation•Wireless systems

• Spread-spectrum clocking

5



Forward Clock I/O Circuits

6

• TX PLL• TX Clock Distribution

• Replica TX Clock Driver

• Channel

• Forward Clock Amplifier

• RX Clock Distribution

• De-Skew Circuit

• DLL/PI

• Injection-Locked Oscillator



Embedded Clock I/O Circuits

7

• TX PLL

• TX Clock Distribution

• CDR • Per-channel PLL-based

• Dual-loop w/ Global PLL &

• Local DLL/PI

• Local Phase-Rotator PLLs

• Global PLL requires RXclock distribution toindividual channels



Linear PLL Model

8



Phase Detector

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output, thus to characterizephase detector gain, extract average output voltage (or current for

charge-pump PLLs) 9

φref

φfb

φe



Loop Filter

• Lowpass filter extracts average of phasedetector error pulses

10

I

I

VCO ControlVoltage

C1

R

C2

Charging

Discharging

VDD

VSS

F(s)



Voltage-Controlled Oscillator

• Time-domain phase relationship

11

VDDVDD/20

ω0 1

K VCO

( ) ( ) ( )tvK ttcVCOoutout

+=∆+= 00 ω ω ω ω

( ) ( ) ( )∫ ∫=∆= dtdt tvK tt cVCOoutoutω φ Laplace Domain Model

φout(t)



Loop Divider

• Time-domain model

12

( ) ( )tN

toutfb

ω ω 1

=

( ) ( ) ( )∫ == tN

tN

toutoutfb

φ ω φ 1

dt1

[Perrott]

φout(t) φfb(t)



Phase & Frequency Relationships

13

• Phase Step

( )( )

( ) ( )∫=

=

t

o

t

tdt

τ τ ω φ

ω φ

d

td

phaseof time)vschangeof (ratederivativefirsttheisFrequencyAngular

( ) ( ) ( )

( ) ( ) ( )( )ttu

tu

111

111

tsint

phaseandtfrequencyangularwithtsinusoidaConsider

φ ω

φ ω

+=

( ) ( )

( ) ( ) ( )( )

frequencyinchangeNo

sin 11

1

tuttu

tut

∆Φ+=

∆Φ=

ω

φ

∆Φ

[Best]




14

• Frequency Step ( )( ) ( ) ( )( )

( )

phaseinrampaproducesstepfrequencyA

where

sinsin

1

1001

01

tt

tttttu

t

ω φ

φ ω ω ω

ω ω ω

∆=

+=∆+=∆+=

[Best]

( ) tt ω φ ∆=1



( )

( ) ( )( )

( )

phaseinchangequadraticaproducesrampfrequencyA

2 where

sin2

sinsin

2

1

10

2

0

0

01

01

tt

ttttdtu

tt

t

•

••

•

∆=

+=

∆+=

∆+=

∆+=

∫

ω φ

φ ω ω

ω τ τ ω ω

ω ω ω


15

[Best]

• Frequency Ramp

0ω t•

∆+ ω ω 0

( ) 2

12

tt

•

∆=

ω φ



Understanding PLL Frequency Response

• Linear “small-signal” analysis is useful for understand PLL dynamics if

• PLL is locked (or near lock)

• Input phase deviation amplitude is small enough to maintain operation inlock range

• Frequency domain analysis can tell us how well the PLL tracks the inputphase as it changes at a certain frequency

• PLL transfer function is different depending on which point in the loopthe output is responding to

16

Input phase response VCO output response

[Fischette]



Open-Loop PLL Transfer Function

17

( ) ( )( )

( )s

sFK K

s

ssG VCOPD

e

out =Φ

Φ=

• Open-loop response generally decreases with frequency



Closed-Loop PLL Transfer Function

18

( ) ( )( )

( )( )

( )( )

N

sFK K s

sFK K

N

sGsG

s

ssHVCOPD

VCOPD

ref

out

+=

+=

ΦΦ=

1

( )

( ) ( )

( ) ( )N

sG

N

sG

N

sG

sN

sFK K l

sG

VCOPD

+=+

−−=∆

=−=∆

−=−=

=

101tDeterminanSystem

101tDeterminanPathForward

GainLoop

GainPathForward

1

1

• Low-pass response whose

overall order is set by F(s)



PLL Error Transfer Function

19

( )( )

( ) ( ) ( )N

sFK K

s

s

N

sGs

ssE

VCOPDref

e

+

=

+

=

Φ

Φ=

1

1

( ) ( )

( ) ( )N

sG

N

sG

N

sG

sN

sFK K l VCOPD

+=+

−−=∆

=−=∆

−=−=

=

101tDeterminanSystem

101tDeterminanPathForward

GainLoop

1GainPathForward

1

1

• Ideally, we want this to be zero

• Phase error generally increases withfrequency due to this high-pass response



Next Time

• PLL System Analysis•1st-Order PLLs

•2nd-Order PLLs

•

Type 1•Type 2

•PLL Frequency Response

•Noise Transfer Functions

•Tracking Response

20

Lecture03 Ee620 Pll Overview

Documents