ENG241 Digital Design Week #11 Memory Systems
Jun 22, 2015
ENG241 Digital Design
Week #11 Memory Systems
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Week #11 Topics
Random Access Memory Static RAM Array of RAM ICs Dynamic RAM Types of Dynamic RAM
Comparison Larger Wider Memories
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Resources
Chapter #9, Mano Sections 9.1 Memory Definitions 9.2 Random Access Memory 9.3 SRAM Integrated Circuits 9.4 Array of SRAM ICs 9.5 DRAM ICs 9.6 DRAM Types
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Memories in General
Computers have two types of memory (i) RAM and (ii) ROM
1. RAM stands for Random Access Memory
Static RAM usually used for Cache Dynamic RAM used for Main Memory
2. ROM stands for Read Only Memory ROM (or equivalent) used to store
permanent programs in a computer system (booting)
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Properties of Memory
1. Volatile: Memory contents disappears if power turned off
Typical computer RAM PDA (Personal Digital Assistant)
2. Nonvolatile: Contents of memory remain even if power turned off
ROM PROM, EEPROM Flash memories Magnetic memories like disk, tape
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Memory Classifications
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Memory Hierarchy
The design constraints on a computer memory can be summed up by three questions (i) How Much (ii) How Fast (iii) How expensive.
There is a tradeoff among the three key characteristics A variety of technologies are used to implement memory system Dilemma facing designer is clear large capacity, fast, low cost!! Solution Employ memory hierarchy
registers
Cache
Main Memory
Disk Cache
Magnetic Disk
Removable Media
Cost
Capacity
Access
Time
Static Ram
Static Ram
Dynamic Ram
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CPU
CacheController
CacheMemory
PCIController
DRAM
EISA/PCI BridgeController
Hard DriveController
VideoAdaptor
PC Card 1 PC Card 2
SCSIAdaptor
PC Card 3
Local CPU / Memory Bus
Peripheral Component Interconnect Bus
EISA PC BusSCSIBus
Co-processor
Memory
Static RAM
Dynamic RAM
Registers
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RAM versus ROM
RAM Read/write Volatile Faster access time Variants
SRAM DRAM
Application Variables Dynamic memory
allocation Heaps, stacks
ROM Read only Non-Volatile Slower Variants
PROM,EPROM EEPROM, FLASH
Application Programs Constants Codes, e.t.c
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Random Access Memories
So called because it takes the same amount of time to address any particular part
Types of RAM1. Static RAM (SRAM), Fast, expensive2. Dynamic RAM (DRAM), slow, cheap
How is memory accessed? Address Lines, Data Lines Control Signals (R/W, chip select, …)
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Simple View of RAM
Of some word size n=4,8,16 …. Some capacity 2k
k bits of address line, k=10,11,.. Maybe have read line Have a write line
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1K x 16 memory
Variety of sizes From 1-bit wide
Issue is no. of pins
Memory size specified in bytes 1K x 16 bit 2KB memory
10 address lines and 16 data lines
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Chip Select and R/W Lines
R/W Lines enable reading/writing Usually a chip select line is used. Why?
To enable RAM chip to be accessed.
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Memory: Writing
Sequence of steps Setup address lines Setup data lines Activate write line (maybe a pos edge)
The write cycle time is the maximum time from the application of the address to the completion of all internal memory operations required to store a word.
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Writing: Timing Waveforms
CPU operates at 50 MHz (20 ns) 4 clock cycles to perform a write
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Memory: Reading
Steps Setup address lines Activate read line Data available after specified amount
of time
Read cycle usually is shorter than write cycle.
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Reading
CPU operates at 50 MHz (20 ns) 65 ns required for a read cycle
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Static RAM: Internal Structure
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Simplify Modeling using Latch
Storage is modeled by an SR latch. Control logic One memory cell per bit
For select = 0, the stored content is held.
For select = 1, the stored content is determined by values on B and B’
The outputs are gated by the select line also.
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Bit Slice
Cells connected to form 1 bit position
Word Select gates one latch from address lines
Note it selects Reads also B (and B’) set by R/W, Data
In and BitSelect When R/W = 0 and
BitSelect = 1, then if Data in = 1 the latch will be set (i.e. a 1 is written)
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Bit Slice can Become Module
Basically bit slice is a one Dimensional array of memory
What type of hardware do we need to access one row at a time?
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16 X 1 RAM
4 address lines required to access 16 locations.
A Decoder is added to select the different words (each 1 bit wide).
For 16 words we need a 4-to-16 line Decoder
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Row/Column
Practical memories contains thousands of words!!
If RAM gets large, there is a huge decoder
Also run into chip layout issues How can we change the structure of
Memory to solve this problem? Rearrange the memory into “2D” i.e.,
matrix layout
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16 X 1 as 4 X 4 Array
Two decoders Row Column
Address just broken up
Not visible from outside
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16 X 1 as 4 X 4 Array
Employing 2 decoders instead of 1 row decoder is called coincident selection
Row Select and Column Select
A3A2A1A0=0000 will attempt to choose RAM cell 0.
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Change from 16x1 to 8 X 2 RAM
Minor change in logic
Try addressing 011 on board
Cells 6,7 are chosen for reading or writing.
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A Single Row Decoder
Imagine 32k x 8 = 256K bit memory 15 address lines are required.
One column layout would need 15-bit decoder with 32,768 outputs For a single decoder that would mean
32,800 gates This is not practical!
How about coincident selection?
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Coincident Selection
A 32K X 8 contains 256 Kbits A 15 bit address line is required. To make the number of rows and columns equal,
we take the square root of 256K, giving 512 = 29
A 9-to-512 decoder is required for the rows (9 address lines are fed to the Row Decoder).
For the columns 512/8 = 64 = 26
A 6-to-64 line decoder is required for the columns (6 address lines are fed to the Column Decoder).
Total number of gates is 512 + 64 = 608 (i.e. reducing the total gate count by more than 50!)
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SRAM Performance
Current SRAMs have cycle times in low nanoseconds (say 2.5ns)
Used as cache (typically on-chip or off-chip secondary cache)
Sizes up to 256 Mbit or so for fast chips
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Larger/Wider Memories
Made up from sets of chips Consider a 64K by 8 RAM
Note new symbols for sets of lines, 8 & 16 bits wide
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Larger: 256k x 8
Connect all output data lines together (tristate)
Connect all input data line together
16 lines of address to fetch a word in any DRAM chip
How to select the specific DRAM chip?
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Larger
Decoder for high-order 2 bits Selects chip Look at selection
logic Address ranges
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Wider – 64K X 16
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Dynamic RAM
Capacitor can hold charge Transistor acts as gate
No charge is a 0 Can close switch & add charge to
store a 1 Then open switch (disconnect)
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DRAM Cell
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Dynamic RAM (continued)
(a) (c)
(f) (g)
Select
BT
C
DRAM cell
To Pump
(b)
(d) (e)
Stored 1 Stored 0
Write 1 Write 0
Read 1 Read 0
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DRAM Characteristics
Destructive Read When cell read, charge removed Must be restored after a read
Refresh Also, there’s steady leakage Charge must be restored periodically
DRAM are dense (lots of cells) so there are many address lines. To reduce the physical size of DRAM we can
reduce the number of pins by applying the address lines serially in to parts (Row Address and then Column Address)
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How DRAM WorksA7A6A5A4
A3A2A1A0
A7A6A5A4A3A2A1A0
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DRAM Logical Diagram
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DRAM Read Signaling
Lower pin count by using same pins for row and column addresses
Delay until data
available
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DRAM Write Timing
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DRAM Refresh
Many strategies Logic on chip Refresh counter and
Refresh controller Refresh counter is
used to provide the address of the row of DRAM cell to be refreshed.
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CAS Before RAS
Set column address Apply CAS first (opposite of RW) Then toggle RAS enough times to cycle through row
addresses On-board refresh counter applies the row addresses
CAS
RAS
Col Add Row Add Row Add Row Add Row Add
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DRAM - Dynamic RAMFPM RAM - Fast page-mode RAMEDO RAM - Extended Data Out RAMBEDO RAM - Burst Extended-data-out RAMSDRAM - Synchronous Dynamic RAMDDRRAM - Double Data Rate RAM
DRAM Chip Types
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Page Mode DRAM DRAMs made to read & write blocks Example
Assert RAS, leave asserted Assert CAS multiple times to read sequence of
data Similar for writes
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DRAM Evolution
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Synchronous DRAM (SDRAM)
Double Data Rate SDRAM
Transfers data on both edges of the clock
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Memory Technologies
DRAM: Dynamic Random Access Memory upside: very dense (1 transistor per bit) and
inexpensive downside: requires refresh and often not the
fastest access times often used for main memories
SRAM: Static Random Access Memory upside: fast and no refresh required downside: not so dense and not so cheap often used for caches
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Summary
RAMs with different characteristics For different purposes
Static RAM Simple to use, small, expensive Fast, used for cache
Dynamic RAM Complex to interface, largest, cheap Needs periodic refresh
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Links
Ram Guides (not very technical) http://
arstechnica.com/paedia/storage.html
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Synchronous DRAM (SDRAM)
Has a clock Common type in PCs late-90s Multiple banks Pipelined
Start read in one bank after another Come back and read the resulting
values one after another
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Double Data RAM (DDRAM)
Double Data Rate SDRAM Transfers data on both edges of the clock
Currently popular Attempt to alleviate the pinout
problems
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Timing: 4M x 4 DRAM
Say need to refresh every 64ms Distributed refresh
Spread refresh out evenly over 64ms On a 4Mx4 DRAM 4096 rows Refresh every 64ms/4096=15.6 us Total time spent is 0.25ms, but spread
Burst refresh Same 0.25ms, but all at once May not be good in a computer system
Refresh takes low % of total time
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Hydraulic Analogy
StorageFull (1)
Empty (0)Pump fills tank to 1
value
Pump drains tank to 0 value
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Reading
Tank had a 1 value – raises
water level
Outside water begins at
intermediate level (black wavy line)
Tank had a 0 value – lowers
water level
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Static vs. Dynamic RAM
SRAM vs. DRAM DRAM stores charge in capacitor
Disappears over short period of time Must be refreshed
SRAM easier to use Faster More expensive per bit Smaller sizes
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DRAM Performance Specs
Important DRAM Performance Considerations Random access time: time required to read any
random single cell Fast Page Cycle time: time required for page mode
access read/write to memory location on the most recentlyaccessed page (no need to repeat RAS in this case)
Extended Data Out (EDO): allows setup of next address while current data access is maintained
SDRAM Burst Mode: Synchronous DRAMs use a selfincrementing counter and a mode register to determine the column address sequence after the first memory location accessed on a page effective for applications that usually require streams of data from one or more pages on the DRAM
Required refresh rate: minimum rate of refreshes
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RAMBUS DRAM (RDRAM)
Another attempt to alleviate pinout limits
Many (16-32) banks per chip Made to be read/written in packets Up to 400MHz bus speeds
But DDR doing very well also
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Burst Mode
During initialization you specify length of data transfer (the burst length)
During use, issue RAS, CAS, then you get a burst of data
Some DRAMs have multiple banks Can overlap opening another bank with
reading burst from current bank
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Read with Autoprecharge
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Bidirectional Lines
Many chips have one set of data pins Used as input for write As output for read Tri-state Makes sense because don’t need both
at once