Lecture No. 16

Lecture No. 16

Vishal Jethva

Digital Logic & Design

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Carry Propagation Delay between 4-bit ALU units

ALU2 ALU1 ALU0ALU3

Cin0Cin4Cin8Cin12

Cout4Cout8Cout12Cout16

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Carry Propagation Delay eliminated by using Group Carry

ALU2 ALU1 ALU0ALU3

Cin0Cin4Cin8Cin12

Look-AheadCarry Generator

P0P1P2P3 G0G1G2G3

C1C2C3 PG

P0G0P1G1P2G2P3G3

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16-bit ALU

S0S0

S1S1S2 S2

Cin

GP P0

74X381

A2A2

B2B2A3 A3B3 B3

ALU0

A0A0

B0B0A1 A1B1 B1

F0F1F2F3

F0F1F2F3

S0S0

S1S1S2 S2

Cin

GP P1

74X381

A2A6

B2B6A7 A3B7 B3

ALU1

A0A4

B0B4A5 A1B5 B1

F0F1F2F3

F4F5F6F7

S0S0

S1S1S2 S2

Cin

GP P2

74X381

A2A10

B2B10A11 A3B11 B3

ALU2

A0A8

B0B8A9 A1B9 B1

F0F1F2F3

F8F9F10F11

S0S0

S1S1S2 S2

Cin

GP P3

74X381

A2A14

B2B14A15 A3B15 B3

ALU3

A0A12

B0B12A13 A1B13 B1

F0F1F2F3

F12F13F14F15

G0P0G1P1

GP 6

74X182

G2P2G3P3

C1C2C3

C8C12

C0

A(0-15)B(0-15)

S(0-2)C0

F(0-15)

C4

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Parallel Comparators

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Implementation of A>B

A0A>B

A1

B0

B1

00101011)( BAABBABABA

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Implementation of A=B

A1

A=B

A0

B1

B0

0101010101010101)( BBAABBAABBAABBAABA

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Implementation of A<B

A0A<B

A1

B0

B1

01000111)( BBABAABABA

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Comparison of numbers by Cascaded 4-bit Comparator

A B Comparator M Comparator L

1101 0111 A>B

0110 1011 A<B

0011 0010 A=B A>B

0100 0101 A=B A<B

1001 1001 A=B A=B

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Implementation of 4-bit Comparator by Cascading two 2-bit Comparators

2-bitComparator

M

A3

A2

B3

B2

A>B

A<B

A=B

2-bitComparator

L

A1

A1

B0

B0

A>B

A<B

A=B

A>B

A<B

A=B

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Iterative Circuit Implementation of A=B function

Module 1

Module 0A0

B0

A1

B1

1

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Iterative Circuit Implementation of A>B function

Module 0

A0

B0

A1

B1

0

Module 1

A>B

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12-bit Comparator

A<B in

A=B in

A>B in

A<B out

A=B out

A>B out74X85

A2A6

B2B6

A7A3

B7B3

Comparator2

A0A4

B0B4

A5A1

B5B1

A<B in

A=B in

A>B in

A<B out

A=B out

A>B out74X85

A2A10

B2B10

A11A3

B11B3

Comparator3

A0A8

B0B8

A9A1

B9B1

A<B in

A=B in

A>B in

A<B out

A=B out

A>B out74X85

A2A2

B2B2

A3A3

B3B3

Comparator1

A0A0

B0B0

A1A1

B1B1

A(0-11)

B(0-11)

0

0

+5v

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Electronic Door Lock

A

CD

B1

Lock

Un-Lock

1

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Function Table of a 2-to-4 Binary Decoder

Input Output

I1 I0 O0 O1 O2 O3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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2-to-4 Decoder

I0

I1

O0

O1

O2

O3

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Function Table of 74LS139, 2-to-4 Decoder

G3Y2Y1Y0Y Input Output

B A

1 X X 1 1 1 1

0 0 0 1 1 1 0

0 0 1 1 1 0 1

0 1 0 1 0 1 1

0 1 1 0 1 1 1

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74LS139, 2-to-4 Decoder

B

A

Y0

Y1

Y2

Y3

G

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Decoders

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