Lecture 9: Combinational Circuitskmram/1192-2192/lectures/CombinationalCircuits.pdf · 8: Combinational Circuits CMOS VLSI Design Slide 28 HI- and LO-Skew q Def: Logical effort of

Introduction to CMOS VLSI

Design

Lecture 9: Combinational Circuits

David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan

University of Pittsburgh

CMOS VLSI Design 8: Combinational Circuits Slide 2

Outline q  Bubble Pushing q  Compound Gates q  Logical Effort Example q  Input Ordering q  Asymmetric Gates q  Skewed Gates q  Best P/N ratio


Example 1 module mux(input s, d0, d1,

output y); assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates.


Example 1 module mux(input s, d0, d1,

output y); assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0S

D1S

Y


Example 2 2) Sketch a design using NAND, NOR, and NOT gates.

Assume ~S is available.


Example 2 2) Sketch a design using NAND, NOR, and NOT gates.

Assume ~S is available.

Y

D0S

D1S


Bubble Pushing q  Start with network of AND / OR gates q  Convert to NAND / NOR + inverters q  Push bubbles around to simplify logic

–  Remember DeMorgan’s Law

Y Y

Y

D

Y

(a) (b)

(c) (d)


Example 3 3) Sketch a design using one compound gate and one

NOT gate. Assume ~S is available.


Example 3 3) Sketch a design using one compound gate and one

NOT gate. Assume ~S is available.

Y

D0SD1S


Compound Gates q  Logical Effort of compound gates

ABCD

Y

ABC Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA =

gB =

gC =

p =

gD =

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE Y

B

Y

B C

A

D

E

A

B

C

D E

gA =

gB =

gC =

gD =

2

2 2

22

6

6

6 6

3

p =

gE =

Complex AOI

Y A B C= +g Y A B C D= +g g ( )Y A B C D E= + +g gY A=


Compound Gates q  Logical Effort of compound gates

ABCD

Y

ABC Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA = 6/3

gB = 6/3

gC = 6/3

p = 12/3

gD = 6/3

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE Y

B

Y

B C

A

D

E

A

B

C

D E

gA = 5/3

gB = 8/3

gC = 8/3

gD = 8/3

2

2 2

22

6

6

6 6

3

p = 16/3

gE = 8/3

Complex AOI

Y A B C= +g Y A B C D= +g g ( )Y A B C D E= + +g gY A=


Example 4 q  The multiplexer has a maximum input capacitance of

16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.


Example 4 q  The multiplexer has a maximum input capacitance of

16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.

Y

D0S

D1S

Y

D0SD1S

H = 160 / 16 = 10 B = 1 N = 2


NAND Solution

Y

D0S

D1S


NAND Solution

Y

D0S

D1S

2 2 4(4 / 3) (4 / 3) 16 / 9

160 / 9ˆ 4.2

ˆ 12.4

N

PGF GBH

f F

D Nf P τ

= + =

= =

= =

= =

= + =

g


Compound Solution

Y

D0SD1S


Compound Solution 4 1 5(6 / 3) (1) 2

20ˆ 4.5

ˆ 14

N

PGF GBH

f F

D Nf P τ

= + =

= =

= =

= =

= + =

g Y

D0SD1S


Example 5 q  Annotate your designs with transistor sizes that

achieve this delay.

YY


Example 5 q  Annotate your designs with transistor sizes that

achieve this delay.

6

6 6

6

10

10Y

24

12

10

10

8

8

88

8

8

88

25

25

2525Y

16 16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36


Input Order q  Our parasitic delay model was too simple

–  Calculate parasitic delay for Y falling •  If A arrives latest? •  If B arrives latest?

6C

2C2

2

22

B

Ax

Y


Input Order q  Our parasitic delay model was too simple

–  Calculate parasitic delay for Y falling •  If A arrives latest? 2τ •  If B arrives latest? 2.33τ

6C

2C2

2

22

B

Ax

Y


Inner & Outer Inputs q  Outer input is closest to rail (B) q  Inner input is closest to output (A)

q  If input arrival time is known –  Connect latest input to inner terminal

2

2

22

B

A

Y


Asymmetric Gates q  Asymmetric gates favor one input over another q  Ex: suppose input A of a NAND gate is most critical

–  Use smaller transistor on A (less capacitance) –  Boost size of noncritical input –  So total resistance is same

q  gA = q  gB = q  gtotal = gA + gB = q  Asymmetric gate approaches g = 1 on critical input q  But total logical effort goes up

Areset

Y

4/3

2

reset

AY


Asymmetric Gates q  Asymmetric gates favor one input over another q  Ex: suppose input A of a NAND gate is most critical

–  Use smaller transistor on A (less capacitance) –  Boost size of noncritical input –  So total resistance is same

q  gA = 10/9 q  gB = 2 q  gtotal = gA + gB = 28/9 q  Asymmetric gate approaches g = 1 on critical input q  But total logical effort goes up

Areset

Y

4

4/3

22

reset

AY


Symmetric Gates q  Inputs can be made perfectly symmetric

A

B

Y2

1

1

2

1

1


Skewed Gates q  Skewed gates favor one edge over another q  Ex: suppose rising output of inverter is most critical

–  Downsize noncritical nMOS transistor

q  Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. –  gu = –  gd =

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skewinverter

unskewed inverter(equal rise resistance)

unskewed inverter(equal fall resistance)


Skewed Gates q  Skewed gates favor one edge over another q  Ex: suppose rising output of inverter is most critical

–  Downsize noncritical nMOS transistor

q  Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. –  gu = 2.5 / 3 = 5/6 –  gd = 2.5 / 1.5 = 5/3

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skewinverter

unskewed inverter(equal rise resistance)

unskewed inverter(equal fall resistance)


HI- and LO-Skew q  Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.

q  Skewed gates reduce size of noncritical transistors –  HI-skew gates favor rising output (small nMOS) –  LO-skew gates favor falling output (small pMOS)

q  Logical effort is smaller for favored direction q  But larger for the other direction


Catalog of Skewed Gates

1/2

2A Y

Inverter

B

AY

BA

NAND2 NOR2

HI-skew

LO-skew1

1A Y

B

AY

BA

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu =gd =gavg =

gu =gd =gavg =

gu =gd =gavg =

gu =gd =gavg =

Y

Y

1

2A Y

2

2

22

B

AY

BA

11

4

4

unskewedgu = 1gd = 1gavg = 1

gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y



1/2

2A Y

Inverter

1

1

22

B

AY

BA

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

BA

11

2

2

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu =gd =gavg =

gu =gd =gavg =

gu =gd =gavg =

gu =gd =gavg =

Y

Y

1

2A Y

2

2

22

B

AY

BA

11

4

4


gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y



1/2

2A Y

Inverter

1

1

22

B

AY

BA

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

BA

11

2

2

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu = 1gd = 2gavg = 3/2

gu = 2gd = 1gavg = 3/2

gu = 3/2gd = 3gavg = 9/4

gu = 2gd = 1gavg = 3/2

Y

Y

1

2A Y

2

2

22

B

AY

BA

11

4

4


gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y


Asymmetric Skew q  Combine asymmetric and skewed gates

–  Downsize noncritical transistor on unimportant input

–  Reduces parasitic delay for critical input

Areset

Y

4

4/3

21

reset

AY


Best P/N Ratio q  We have selected P/N ratio for unit rise and fall

resistance (µ = 2-3 for an inverter). q  Alternative: choose ratio for least average delay q  Ex: inverter

–  Delay driving identical inverter –  tpdf = –  tpdr = –  tpd = –  Differentiate tpd w.r.t. P –  Least delay for P =

1

PA


Best P/N Ratio q  We have selected P/N ratio for unit rise and fall

resistance (µ = 2-3 for an inverter). q  Alternative: choose ratio for least average delay q  Ex: inverter

–  Delay driving identical inverter –  tpdf = (P+1) –  tpdr = (P+1)(µ/P) –  tpd = (P+1)(1+µ/P)/2 = (P + 1 + µ + µ/P)/2 –  Differentiate tpd w.r.t. P –  Least delay for P =

1

PA

µ


P/N Ratios q  In general, best P/N ratio is sqrt of equal delay ratio.

–  Only improves average delay slightly for inverters –  But significantly decreases area and power

Inverter NAND2 NOR2

1

1.414A Y

2

2

22

B

AY

BA

11

2

2

fastestP/N ratio gu =

gd =gavg =

gu =gd =gavg =

gu =gd =gavg =

Y


P/N Ratios q  In general, best P/N ratio is sqrt of that giving equal

delay. –  Only improves average delay slightly for inverters –  But significantly decreases area and power

Inverter NAND2 NOR2

1

1.414A Y

2

2

22

B

AY

BA

11

2

2

fastestP/N ratio gu = 1.15

gd = 0.81gavg = 0.98

gu = 4/3gd = 4/3gavg = 4/3

gu = 2gd = 1gavg = 3/2

Y


Observations q  For speed:

–  NAND vs. NOR –  Many simple stages vs. fewer high fan-in stages –  Latest-arriving input

q  For area and power: –  Many simple stages vs. fewer high fan-in stages

Lecture 9: Combinational Circuitskmram/1192-2192/lectures/CombinationalCircuits.pdf · 8: Combinational Circuits CMOS VLSI Design Slide 28 HI- and LO-Skew q Def: Logical effort of

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