EE241 1 UC Berkeley EE241 J. Rabaey, B. Nikoli EE241 - Spring 2003 Advanced Digital Integrated Circuits Lecture 6 MOS Logic Styles UC Berkeley EE241 J. Rabaey, B. Nikoli Reading Chapter 7 in the text by K. Bernstein Background material from Rabaey References » [Rabaey 03] J.M. Rabaey “Digital Integrated Circuits: A Design Perspective,” Prentice Hall 2003. » [Bernstein 98] K. Bernstein et al, “High-Speed CMOS Design Styles,” Kluwer 1998. » [Oklobdzija99] V.G. Oklobdzija, “High- Performance Systems: Circuits and Logic,” IEEE Press 1999.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
EE241
1
UC Berkeley EE241 J. Rabaey, B. Nikolić
EE241 - Spring 2003Advanced Digital Integrated Circuits
� Many styles: don’t try to remember thenames – remember the principles
UC Berkeley EE241 J. Rabaey, B. Nikolić
CMOS Logic Styles
PUN
PDN
ABC
OUT
VDD
GND
ABC
Complementary
robustscales
large and slow
LOGICNETWORK
ABC
OUT
Pass Transistor Logic
simple and fastnot always very efficientversatile
EE241
3
UC Berkeley EE241 J. Rabaey, B. Nikolić
CMOS Logic Styles
LOAD
ABC PDN
OUT
GND
GND
VDD
Ratioed Logic
small & faststatic power
RPDN <<RLOAD
VDD
PDN
φ
In1In2In3
Out
φ
CL
Dynamic Logic
Small & fastest!Noise issuesScales?
UC Berkeley EE241 J. Rabaey, B. Nikolić
Static CMOS
VDD
VSS
PUN
PDN
In1
In2
In3
F = G
In1
In2
In3
PMOS Only
NMOS Only
Complementary CMOS
EE241
4
UC Berkeley EE241 J. Rabaey, B. Nikolić
Complementary CMOS� Very robust, full swing, high noise margins
» But … high noise generation
� Fast to design, can synthesize� Implements all logic functions� No static power� Among other properties:
» Different pull-up and pull-down delays» Delay dependence on history» Crowbar current» Input capacitance consists of both P and N» Fast NAND, NOR, slow MUX, XOR
» No dynamic nodes – good noise immunity» High static performance (monotonic)» No data dependent delay (worst case gets better)» No false transitions (monotonic)» Smaller clock load than dynamic
� Disadvantages» Width of reset wave limits logic depth and clock
speed» Restricted connectivity» Complex clocking
UC Berkeley EE241 J. Rabaey, B. Nikolić
PS-CMOS
Evaluation and reset waves: reset is 1.5x slower
EE241
9
UC Berkeley EE241 J. Rabaey, B. Nikolić
Skewing Gates� Different rising and falling delays
2W
2W
4W
W
Good for H-to-L transition Good for L-to-H transition