Lecture 5. Sequential Logic 2 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research.

Lecture 5. Sequential Logic 2

Prof. Taeweon SuhComputer Science Education

Korea University

2010 R&E Computer System Education & Research

Korea Univ

Clock Oscillators

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Clock Oscillators in Digital Systems

• Virtually all digital systems are essentially operating synchronous to the clock

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Where are Clock Oscillators?

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Clock in Digital Circuit

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D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

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Synchronous Sequential Logic

• Output of sequential logic is determined not only by current inputs but also by state stored in registers

• When sequential logic is working (updated) at the event (e.g., rising or falling edge) of clock source, we say that the circuit is synchronous to the clock In other words, if the state is updated at the event of clock

source, the circuit is synchronous sequential logic

• Virtually all digital systems are essentially synchronous to the clock Virtually all digital systems are synchronous sequential

logic

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Synchronous Sequential Logic

• Synchronous sequential logic composition Every circuit element is either a register or a

combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register

• Two common synchronous sequential circuits Finite state machines (FSMs) Pipelines

• will talk in depth about pipeline in computer architecture class next semester

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Finite State Machine (FSM)

• Finite state machines (FSMs) is composed of 2 components: registers and combinational logic Registers represent one of the finite number of

states• k registers can represent one of a finite number (2K)

of unique states• An initial state (in registers) is assigned based on

reset input at the (rising or falling) edge of clock The next state may change depending on the current

state as the next input comes in

Based on the current state (and input), output is determined via combinational logic

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FSM Quick Example

• Vending machine You are asked to design a vending machine

to sell cokes. • Suppose that a coke costs 300 won • The machine takes only 100 won coins

How would you design a logic with inputs and output?

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State 0

resetState 1

100 won

State 2

100 won

State 3 /

coke out

100 won

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Finite State Machine (FSM)

• FSM is composed of State register that

• Store the current state• Load the next state at the clock edge

Combinational logic that• Computes the next state based on current state and

input• Computes the outputs based on current state (and input)

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NextState

CurrentState

S’ S

CLK

CL

Next StateLogic

NextState

CL

OutputLogic

Outputs

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Finite State Machines (FSMs)

• Next state is determined by the current state and the inputs• Two types of FSMs differ in the output logic

Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and inputs

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CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

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Moore and Mealy

• Edward F. Moore, 1925 - 2003 Together with Mealy, developed automata theory, the

mathematical underpinnings of state machines, at Bell Labs.

Not to be confused with Intel founder Gordon Moore Published a seminal article, Gedanken-experiments on

Sequential Machines in 1956

• George H. Mealy Published “A Method of Synthesizing Sequential Circuits”

in 1955 Wrote the first Bell Labs operating system for the IBM 704

computer

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Finite State Machine Example

• Let’s design a simplified “traffic light controller” Traffic sensors: TA, TB

• Each sensor becomes TRUE if students are present • Each sensor becomes FALSE if the street is empty

Lights: LA, LB• Each light receives digital inputs specifying whether it should be

green, yellow, or red

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TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bravado

Blvd.

Dorms

Fields

DiningHall

Labs

TA

TB

LA

LB

CLK

Reset

TrafficLight

Controller

Inputs: clk, Reset, TA, TB

Outputs: LA, LB

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FSM State Transition Diagram

• Moore FSM Circles represent states Arcs represent transitions between states Outputs are labeled in each state

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S0LA:

greenLB: red

S1LA:

yellowLB: red

S2LA: red

LB: green

S3LA: red

LB: yellow

TAResetTA

TBTB

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bravado

Blvd.

Dorms

Fields

DiningHall

Labs

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FSM State Transition Table

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S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset Current State

InputsNext State

S TA TB S'

S0 0 X S1

S0 1 X S0

S1 XX S2

S2

S2

S3

X

X

X

0

1

X

S3

S2

S0

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FSM Encoded State Transition Table

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Current State Inputs

Next State

S1 S0 TA TB S'1 S'0

0 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

State

Encoding

S0 00

S1 01

S2 10

S3 11

S'1 = S1 S0

S'0 = S1S0TA + S1S0TB

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FSM Output Table

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Current State Outputs

S1 S0 LA1 LA0 LB1 LB0

Output Encoding

green 00

yellow 01

red 10

LA1 = S1

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

0

0

1

1

0

1

0

1

0 0 1 0

0 1 1 0

1 0 0 0

1 0 0 1

LA0 = S1S0

LB1 = S1

LB0 = S1S0

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FSM Schematic: State Register

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S1

S0

S'1

S'0

CLK

state register

Reset

r

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FSM Schematic: Next State Logic

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S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1 S0

r

S'1 = S1 S0

S'0 = S1S0TA + S1S0TB

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FSM Schematic: Output Logic

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S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r

LA1 = S1

LA0 = S1S0

LB1 = S1

LB0 = S1S0

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FSM Timing Diagram

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S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

CLK

Reset

TA

TB

S'1:0

S1:0

LA1:0

LB1:0

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S1 (01) S2 (10) S3 (11) S0 (00)

t (sec)

??

??

S0 (00)

S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??

??

0 5 10 15 20 25 30 35 40 45

Green (00)

Red (10)

S0 (00)

Yellow (01) Red (10) Green (00)

Green (00) Red (10)Yellow (01)

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FSM State Encoding

• In the previous example, the state and output encodings were selected arbitrarily Different choice would have resulted in a different circuit

• Commonly used encoding methods Binary encoding

• Each state is represented as a binary number For example, to represent four states, we need 2 bits (00, 01,

10, 11) One-hot encoding

• A separate bit is used for each state• Only one bit is HIGH at once (one-hot)

For example, to represent four states, we need 4 bits (0001, 0010, 0100, 1000)

So, it requires more flip-flops• But, it often results in simpler next state and output logic

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Moore vs. Mealy FSM

• Two types of FSMs differ in the output logic Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and

the inputs

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CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

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Snail Example

• There is a snail The snail crawls down a paper tape with 1’s and 0’s

on it The snail smiles whenever the last four digits it has

crawled over are “1101”

• Design Moore and Mealy FSMs of the snail’s brain

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State Transition Diagrams

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Mealy FSM: arcs indicate input/output

Moore FSM: arcs indicate input

S00

reset

S10

1

0 0

S20

1

1

S30

0

0

S41

1

1

0

S0

reset

S1

1/0

0/0 0/0S2

1/0

1/0

S3

0/0

1/1

1 11 110 1101

(1101)

0/0

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Moore FSM State Transition Table

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Current State

Inputs Next State

S A S'

S0 0 S0

S0 1 S1

S1 0 S0

S1

S2

S2

1

0

1

S2

S3

S2

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S3

S3

S4

S4

0

1

0

1

S0

S4

S0

S2

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Moore FSM State Transition Table

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Current State

Inputs Next State

S2 S1 S0 AS'2

S'1

S'0

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 0 0

0 0 1 1 0 1 0

0 1 0 0 0 1 1

0 1 0 1 0 1 0

0 1 1 0 0 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 0

1 0 0 1 0 1 0

StateEncodin

g

S0 000

S1 001

S2 010

S3 011

S4 100

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S'2 = S1 S0 A

S'1 = S1 S0 A + S1 S0 + S2A

S'0 = S2 S1 S0 A + S1S0 A

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Moore FSM Output Table

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Current State Output

S2 S1 S0 Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

Y = S2

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S0

S1

S2

S3

S4

0

0

0

0

1

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Moore FSM Schematic

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S2

S1

S0

S'2

S'1

S'0

Y

CLK

Reset

A

S2

S1

S0

S'2 = S1 S0 A

S'1 = S1 S0 A + S1 S0 + S2A

S'0 = S2 S1 S0 A + S1S0 A

Y = S2

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Mealy FSM State Transition and Output Table

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Current State Input

Next State

Output

S1 S0 A S'1 S'0 Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 0

0 1 1 1 0 0

1 0 0 1 1 0

1 0 1 1 0 0

1 1 0 0 0 0

1 1 1 0 1 1

State Encoding

S0 00

S1 01

S2 10

S3 11

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSM

S'1 = S1 S0 + S1 S0 A

S'0 = S1 S0 A + S1S0 A + S1S0 A

Y = S1 S0 A

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Mealy FSM Schematic

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S'1

S'0

CLK

Reset

S1

S0

A

Y

S0S1

S'1 = S1 S0 + S1 S0 A

S'0 = S1 S0 A + S1S0 A + S1S0 A

Y = S1 S0 A

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Moore and Mealy Timing Diagram

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Mealy Machine

Moore Machine

CLK

Reset

A

S

Y

S

Y

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S0 S3?? S1 S2 S4 S4S2 S3 S0

1 1 0 1 1 0 1 01

S2

S0 S3?? S1 S2 S1 S1S2 S3 S0S2

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSM

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

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Difference between Moore and Mealy FSMs

• A Moore machine typically has more states than a Mealy machine for a given problem

• A Mealy machine’s output rises a cycle sooner because it responds to the input rather than waiting for the state change When choosing your FSM design style, consider

when you want your outputs to respond

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FSM Design Procedure

• Identify inputs and outputs

• Sketch a state transition diagram

• Write a state transition table

• Select state encodings

• For a Moore machine Rewrite the state transition table with the selected state encodings Write the output table

• For a Mealy machine Rewrite the combined state transition table and output table with

the selected state encodings

• Write Boolean equations for the next state and output logic

• Sketch the circuit schematic34