Lecture 4a CMOS Fabrication, Layout and Simulationcourses.ece.ubc.ca/579/579.lect4a.fabsim.pdf · Lecture 4a CMOS Fabrication, Layout and Simulation R. Saleh ... directly from the

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Lecture 4a

CMOS Fabrication, Layout and Simulation

R. SalehDept. of ECE

University of British [email protected]

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Fabrication

Fabrication is the process used to create devices and wires.

– Transistors• ndiff, pdiff, wells, poly, transistors, threshold adjust implants

– Wires• contacts, metal1, via, metal2

Fabrication is pretty complex.

• Give a brief overview of the process, for background.• Want to understand origin of layout rules / process parameters

– The abstractions of the process for the designer (us).

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Making Chips

Wafers

Processing

Chemicals

ProcessedWafer

Chips

Masks

Layout

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Basic Fabrication Step

Two parts:

1) Transfer an image of the design to the wafer

2) Using that image as a guide, create the desired layer on silicon– diffusion (add impurities to the silicon)

– oxide (create an insulating layer)

– metal (create a wire layer)

Use the same basic mechanism (photolithography) to do step 1.Use three different methods to do step 2.

• Ion Implant - used for diffusion. Shoot impurities at the silicon.

• Deposition - used for oxide/metal. Usually from chemical vapor deposition (CVD)

• Grow - used for some oxides. Place silicon in oxidizing ambient.

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Integrated Circuit Fabrication

• Repeat:

– Create a layer on the wafer– Put a photo-sensitive material (resist) on top of the wafer– Optically project an image of the pattern you desire on the wafer

– Develop the resist– Use the resist as a mask to prevent the etch (or other process) from

reaching the layer under the resist, transferring the pattern to the layer

– Remove the resist

• Key point is that all the chips (die) on the wafer are processed in parallel, and for some chemical steps, many wafers are processed in parallel.

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Photolithography

• To transfer the pattern onto the wafer, one first needs to have an image to project. While this can be done using some scanning technology directly from the design database to the wafer (like generating a TV picture), it is usually done using a two step process:– First a glass plate with a image of the pattern etched in chrome is generated

from the design database. This glass plate is called a mask, and serves the same function of a negative in photography.

– This image is optically projected onto wafer using a “projection-aligner” which is very much like an enlarger in photography. It projects the image of the mask onto the silicon wafer.

• This two step process is used since scanning data serially is anexpensive step since it takes a long time on an expensive machine. By generating a mask which can print on a large number of wafers, the cost per wafer can be made small. (But implies that you want lots of parts).

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Basic Processing

Step 1: Apply material to wafer

Step 2: Spin on a photoresistive

material

Step 3: Pattern photoresist with

UV light through glass mask

Step 4: Apply specific processing step

such as etch, implant, oxidation, …after

removing soluble photoresist

Step 5: Wash off resist

material to be patterned

wafer

photoresist

glass maskUV light

soluble photoresist

etch away unwanted

material

patterned material

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n-well

gate oxide gate oxide

Cross-sectional View Plan View

polysilicon gate polysilicon gate

STIp-well

STISTI

Making Transistors

Apply threshold adjust implant

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polycide

n+ implant p+ implant

salicide

Making Transistors (cont’d)

Cross-sectional View Plan View

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Final Transistor Structure

n+ n+

STI p-well

p+ p+

STIn-wellSTI

common substrate

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Structure of NMOS Device

n+ n+

– VGS +

+ VDS –

STI STI

p

SpacersSelf-aligned

silicide = salicide

Polycide

Lightly-dopeddrain

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Fabrication Information

• Now that we know what fabrication is trying to do, how do we tell them precisely what to build?

• We don’t care about the real details of the fab, but we have to define the patterning of the layers (that meet their rules) to specify our design.

• Sometimes knowing more about the fab details is useful when you need to debug a part.

“tapeout”

Design

House

Foundry

(Fab)Design Rules

(layout)

Process Parameters

(simulation)

Layout(Mask Set)

GDS-II

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Layout Design Rule Examples

3λ3λ

3λ3λ

3λ

min. width rule

poly overlap of field 2λ

poly to diffusion

spacing 2λ

Resolution

Alignment

min. poly width 2λ

min. spacing

min. contact overlap λ

min. contact spacing to

gate 2λ

min. contact size 2λx2λ

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Transistor Layout Information

W

NMOS

G B

D

S

YD

L

ZYS

D

S

G

AD=YD x W

AS=Ys x W

PS= W

PD= W

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Circuit Simulation with SPICE

• For deep submicron devices, we must have an elaborate set of device models in SPICE to handle realistic situations when the chip is fabricated

• To address these issues, we will:

• Briefly review the most important issues

• Device modeling history

• Binning of device sizes

• Process variations

• Temperature variations

• Voltage variations

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MOSFET Modeling… 2 basic approaches

Physical parameters make physical sense; mostly extracted from process (tox, Leff, etc.) ; usually few params

Empirical curves match measured devices well parameters are difficult to understand, and there are lots parameters extracted from carefully measured devices

Reality is always a compromise between the two.***WARNING***

Empirical models can break in unpredictable ways if pushed beyond their characterization space. (but we need them since physics can only help us model to the limits of our knowledge)

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Brief history of Spice MOS models

• First generation• Hspice Level 1, 2, 3 • “physical” analytical models with geometry in model

equations• Holding onto hand-calculation...

• Second generation• Hspice level 13 (Bsim), 28 (“MetaMOS”), 39(Bsim2)• Shift in emphasis to circuit simulation with lots of

mathematical conditioning• Quality of outcome is highly dependent on parameter

extraction methodology• Good luck with hand-calculation• => BUT served industry well for over 12 years!

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Spice MOS models... the present

• Second generation models fell apart somewhere between 0.8m and 0.5m

• There is also a new need: low-voltage design

• Third generation: Hspice level 49 (Bsim3v3), 55 (EKV)

Bsim3 intent was return to simplicity... but... now Bsim3v3 > 100 parameters!

– Vendors have now figured out how to reliably build Bsim3v3 models

– You will be using a Bsim3v3 model (or BSIM4 in the future)

EKV model developed by EPFL in Switzerland... has promise

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Checking out your models

LinearGenerate IV Characteristics

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Checking out your models

• Try out multiple W/L’s and compare against measure data

• Try out NMOS and PMOS devices

• Check out Ids vs. Vgs to estimate VT

• Try different temperature ranges

• Check out Ids vs. Vgs

• Check out Ids vs. Vbs

• Check out VT vs. L

• Check out VT vs. W• Run simple timing experiments: compute Req, Cg, Cj, etc.

• For analog circuits, need to plot gm, gds, gmbs

• etc...

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Ids vs. Vgs (NMOS)

Leakage

Subthreshold

Active

Log IDS

VGS

• Plot log(Ids) vs. Vgs• Examine two regions

•saturation•subthreshold

• Leakage currents flow when device is completely off

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Binning approach to Modeling

• May need to bin space of models & stay inside covered space

Beware of non-physical behavior beyond boundaries! Some model sets were really just developed with minimum L’s rather than all possible L’s.

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Process Variations

• So far we have talked about transistors as if all transistors were the same

• Not true -- no two are exactly alike

• Parameters of a fabrication run are generally normally distributed - mean, standard deviation

Normal Distribution

0

0.2

0.4

0.6

0.8

1

-3 -2 -1 0 1 2 3

sigmaP

rob

Series1

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Circuit Parameters

• We need a way to identify and use the extreme points in parameter distributions (spec limits)

• Wan to stress circuits at these points

• Good place to test your design for robustness

• Define Process Corners:

• Select appropriate process parameters:

– Poly linewidth, nMOS Vt, pMOS Vt, Tox,

– metal width, oxide thickness

• Choose operating conditions

– Operating voltage (die voltage)

– Temp (0-100oC die temp)

P

V

T

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Process Corners

• Group parameters into transistor effects, and operating effects

• nMOS can be slow, typical, fast (S, T, F)

• pMOS can be slow, typical, fast (S, T, F)

• Temperature can be hot, typical, cold (S, T, F)

• Vdd can be high, typical, low (F, T, S)

• Label process corner as nMOS, pMOS, Temp, Vdd

TTTT = typical nMOS, typical pMOS, room temp, nominal supply

SSSS = slow nMOS, slow pMOS, hot temp, low supply

FSSS = fast nMOS, slow pMOS, hot temp, low supply

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Berkeley Predictive Models

• What parameters should we use for 65nn, 45nm, etc.?

• Folks at Berkeley have created a set of predictive models based on the ITRS projections and known trends for MOS devices

• They are kept on the BPM website and updated each year• We will be using these models for our simulations but we should

be aware that they have some shortcomings since they are predictive models.

• Always check out your models before using them!