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Lecture 3 Given [Compatibility Mode]

Apr 04, 2018

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  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

    1/23

    EL 511

    VLSI Design

    Instructor:

    Mazad S. Zaveri

    Faculty Block 4, Room 4206

    ma : maza _zaver a c .ac. nhttp://intranet.daiict.ac.in/~mazad_zaveri/

    EL 511 VLSI Design

    1

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    We will have a Quiz-1 today. (10 minutes)

    Homework-1 has been posted

    Gate-length 45 nm 32 nm =

    45*0.7 nm

    22 nm =

    45*0.7*0.7 nm

    Year 2009 2011 2013

    Generation x Next after x next after (next after x)

    EL 511 VLSI Design

    2

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    -1. A software has 500 lines of code. Of

    , ,

    100 lines can run only sequentially.

    a s e max mum spee -up max

    How many processors are needed to- . max

    2. What is the reason behind using high-k

    ga e-ox e n newer genera on o n eprocessors? Briefly explain, atleast two

    EL 511 VLSI Design

    3

    reasons.

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Conceptual Energy Band ModelElectron

    Ec

    Energy (E)

    Ev

    When silicon atoms come

    New electron energy band modelis created

    EL 511 VLSI Design

    4

    of the band model

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    E = Conduction Band

    Electron

    Energy (E)

    (starting) level Ev = Valence Band

    Ec

    Ev

    Conduction Band

    Band Gap

    en ng eve

    EG = Energy band gap

    Valence Band

    No Allowed states

    EG = Ec Ev

    E= Electron energy Unit is electron-volt (eV)

    EL 511 VLSI Design

    5

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    Types of Carriers- Electron & HoleWhen no bonds in the (lattice) or bondingmodel are broken, there are no carriers

    (In terms of energy band model) No carriers

    are present Valence band is completely filled

    When Si-Si bond breaks, the associated electron

    with electrons; and Conduction band is devoid

    of any electrons

    s ree o wan er n e a ce, e re ease

    electron is a carrier

    (In terms of energy band model) Excitation of

    carrier Electrons in conduction band are carriers

    When Si-Si bond breaks, in addition to electron

    release we have a missin bond void in the

    lattice). Nearby electrons may jump to fill this

    bond, creating a void in a new place. This void is

    called Hole

    EL 511 VLSI Design

    6

    (In terms of energy band model) Flow of void in

    the valence band, due to motion of electrons inthe valence band

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Material Classification based on Band Gap

    Insulator

    Bad conductor large energy band gap (EG)

    Semiconductor on uc s on y w en exc a on energy s prov e s G

    between the EG of metal and insulator Metal Good conductor Very narrow EG

    Electron-volt (eV) is an unit of

    energy equal to 1.6 x 10-19joules

    EL 511 VLSI Design

    7

    electron = 1.6 x 10-19 coulomb

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    Carrier numbers in Intrinsic Semiconductor

    Intrinsic semiconductor

    Extremely pure semiconductor

    Without any externally added impurity (dopants)

    n= number of electrons/cm3

    p= number of holes/cm

    In intrinsic semiconductor, Underequilibrium conditions

    Electron concentration = hole concentration

    n= = n

    For silicon (at room temp), ni = 1 x 1010 / cm3

    Holes and electrons are created only in pairs in intrinsic

    semiconductors

    EL 511 VLSI Design

    8

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    Doping manipulation of carrier numbers

    Doping Means the addition of controlled amounts of specific

    Why? Purpose of increasing either the electron or the hole

    concentration

    How? Replace some Si atoms with some dopant atoms

    Density of Si atoms in the Si crystal is 5 x 1022 / cm3

    ope sem con uc or s ca e x r ns csemiconductor

    To increase electron concentration

    Use Donors (Column V elements in periodic table) P (Phosphorus), As (Arsenic), Sb (Antimony)

    To increase hole concentration

    EL 511 VLSI Design

    9

    se ccep ors o umn e emen s n per o c a e B (Boron), Ga (Gallium), In (Indium)

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Donor (n-type material) Column V elements

    Have five valence electrons

    ,

    Si atom with a donor atom Four out of five electrons of the donor

    are use n orm ng our on s sotightly bound

    Fifth electron is loosely bound to

    Can be easily released at roomtemperature acts as a carrier

    If released from the donor site leaves

    P+

    behind a +ve charged donor ion Donor ion cannot move around in the

    crystal

    EL 511 VLSI Design

    10

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    Acceptor (p-type material) Column III elements

    Have 3 valence electrons

    Inside a silicon crystal, we replace Sia om w an accep or a om Three electrons of the acceptor will form three

    out of four bonds

    Electron from other nearby Si-Si bond, will be

    taken or accpeted and the incomplete bond

    will be completed ,

    will now have a missing bond, and will act as ahole

    The acceptor atom, accepted an electron so will

    Holes can be easily formed at room temperature acts as a carrier

    Acceptor ion cannot move around in the crystal -

    EL 511 VLSI Design

    11

    -

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    Donor and Acceptor

    Visualization in terms of energy band model Donor

    Weekly bound electrons are in a donor site

    Need only about 0.05 to 0.1eV to excite and jump to conduction band

    Donor

    A new electronic level (EA )is introduced in the forbidden gap, above Ev Electrons from valence band will excite/jump to this new level, creating holes

    Acce tor

    EL 511 VLSI Design

    12

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Fermi Function 1= erm unc on

    Specifies, under equilibrium

    ( ) /1 F

    E E kTe +

    ,

    an available state at an EnergyE will be occupied by an

    EF = Fermi Level or Fermi energy

    k= Boltzmann constant

    k= 8.617 x 10-5 eV/K

    T= Temperature in Kelvin (K)

    Indicates the relative

    concentration of electrons in

    EL 511 VLSI Design

    13

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    Semiconductor classification based on Fermi-level

    Intrinsic Fermi level Lies in the middle of ener band a

    Ei = (Ec + Ev )/2 and Ei = EF

    N-type semiconductor F > i

    P-type semiconductor E < E

    EL 511 VLSI Design

    14

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Carrier distributions

    N-type

    conduction band

    ( ) ( )c

    g E f E

    Intrinsic

    Distribution of holes

    (unfilled states) in valence

    band

    ( ) 1 ( )vg E f E

    P-type

    EL 511 VLSI Design

    15

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    n= number of electrons/cm3

    p= number of holes/cm3

    In intrinsic semiconductor n= p= ni

    Ei EF and np ni

    Use these equations to find the electron and holeconcen ra ons

    Valid only under equilibrium conditions of the semiconductor

    ( ) /F iE E kT

    in n e= ( ) /i FE E kTip n e

    =2

    inp n=

    EL 511 VLSI Design

    16

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    Intrinsic carrier concentration

    As temperature increases, thenumber of intrinsic carriers increase

    But for intrinsic carriers n= p= ni

    EL 511 VLSI Design

    17

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Charged entities in an extrinsic semiconductor

    Electron (n) and +ve charged donor ions (ND)

    Holes (p) and ve charged acceptor ions (NA)

    For an extrinsic semiconductor Assuming both type of dopants (donor and acceptors)

    Uniformly doped semiconductor

    Assuming equilibrium conditions No electric fields (built-in or external)

    This semiconductor is charge-neutral

    0D A

    p n N N+ + =

    Only some dopant atoms are ionized

    EL 511 VLSI Design

    18

    D A Valid forT> room temp

    When all dopant atoms are ionized

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    The eneral case

    Assume both types of dopants in the semiconductor For simplicity, assume that all dopant atoms are

    on ze room emp

    1/ 22

    2

    1/ 2

    2 2

    D A D Ai

    n n

    = + +

    2

    2 2

    i A D A Di

    n N N N N p nn

    = = + +

    EL 511 VLSI Design

    19

  • 7/31/2019 Lecture 3 Given [Compatibility Mode]

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    Electron-Hole concentration from doping

    concen ra ons

    D A

    D i

    N N

    N n

    2

    D

    inpN

    =

    use

    When

    A DN N Ap Nuse

    A iN n2

    i

    A

    nn

    N=

    When

    EL 511 VLSI Design

    20

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    Electron-Hole concentration from doping

    concen ra onsuse

    When n N N

    The above condition can also occur with increasing temperature.

    in the intrinsic carrier concentration. At sufficiently high temperatures niwill

    eventually equal and then exceed net doping concentration

    All semiconductors become intrinsic at sufficientl hi h tem eratures

    1/ 2

    useWheni A Dn N N

    2

    1/ 222

    2 2D A D A

    iN N N Nn n

    n N N N N

    = + +

    EL 511 VLSI Design

    21

    2 2i

    p nn

    = = + +

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    Position of Fermi-level from do in concentration

    useWhen DN =D A

    N NF i

    i

    n

    D iN n

    Whenln Ai F

    i

    E E kTn

    =

    A D

    A iN n

    EL 511 VLSI Design

    22

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    Temperature dependence of carrier concentrations

    Plot is for phosphorus ND = 1015/cm3

    ambient temperature, causes

    monotonic increase in the

    intrinsic carrier concentration. At

    sufficiently high temperatures ni

    will eventually equal and thenexceed net doping concentration

    All semiconductors become

    intrinsic at sufficiently high

    temperatures

    -123C 0C27C

    C = K - 273

    EL 511 VLSI Design

    23(= -273C)