Lecture 22

Lecture 22

OUTLINE

The MOSFET (cont’d) • Velocity saturation• Short channel effect• MOSFET scaling approaches

Reading: Pierret 19.1; Hu 7.1, 7.3

MOSFET Scaling• MOSFETs have been steadily miniaturized over time

– 1970s: ~ 10 m– Today: ~30 nm

• Reasons:– Improved circuit operating speed– Increased device density --> lower cost per function

EE130/230M Spring 2013 Lecture 22, Slide 2

Benefit of Transistor ScalingAs MOSFET lateral dimensions (e.g. channel length L) are reduced:

• IDsat increases decreased effective “R”

• gate and junction areas decrease decreased load “C” faster charging/discharging (i.e. d is decreased)


Velocity SaturationVelocity saturation limits IDsat in sub-micron MOSFETS

Simple model:

Esat is the electric field at velocity saturation:

sat

sat

vv

v

1

sat

sat

v2

for sat

for < sat

Siin holesfor cm/s 106

Siin sonfor electr cm/s 1086

6

satv


MOSFET I-V with Velocity Saturation

LV

VVm

VVCL

W

I

sat

DS

DSDSTGSeffoxe

D

1

2

L

VI channellong

I

sat

DS

DD

1

In the linear region:


Drain Saturation Voltage, VDsat

• If satL >> VGS-VT then the MOSFET is considered “long-channel”. This condition can be satisfied when– L is large, or – VGS is close to VT

LVV

m

V satTGSDsat 11

satsat

v2


Example: Drain Saturation VoltageQuestion: For VGS = 1.8 V, find VDsat for an NMOSFET with Toxe = 3 nm, VT = 0.25 V, and WT = 45 nm, if L = (a) 10 m, (b) 1 m, (c) 0.1 m (d) 0.05 m

Solution: From VGS , VT and Toxe, eff is 200 cm2V-1s-1. Esat= 2vsat / eff = 8 104 V/cm

m = 1 + 3Toxe/WT = 1.21

1

LVV

mV

satTGSDsat


(a) L = 10 m: VDsat= (1/1.3V + 1/80V)-1 = 1.3 V

(b) L = 1 m: VDsat= (1/1.3V + 1/8V)-1 = 1.1 V

(c) L = 0.1 m: VDsat= (1/1.3V + 1/.8V)-1 = 0.5 V

(d) L = 0.05 m: VDsat= (1/1.3V + 1/.4V)-1 = 0.3 V

11

LVV

mV

satTGSDsat


IDsat with Velocity SaturationSubstituting VDsat for VDS in the linear-region ID equation gives

For very short channel length:

• IDsat is proportional to VGS–VT rather than (VGS – VT)2

• IDsat is not dependent on LEE130/230M Spring 2013 Lecture 22, Slide 9

LmVV

I channellong

LmVV

VVCmLW

I

sat

TGS

Dsat

sat

TGS

TGSeffoxe

Dsat

11

22

mVVL TGSsat /

TGSoxesatTGSeffoxesatDsat VVCWvVVCW

I 2

Short- vs. Long-Channel NMOSFET

Short-channel NMOSFET:• IDsat is proportional to VGS-VTn rather than (VGS-VTn)2

• VDsat is lower than for long-channel MOSFET• Channel-length modulation is apparent

0 1 2 2.5Vds (V)

0.0

0.1

0.2

0.3

0.4

I ds

(mA

/m

)

L = 0.15 mV

gs = 2.5V

Vgs

= 2.0V

Vgs

= 1.5V

Vgs

= 1.0V

Vds (V)

I ds

(A

/m

)

L = 2.0 m Vgs = 2.5V

Vgs = 2.0V

Vgs = 1.5V

Vgs

= 1.0V

0.0

0.01

0.02

0.03

(a)

(b)

Vt = 0.7 V

Vt = 0.4 V

0 1 2 2.5Vds (V)

0.0

0.1

0.2

0.3

0.4

I ds

(mA

/m

)

L = 0.15 mV

gs = 2.5V

Vgs

= 2.0V

Vgs

= 1.5V

Vgs

= 1.0V

Vds (V)I d

s (

A/

m)

L = 2.0 m Vgs = 2.5V

Vgs = 2.0V

Vgs = 1.5V

Vgs

= 1.0V

0.0

0.01

0.02

0.03

(a)

(b)

Vt = 0.7 V

Vt = 0.4 V


Velocity Overshoot• When L is comparable to or less than the mean free

path, some of the electrons travel through the channel without experiencing a single scattering event

projectile-like motion (“ballistic transport”)

The average velocity of carriers exceeds vsat

e.g. 35% for L = 0.12 m NMOSFET

Effectively, vsat and sat increase when L is very small


The Short Channel Effect (SCE)

• |VT| decreases with L– Effect is exacerbated by high values of |VDS|

• This effect is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and bias condition

“VT roll-off”


Qualitative Explanation of SCE• Before an inversion layer forms beneath the gate, the

surface of the Si underneath the gate must be depleted (to a depth WT)

• The source & drain pn junctions assist in depleting the Si underneath the gate – Portions of the depletion charge in the channel region are

balanced by charge in S/D regions, rather than by charge on the gate

Less gate charge is required to invert the semiconductor surface (i.e. |VT| decreases)


depletionchargesupportedby gate(simplifiedanalysis) n+ n+

VG

p depletion region

Large L:

S D

Small L:

DS

Depletion charge supported by S/D

Depletion charge supported by S/D

The smaller L is, the greater the percentage of depletion charge balanced by the S/D pn junctions:

rj


First-Order Analysis of SCE

1

212

j

Tj r

WrLL

L

LL

21

WT


• The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor

• This is the factor by which the depletion charge Qdep is reduced from the ideal

• One can deduce from simple geometric analysis that

VT Roll-Off: First-Order Model

1

21)(

j

Tj

oxe

TATchannellongTT r

W

L

r

C

WqNVVV

Minimize VT by

• reducing Toxe

• reducing rj

• increasing NA

(trade-offs: degraded eff, m) MOSFET vertical dimensions should be scaled along with horizontal dimensions!


MOSFET Scaling: Constant-Field Approach

• MOSFET dimensions and the operating voltage (VDD) each are scaled by the same factor >1, so that the electric field remains unchanged.


Constant-Field Scaling Benefits

• Circuit speed improves by

• Power dissipation per function is reduced by 2


• Since VT cannot be scaled down aggressively, the operating voltage (VDD) has not been scaled down in proportion to the MOSFET channel length:


• Electric field intensity increases by a factor >1• Nbody must be scaled up by to suppress short-channel effects

• Reliability and power density are issues


MOSFET Scaling: Generalized Approach

Lecture 22

Documents

channel region

apparentee130230m spring

functionee130230m spring

vtee130230m spring

2ee130230m spring

smallee130230m spring

vee130230m spring

short channel length