Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved in CMOS digital computation Investigate the “complementary” nature of CMOS logic circuits Introduce CMOS NAND and NOR Determine the effective R and C for CMOS logic transitions
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Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.
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Lecture 21
Today we will Revisit the CMOS inverter, concentrating on logic 0
and logic 1 inputs Come up with an easy model for MOS transistors
involved in CMOS digital computation Investigate the “complementary” nature of CMOS
logic circuits Introduce CMOS NAND and NOR Determine the effective R and C for CMOS logic
transitions
D
S
VDD (Logic 1)
D
S
VOUT
VIN
VGS(n) = VIN
VGS(p) = VIN – VDD
VDS(n) = VOUT
+ VGS(n) -
+ V GS(p) -
+VDS(n)
_
CMOS Inverter
VDS(n)
(=VOUT)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve(written in terms of NMOS variables)
CMOS Analysis
VIN < VTH(n)
(e.g., logic 0)
As VIN goes up, VGS(n) gets biggerand VGS(p) gets less negative.
NMOS cutoff (open circuit)
PMOS triode (with VDS(p) = 0 V)
VDS(n)
(=VOUT)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve(written in terms of NMOS variables)
CMOS Analysis
VIN > VDD + VTH(p)
(e.g., logic 1)PMOS cutoff (open circuit)
NMOS triode (with VDS(n) = 0 V)
Model for Digital Computation
This leads us to a simpler model for transistors in CMOS circuits, when VIN is fully logic 0 or logic 1.
Transistor is not cutoff, but zero current flow of partner transistor causes VDS = 0 V.
Practice
VOUT
VDD
VIN
= VDD
VOUT
VDD
VIN
= 0 V
Use this model to find VOUT for the circuits below.
CMOS NANDVDD
A
B
S
S S
S
PMOS1
NMOS1
PMOS2
NMOS2
AB
More Practice
Verify the logical operation of the CMOS NAND circuit:
VDD
A= 0V
S
S S
SB
= 0V
VDD
A= 0V
S
S S
SB
= VDD
More Practice
Verify the logical operation of the CMOS NAND circuit:
VDD
A= VDD
S
S S
SB
= 0V
VDD
A= VDD
S
S S
SB
= VDD
CMOS Networks
Notice that VOUT gets connected to either VDD or ground by “active” (not cutoff) transistors.
We say that these active transistors are “pulling up” or “pulling down” the output.
NMOS transistors = pull-down network PMOS transistors = pull-up network These networks had better be complementary or
VOUT could be “floating”—or attached to both VDD and ground at the same time.
CMOS NAND vs. NOR
VDD
A
B
S
S S
S
AB
VDD
A
B
S
S S
S
CMOS NOR
A+B
CMOS NAND
Complementary Networks
If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.
The reverse is also true. Determining the logic function from CMOS circuit is
not hard: Look at the NMOS half. It will tell you when the
output is logic zero. Parallel transistors: “like or” Series transistors: “like and”
Resistance and Capacitance
The separation of charge by the oxide insulator creates a natural capacitance in the transistor from gate to source.
The silicon through which ID flows has a natural resistance. There are other sources of capacitance and resistance too.
n-typemetal metaloxide insulator
metal
p-type
metal
gate
drain
n-type+ + + + + +
___
_
_ _
h hh h
- +
_ _ _
h
VGS > VTH(n)
h hh h h
e e e ee
Gate Delay—The Full Picture
Suppose VIN abruptly changed from logic 0 to logic 1.
VOUT1 may not change quickly, since is attached to the gates of the next inverter.
These gates must collect/discharge electrons to change voltage. Each gate attached to the output contributes a capacitance.
D
S
VDD
D
S
VOUT1
D
S
VDD
D
S
VOUT2
VIN
e
e
Gate Delay—The Full Picture
Where will these electrons come from/go to? No charges can pass through the cutoff transistor. Charges will go through the pull-down/pull-up transistors to
ground. These transistors contribute resistance.
D
S
VDD
D
S
VOUT1
D
S
VDD
D
S
VOUT2
VIN
e
e
Computing Gate Delay
1. Determine the capacitance of each gate attached to the output. These combine in parallel. Higher fan-out = more capacitance.
2. Determine which transistors are pulling-up or pulling-down the output. Each contributes a resistance, and may need to be combined in series and/or parallel.
3. The C from 1) and R from 2) are the RC for the VOUT1 transition.
D
S
VDD
D
S
VOUT1
D
S
VDD
D
S
VOUT2
VIN
tp = (ln 2)RC
Example
Suppose we have the following circuit:
If A and B both transition from
logic 1 to logic 0 at t = 0,
find the voltage at the NAND
output, VOUT(t), for t ≥ 0.
A
B
Logic 0 = 0 V
Logic 1 = 1 V
NMOS resistance
Rn = 1 k
PMOS resistance
Rp = 2 k
Gate capacitance
CG = 50 pF
Answer
A and B both transition from 0 to 1. Since VOUT comes out of a NAND of A with B, VOUT transitions from 1 to 0.
VOUT(0) = 1 V VOUT,f = 0 V Since the output is transitioning from 1 to 0, it is being pulled
down. Both NMOS transistors in the NAND were previously cutoff, but are now active. The NMOS in the NAND are in series, so the resistances add:
R = 2 RN = 2 k The output in question feeds into 2 logic gate inputs (one
inverter, one NOR). Each CMOS input is attached to two transistors. Thus we have 2 x 2 = 4 gate capacitances to charge. All capacitances are in parallel, so they add: