EE241 1 UC Berkeley EE241 B. Nikolic EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 17 Adders and Multipliers UC Berkeley EE241 B. Nikolic Logarithmic Lookahead Adders A 7 F A 6 A 5 A 4 A 3 A 2 A 1 A0 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 F t p log 2 (N) t p N
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EE241
1
UC Berkeley EE241 B. Nikoli c
EE241 - Spring 2000Advanced Digital Integrated Circuits
Lecture 17
Adders and Multipliers
UC Berkeley EE241 B. Nikoli c
Logarithmic Lookahead Adders
A7
F
A6A5A4A3A2A1
A0
A0
A1
A2A3
A4
A5
A6
A7
F
tp∼ log2(N)
tp∼ N
EE241
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UC Berkeley EE241 B. Nikoli c
Tree Adders
lmG ppP ⋅=
lmmG gpgG ⋅+=
m – more significantl – less significant
Start from the input P, G, and continue up the tree2-bit groups, then 4-bit groups, …
l Combination:» 8-bit tapered pre-discharged Manchester
carry chains, with Cin = 0 and Cin = 1» 32-bit LSB carry-lookahead» 32-bit MSB conditional sum adder» Carry-select on most significant bits» Latch-based timing
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UC Berkeley EE241 B. Nikoli c
Z X·· Y× Zk2k
k 0=
M N 1–+
∑= =
Xi2i
i 0=
M 1–
∑
Yj2j
j 0=
N 1–
∑
=
XiYj2i j+
j 0=
N 1–
∑
i 0=
M 1–
∑=
X Xi 2i
i 0=
M 1–
∑=
Y Yj2j
j 0=
N 1–
∑=
with
Binary Multiplication
UC Berkeley EE241 B. Nikoli c
1 0 1 1
1 0 1 0 1 0
0 0 0 0 0 0
1 0 1 0 1 0
1 0 1 0 1 0
1 0 1 0 1 0
×
1 1 1 0 0 1 1 1 0
+
Partial Products
AND operation
Binary Multiplication
2N bits in the final sum
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UC Berkeley EE241 B. Nikoli c
HA FA FA HA
FA FA FA HA
FA FA FA HA
X0X1X2X3 Y1
X0X1X2X3 Y2
X0X1X2X3 Y3
Z1
Z2
Z3Z4Z5Z6
Z0
Z7
Array Multiplier
UC Berkeley EE241 B. Nikoli c
Shift-and-Add Multiplier
l Standard adder and shift-in the multiplicand
l Shift the result as well and addl N cyclesl Parallel adders add more hardware
(adders) instead.
EE241
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UC Berkeley EE241 B. Nikoli c
HA FA FA HA
HAFAFAFA
FAFA FA HA
Critical Path 1
Critical Path 2
Critical Path 1 & 2
MxN Array Multiplier— Critical Path
UC Berkeley EE241 B. Nikoli c
H A HA HA HA
FAFAFAHA
FAHA FA FA
FAHA FA HA
Vector Merging Adder
Carry-Save Multiplier
EE241
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UC Berkeley EE241 B. Nikoli c
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
C i
Co
S
Ci
P
P
P
P
P
Identical Delays for Carry and Sum
Adder Cells in Array Multiplier
UC Berkeley EE241 B. Nikoli c
SCSCSCSC
SCSCSCSC
SCSCSCSC
SC
SC
SC
SC
Z0
Z1
Z2
Z3Z4Z5Z6Z7
X0X1X2X3
Y1
Y2
Y3
Y0
Vector Merging Cell
HA Multiplier Cell
FA Multiplier Cell
X and Y signals are broadcastedthrough the complete array.( )
Multiplier Floorplan
EE241
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UC Berkeley EE241 B. Nikoli c
FA
FA
FA
FA
y0 y1 y2
y3
y4
y5
S
Ci-1
Ci-1
Ci-1
Ci
Ci
Ci
FA
y0 y1 y2
FA
y3 y4 y5
FA
FA
CC S
Ci-1
Ci-1
Ci-1
Ci
Ci
Ci
Wallace-Tree Multiplier
UC Berkeley EE241 B. Nikoli c
Wallace-Tree Multiplier
Wallace,Trans on Comp. 2/64
EE241
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UC Berkeley EE241 B. Nikoli c
Wallace-Tree Multiplier
UC Berkeley EE241 B. Nikoli c
Tree Multipliers
l Time is proportional to log Nl Wiring is complicatedl Different wire lengthsl Optional pipelining