Lecture 11 Signal Integrity for Nanometer Design Professor Lei He Professor Lei He EE 201A, Spring 2004 EE 201A, Spring 2004 http://eda.ee.ucla.edu http://eda.ee.ucla.edu
Apr 01, 2015
Lecture 11
Signal Integrity for Nanometer Design
Professor Lei HeProfessor Lei He
EE 201A, Spring 2004EE 201A, Spring 2004
http://eda.ee.ucla.eduhttp://eda.ee.ucla.edu
Outline Capacitive noiseCapacitive noise
Technology trendsTechnology trends Capacitance model and characteristicsCapacitance model and characteristics Layout optimizationLayout optimization
Inductive noise and layout optimizationInductive noise and layout optimization When inductance become importantWhen inductance become important Inductance model and characteristicsInductance model and characteristics Layout optimizationLayout optimization
Example: SINO algorithm for both Cx and Lx noiseExample: SINO algorithm for both Cx and Lx noise
Other noise sourcesOther noise sources
Interconnect Capacitance
Cf Ca
Cx
Significance of Coupling Capacitance
0
0.2
0.4
0.6
0.8
1
0.25 0.18 0.15 0.13 0.1 0.07
Technology Generation (um)
Cx/Ctotal
Min. Spacing
2x Min. Spacing
Delay Relative to Delay with no Crosstalk for different amounts of coupling
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
0.00 1.00 2.00 3.00 4.00 5.00
Relative Slope
Rel
ativ
e D
elay
50% coupling
100% coupling
10% coupling
Delay Variations Due to Coupling Capacitance
CxCx
Coupling Noise
0.000
0.050
0.100
0.150
0.200
0.250
0.300
0.350
250 180 150 100 70
Technology (nm)
No
ise
(%
Vd
d) a pair of in-phase aggressors
one aggressor
a pair of skewed
Coupling noise from two adjacent aggressors to the middle victim wire with 2x min. spacing. Rise time is 10% of project clock period.
•Capacitive coupling depends strongly on both spatial and temporal relations!
Solution to Capacitance Computation Accurate solution to small structureAccurate solution to small structure
Numerical method based on Maxwell’s equationsNumerical method based on Maxwell’s equations Raphael RC3, FastCap [Nabors-White, TCAD’91]Raphael RC3, FastCap [Nabors-White, TCAD’91]
Efficient solution to full chipEfficient solution to full chip Using tables or empirical formulas Using tables or empirical formulas
• 2.5-D capacitance model [Cong-He-Kahng-et al,DAC’97]2.5-D capacitance model [Cong-He-Kahng-et al,DAC’97] Capacitance is Capacitance is notnot simply simply A/dA/d
• A: areaA: area• d: distanced: distance
Characteristics of Coupling Capacitance Coupling capacitance virtually exists only between Coupling capacitance virtually exists only between
adjacent wires or crossing wiresadjacent wires or crossing wires
CxCx
CxCxCxCx
Capacitance can be pre-computed for a set of (localized) Capacitance can be pre-computed for a set of (localized) interconnect structuresinterconnect structures 2D or 2.5D capacitance model2D or 2.5D capacitance model
Noise avoidance technique:Noise avoidance technique: Shield insertionShield insertion
Shield is a wire directly connected to Vdd or GndShield is a wire directly connected to Vdd or Gnd
Layout to reduce impact of Cx
Vdd Gnds1 Gs2 s3 s4
Vdd Gnds1 s2 s3 s4
Coplanar parallel interconnect structures with pre-routed Vdd and Gnd
Timing Sensitivity Two nets are considered sensitive if a switching Two nets are considered sensitive if a switching
event on signal sevent on signal s11 happens during a sample time happens during a sample time
window for swindow for s22
time
aggressor
Sig
nal le
vels
(V)
victim1
VIH
Sampling window
error occurs
victim2
no error occurs
Noise avoidance techniques:Noise avoidance techniques: Net ordering (track assignment / net placement)Net ordering (track assignment / net placement)
Layout to reduce impact of Cx
Vdd Gnds4 s1 s3 s2
Vdd Gnds1 s2 s3 s4
Coplanar parallel interconnect structures with pre-routed Vdd and Gnd
Characteristics of Coupling Capacitance
Coupling capacitanceCoupling capacitance is highly sensitive to spacingis highly sensitive to spacing
0
0.05
0.1
0.15
0.2
0.25
0.3
50 100 150 200 250 300
cou[ingcapacitance(fF/um)
Proper wire sizing and spacing may limit the impact of Proper wire sizing and spacing may limit the impact of Cx by changing the ratio Cx/CtotalCx by changing the ratio Cx/Ctotal
E1 E1
spacingspacing
Spacing (nm)Spacing (nm)
Relation between Delay and Noise
T_max = T * ln (1/0.5-v) / ln 2T_max = T * ln (1/0.5-v) / ln 2 T_min = T * ln (1/(o.5+v) / ln 2T_min = T * ln (1/(o.5+v) / ln 2 Typical valuesTypical values
• VV T_max/TT_max/T T_min/TT_min/T
• 0.10.1 1.321.32 0.740.74
• 0.150.15 1.511.51 0.620.62
• 0.200.20 1.751.75 0.520.52
VIC
AGG
VOUT
VOUTw/o XTalk
AOUT
delay
Noise estimation and filtering
Rule of thumb:Rule of thumb:• Cx/C < thresholdCx/C < threshold
Devgan, ICCAD’97Devgan, ICCAD’97• V < (Rv + Rint / 2) * Cx / (1.25 Tr)V < (Rv + Rint / 2) * Cx / (1.25 Tr)• Tr: rising time for the aggressorTr: rising time for the aggressor
Vittal et al, TCAD’99 (more accurate)Vittal et al, TCAD’99 (more accurate)• V = (Rv + Rint / 2) * Cx / {0.63Tr + Ra (Ca + Cx) + Rv (Cv + Cx) + Rint V = (Rv + Rint / 2) * Cx / {0.63Tr + Ra (Ca + Cx) + Rv (Cv + Cx) + Rint
* Cx}* Cx}
To reduce Cx impactTo reduce Cx impact• Increase the driver size of victimIncrease the driver size of victim• Decrease the driver size of aggressorDecrease the driver size of aggressor• Or bufferingOr buffering• Need a global device size solution coupled with Time AnalysisNeed a global device size solution coupled with Time Analysis
Mini-Summary
Capacitive crosstalk is localizedCapacitive crosstalk is localized
Capacitive crosstalk affects both delay and signal Capacitive crosstalk affects both delay and signal integrityintegrity
Capacitive crosstalk can be minimized byCapacitive crosstalk can be minimized by• Spacing (and wire sizing)Spacing (and wire sizing)• Device sizingDevice sizing• Net orderingNet ordering• ShieldingShielding• Buffering Buffering
Outline Capacitive noiseCapacitive noise
Technology trendsTechnology trends Capacitance characteristicsCapacitance characteristics Layout optimizationLayout optimization
Inductive noise and layout optimizationInductive noise and layout optimization When inductance become importantWhen inductance become important Inductance characteristicsInductance characteristics Layout optimizationLayout optimization
Example: SINO algorithm for both Cx and Lx noiseExample: SINO algorithm for both Cx and Lx noise
Other noise sourcesOther noise sources
Is RC Model still Sufficient? Interconnect impedance is more than resistanceInterconnect impedance is more than resistance
• Z Z R +j R +jLL 1/t1/trr
On-chip inductance should be considered On-chip inductance should be considered • When When L becomes comparable to R as we move L becomes comparable to R as we move
towards Ghz+ designstowards Ghz+ designs
Candidates for On-Chip Inductance
Wide clock treesWide clock trees Skews are different under RLC and RC modelsSkews are different under RLC and RC models Neighboring signals are disturbed due to large clock Neighboring signals are disturbed due to large clock di/dt di/dt
noisenoise
Fast edge rate (~100ps) busesFast edge rate (~100ps) buses RC model RC model under-estimatesunder-estimates crosstalk crosstalk
P/G grids (and C4 bumps)P/G grids (and C4 bumps) di/dtdi/dt noise might overweight IR drop noise might overweight IR drop
Inductance Minimization
Reference plane Reference plane • wiring layers sandwiched between power planeswiring layers sandwiched between power planes
GND plane
VDD plane
Inductance Minimization Coplanar shieldsCoplanar shields
Bus signals
VDD shield
GND shield
Characteristics of Coupling in 18-Bit Bus
0.38V (29%)0.38V (29%)2 (b)2 (b)
0.17V (13%)0.17V (13%)5 (c)5 (c)
0.71V (55%)0.71V (55%)0 (a)0 (a)
Noise (% of Vdd)Noise (% of Vdd)# of Shields# of Shields
(a)
(b)
(c)
Lx coupling between non-adjacent nets is non-trivial Shielding is effective to reduce Lx coupling
Figure of Merit of Inductive Coupling
Inductive coupling coefficient defined asInductive coupling coefficient defined as
A formula-based Keff model has been A formula-based Keff model has been developeddeveloped High fidelity between formula and noise voltage High fidelity between formula and noise voltage
[He-Xu, 2000][He-Xu, 2000]
ji LLLijK /
Illustration of Keff Computation [XuHe,2000]
Keff(i,j) = (f(i) + g(j)) / 2f(i) = (Ni – gl)/(Nj – gl); g(j) = (gr – Nj)/(gr-Ni)
Inductance Minimization Staggered inverters/buffersStaggered inverters/buffers
Differential signalsDifferential signals Nets with opposite switching signals can be placed adjacent to each otherNets with opposite switching signals can be placed adjacent to each other
• Decrease Lx noise at the cost of a higher Cx noiseDecrease Lx noise at the cost of a higher Cx noise
Mutual capacitance
polarities
Mini-Summary
Inductive crosstalk is globalizedInductive crosstalk is globalized
Inductive crosstalk affects both delay and signal integrityInductive crosstalk affects both delay and signal integrity
Inductive crosstalk is not sensitive toInductive crosstalk is not sensitive to• Spacing (and wire sizing)Spacing (and wire sizing)• Net orderingNet ordering
Inductive crosstalk can be minimized byInductive crosstalk can be minimized by• ShieldingShielding• BufferingBuffering• Ground planeGround plane• Differential signalDifferential signal• Signal terminationSignal termination
Outline Capacitive noiseCapacitive noise
Technology trendsTechnology trends Capacitance model and characteristicsCapacitance model and characteristics Layout optimizationLayout optimization
Inductive noise and layout optimizationInductive noise and layout optimization When inductance become importantWhen inductance become important Inductance model and characteristicsInductance model and characteristics Layout optimizationLayout optimization
Example: SINO algorithm for both Cx and Lx noiseExample: SINO algorithm for both Cx and Lx noise
Other noise sourcesOther noise sources
Noise avoidance techniques:Noise avoidance techniques: Net ordering (track assignment / net placement)Net ordering (track assignment / net placement) Shield insertionShield insertion
Shield is a wire directly connected to Vdd or GndShield is a wire directly connected to Vdd or Gnd
SINO Problem [He-Lepak, ISPD2K]:
Simultaneous Shield Insertion and Net Ordering
Vdd Gnds4 Gs1 s3 s2
Vdd Gnds1 s2 s3 s4
Coplanar parallel interconnect structures with pre-routed Vdd and Gnd
SINO/NF Problem
Given: An initial placement PGiven: An initial placement P Find: A new placement P’ via simultaneous shield Find: A new placement P’ via simultaneous shield
insertion and net ordering such that:insertion and net ordering such that: P’ is capacitive noise freeP’ is capacitive noise free
• Sensitive nets are not adjacent to each otherSensitive nets are not adjacent to each other P’ is inductive noise freeP’ is inductive noise free
• Sensitive nets do not share a blockSensitive nets do not share a block P’ has minimal areaP’ has minimal area
Equivalent to one-shield-one-signalEquivalent to one-shield-one-signal When all nets are sensitive to one anotherWhen all nets are sensitive to one another
SINO/NB Problem
Given: An initial placement PGiven: An initial placement P Find: A new placement P’ via simultaneous shield Find: A new placement P’ via simultaneous shield
insertion and net ordering such that:insertion and net ordering such that: P’ is capacitive noise freeP’ is capacitive noise free All nets in P’ have inductive noise less than a given valueAll nets in P’ have inductive noise less than a given value P’ has minimal areaP’ has minimal area
Properties of SINO Problems
Theorem: The optimal SINO/NF problem is NP-Theorem: The optimal SINO/NF problem is NP-hardhard
Theorem: The optimal SINO/NB problem is Theorem: The optimal SINO/NB problem is NP-hardNP-hard
Theorem: The maximum clique in the Theorem: The maximum clique in the sensitivity graph is a lower bound on the number sensitivity graph is a lower bound on the number of blocks required for all SINO/NF solutionsof blocks required for all SINO/NF solutions
Sensitivity Graph for SINO Problem
Graph indicating which nets are sensitive to one-Graph indicating which nets are sensitive to one-another (vertices=nets, edges=nets are sensitive)another (vertices=nets, edges=nets are sensitive)
Sensitivity graph with clique size = 3
One maximal clique
Greedy Shield Insertion
Shield Insertion (SI)Shield Insertion (SI) Insert shield when a Cx or Lx violation occursInsert shield when a Cx or Lx violation occurs Results depend strongly on the initial placementResults depend strongly on the initial placement
Net Ordering + Shield Insertion (NO+SI)Net Ordering + Shield Insertion (NO+SI) First remove Cx coupling by net ordering, then First remove Cx coupling by net ordering, then
perform shield insertion for Lxperform shield insertion for Lx Results depend weakly on the initial placement Results depend weakly on the initial placement
Separated NO+SI—simultaneous algorithm works better
Graph Coloring SINO (GC)
Our implementation: Greedy-based GCOur implementation: Greedy-based GC Can solve with other GC methods as wellCan solve with other GC methods as well Main contributions of SINO-GC:Main contributions of SINO-GC:
Provide lower bound measurements for SINO/NFProvide lower bound measurements for SINO/NF Comparative reference pointComparative reference point
Simulated Annealing SINO (SA) Cost Function is a weighted sum of:Cost Function is a weighted sum of:
Number of Cx violationsNumber of Cx violations Number of Lx violationsNumber of Lx violations Inductance Violation Figure (quantizes level of inductive noise)Inductance Violation Figure (quantizes level of inductive noise) Area of PlacementArea of Placement
Random MovesRandom Moves Combine two random blocks in placement PCombine two random blocks in placement P Swap two (arbitrary) random s-wires in PSwap two (arbitrary) random s-wires in P Move a single random s-wire in PMove a single random s-wire in P Insert a shield wire at a random location in PInsert a shield wire at a random location in P
Quality of SINO/NB Solutions
SINO/NFSINO/NF SINO/NBSINO/NB
KKthreshthresh Graph Graph ColoringColoring
Greedy Greedy SISI
NO+SINO+SI GCGC SASA
Net Sensitivity Rate: 10%Net Sensitivity Rate: 10%
1.01.0 3.23.2
((2.02.0))
5.05.0 2.82.8 2.02.0 1.81.8
2.02.0 4.24.2 1.21.2 2.02.0 1.01.0
Net Sensitivity Rate: 30%Net Sensitivity Rate: 30%
1.01.0 6.06.0
((3.83.8))
13.213.2 4.44.4 4.24.2 3.03.0
2.02.0 13.213.2 2.82.8 3.83.8 2.02.0
Net Sensitivity Rate: 60%Net Sensitivity Rate: 60%
1.01.0 13.613.6
((8.28.2))
22.422.4 5.45.4 8.28.2 5.05.0
2.02.0 22.422.4 4.04.0 8.28.2 3.43.4
Max. clique size in the sensitivity graph
# of shields is fewer than lower bound for SINO/NFCPU time is much less than existing net ordering algorithms
Expand to Full-Chip Level
Shield estimationShield estimation Crosstalk Modeling (LSK model) @ chip levelCrosstalk Modeling (LSK model) @ chip level Global routing synthesisGlobal routing synthesis Post-routing refinement with optimal Post-routing refinement with optimal
crosstalk budgetingcrosstalk budgeting
Shielding Estimation
The number of shields for min-area SINO solution is:The number of shields for min-area SINO solution is: Linear with number of nets (Linear with number of nets (NNnsns))
Quadratic with sensitivities (Quadratic with sensitivities (SSii))
Linear with crosstalk bounds (Linear with crosstalk bounds (KKth,ith,i))
Holds for min-area SINO solutions Holds for min-area SINO solutions
Estimation can be used to guide routing synthesisEstimation can be used to guide routing synthesis
Shielding Estimation For known crosstalk bound (For known crosstalk bound (KKth,ith,i) but unknown sensitivity rate ) but unknown sensitivity rate SSii and unknown number of net and unknown number of net
NNnsns, the number of shields is, the number of shields is
To be used in global routing synthesisTo be used in global routing synthesis
For known For known SSii and and NNns ns but unknown but unknown KKth,ith,i
To be used in noise budgetingTo be used in noise budgeting
651
41
31
22
1
21 cNcScSNcScSNcN ns
N
ii
N
iins
N
ii
N
iinsss
nsnsnsns
nsN
iithss KN
1,
Shielding Estimation (Cont’d)
In most general case, the number of shields isIn most general case, the number of shields is
121
,11101
,9
18
11,27
16
11,5
1
24
1
2
1,23
1
22
1
2
1,1
1
111
111
dKN
dNdKd
SN
dSKN
dSdSKN
d
SN
dSKN
dSdSKN
dN
nsns
nsnsnsnsnsns
nsnsnsnsnsns
N
iith
nsns
N
iith
N
ii
ns
N
ii
N
iith
ns
N
ii
N
ii
N
iith
ns
N
ii
ns
N
ii
N
iith
ns
N
ii
N
ii
N
iith
nsss
Computation of LSK Value
For each sink, LSK value is For each sink, LSK value is
Sum over the path from source to sink lljj: length of the region : length of the region j j wherewhere net net ii is routed is routed
KKiijj: : sum of inductive coupling coefficients for net sum of inductive coupling coefficients for net ii in region in region jj
ji
jj Kl
Region H1Region H1
Region H3Region H3
Net iNet iRegion H2Region H2
Fidelity of LSK Model
For SINO solutions, higher LSK values For SINO solutions, higher LSK values
higher SPICE-computed noise using detailed RLC circuitshigher SPICE-computed noise using detailed RLC circuits
0
500
1000
1500
2000
2500
0 0.05 0.1 0.15 0.2 0.25
SPICE-computed noise voltage
LS
K v
alu
e
Converting LSK Value to Noise Voltage
Table buildingTable building Consider SINO solution of parallel interconnect Consider SINO solution of parallel interconnect
buses (i.e., two-pin nets)buses (i.e., two-pin nets) Compute and store both LSK Compute and store both LSK values and noise values and noise
voltages via SPICE simulationvoltages via SPICE simulation
Table lookup (either two-pin or multi-pin Table lookup (either two-pin or multi-pin nets)nets) Linear interpolation and extrapolationLinear interpolation and extrapolation
Verification of LSK Model
Errors less than 15% for SINO solutions to two-pin netsErrors less than 15% for SINO solutions to two-pin nets Errors less than 20% for SINO solutions to multi-pin netsErrors less than 20% for SINO solutions to multi-pin nets
0
0.05
0.1
0.15
0.2
0.25
0 0.05 0.1 0.15 0.2 0.25
LSK-model-computed noise voltage
SP
ICE
-co
mp
ute
d n
ois
e v
olt
ag
e -15%
+15%
GSINO Problem Formulation
GivenGiven Pin locations of each netPin locations of each net RLC crosstalk bound for each sinkRLC crosstalk bound for each sink
DecideDecide Rectilinear Steiner tree for each netRectilinear Steiner tree for each net SINO solution within each routing regionSINO solution within each routing region
Such thatSuch that RLC crosstalk constraint is satisfied for each sinkRLC crosstalk constraint is satisfied for each sink Wire length is minimizedWire length is minimized Chip area is minimizedChip area is minimized
Overall GSINO/LD Algorithm
GSINO is NP-hardGSINO is NP-hard Sub-problem SINO is NP-hardSub-problem SINO is NP-hard
High-quality solution via three-phase High-quality solution via three-phase GSINO/LD algorithmGSINO/LD algorithm Phase I: Global routing with linear distribution of Phase I: Global routing with linear distribution of
crosstalk boundscrosstalk bounds Phase II: SINO within each region Phase II: SINO within each region
• Developed in [He-Lepak, ISPD’00]Developed in [He-Lepak, ISPD’00] Phase III: post-routing refinement (RF)Phase III: post-routing refinement (RF)
Algorithm Phase I
Routing topology generationRouting topology generation L and Z shape routes within bounding box of all pinsL and Z shape routes within bounding box of all pins Leads to fixed path length from source to each sinkLeads to fixed path length from source to each sink
Crosstalk bound distributionCrosstalk bound distribution Linear distribution from source to each sink for Linear distribution from source to each sink for
fixed lengthfixed length More sophisticated solution presented later onMore sophisticated solution presented later on
Algorithm Phase I (Cont’d) Routing algorithm: Iterative deletion (ID) [Cong-Preas, Routing algorithm: Iterative deletion (ID) [Cong-Preas,
Integration’92]Integration’92] Start with net connection graph (completed graph)Start with net connection graph (completed graph) Iteratively delete the edge with the largest weight Iteratively delete the edge with the largest weight Until graph becomes a treeUntil graph becomes a tree
α * f (wire_length) + β * density (Ri) + γ * overflow (Ri)
Density = signal nets + estimated shields (via formula)Density = signal nets + estimated shields (via formula) Shielding area is reserved Shielding area is reserved Shielding area is minimized as sensitive nets are Shielding area is minimized as sensitive nets are
automatically distributed to different regionsautomatically distributed to different regions Alternative global routing algorithm may be appliedAlternative global routing algorithm may be applied
Algorithm Phase III
Phase III: post-SINO refinement (RF)Phase III: post-SINO refinement (RF) Eliminate remaining but limited RLC noise Eliminate remaining but limited RLC noise
violationsviolations• Start with most severe crosstalk-violating netStart with most severe crosstalk-violating net
• Decrease noise bound to allow one more shield in the least Decrease noise bound to allow one more shield in the least congested region using the formulacongested region using the formula
• Until no crosstalk violationsUntil no crosstalk violations
Reduce routing congestionReduce routing congestion• Start with most congested regionStart with most congested region
• Increase noise bound to remove one shield in the region Increase noise bound to remove one shield in the region using the formulausing the formula
• Until new SINO solution without crosstalk violationUntil new SINO solution without crosstalk violation
nsN
iithss KN
1,
Experiment Settings Comparison amongComparison among
ID+NOID+NO• ID: ID-based global routing without considering shielding ID: ID-based global routing without considering shielding
in the weight functionin the weight function• NO: net ordering to eliminate as much capacitive coupling NO: net ordering to eliminate as much capacitive coupling
as possibleas possible iSINO/LD = ID + SINO + RF (best alternative)iSINO/LD = ID + SINO + RF (best alternative) GSINO/LDGSINO/LD
ITRS 0.10um technologyITRS 0.10um technology
VddVdd 1.05V1.05V Load capacitanceLoad capacitance 60fF60fF
FrequencyFrequency 3GHz3GHz Wire widthWire width 1.01.0μμmm
Input rising timeInput rising time 33ps33ps Wire thicknessWire thickness 1.11.1μμmm
Driver resistanceDriver resistance 150150ΩΩ Wire spacingWire spacing 0.80.8μμmm
Benchmark Circuits
Large scale industrial benchmark circuits Large scale industrial benchmark circuits Placement done by DRAGON [Wang et al, ICCAD’2K]Placement done by DRAGON [Wang et al, ICCAD’2K] Uniform crosstalk constraints 0.15V (15% of Vdd)Uniform crosstalk constraints 0.15V (15% of Vdd)
Number Number of netsof nets
Number of Number of regionsregions
Number Number of pinsof pins
Region’s Region’s capacitycapacity
Regions Regions physical size physical size ((μμm * m * μμm)m)
ibm01ibm01 1305613056 64 * 64=409664 * 64=4096 4581545815 V:12 H:14V:12 H:14 25 * 3025 * 30
ibm02ibm02 1929119291 80 * 64=512080 * 64=5120 7903379033 V:22 H:34V:22 H:34 40 * 6540 * 65
ibm03ibm03 2610426104 80 * 64=512080 * 64=5120 8019380193 V:20 H:30V:20 H:30 40 * 6040 * 60
ibm04ibm04 3132831328 96 * 64=614496 * 64=6144 9475694756 V:20 H:32V:20 H:32 40 * 6040 * 60
ibm05ibm05 2964729647 128 * 64=8192128 * 64=8192 127509127509 V:42 H:63V:42 H:63 80 * 11580 * 115
ibm06ibm06 3439534395 128 * 64=8192128 * 64=8192 125880125880 V:20 H:33V:20 H:33 40 * 6040 * 60
Number of Crosstalk-violating Nets
Up to 25% of nets may have crosstalk violations in ID+NOUp to 25% of nets may have crosstalk violations in ID+NO No crosstalk violations for iSINO and GSINONo crosstalk violations for iSINO and GSINO
ID+NOID+NO iSINO-RFiSINO-RF iSINOiSINO GSINO-RFGSINO-RF GSINOGSINO
Sensitivity rate = 30%Sensitivity rate = 30%
ibm01ibm01 19821982 177177 00 7979 00
ibm02ibm02 33703370 321321 00 148148 00
ibm03ibm03 50855085 365365 00 196196 00
ibm04ibm04 53925392 545545 00 302302 00
ibm05ibm05 45284528 552552 00 209209 00
ibm06ibm06 49514951 398398 00 163163 00
Sensitivity rate = 50%Sensitivity rate = 50%
ibm01ibm01 26952695 272272 00 113113 00
ibm02ibm02 43864386 448448 00 185185 00
ibm03ibm03 62376237 663663 00 327327 00
ibm04ibm04 62016201 891891 00 346346 00
ibm05ibm05 73487348 912912 00 362362 00
ibm06ibm06 67526752 605605 00 259259 00
Expand to Full Chip
Crosstalk ModelingCrosstalk Modeling Global routing synthesisGlobal routing synthesis Post-GR refinement with optimal crosstalk Post-GR refinement with optimal crosstalk
budgetingbudgeting iSINO formulations iSINO formulations iSINO/LP algorithmiSINO/LP algorithm Experiment resultsExperiment results
ConclusionsConclusions
iSINO Formulation
Given:Given: Global routing solution and crosstalk constraints at Global routing solution and crosstalk constraints at
sinkssinks Find:Find:
A partition of crosstalk budget among routing A partition of crosstalk budget among routing regions and a SINO solution for each regionregions and a SINO solution for each region
Such thatSuch that The crosstalk constraint is satisfied, and the routing The crosstalk constraint is satisfied, and the routing
area is minimizedarea is minimized
Overall Algorithm of iSINO
Phase I : noise budgeting for given global routingPhase I : noise budgeting for given global routing CB/1D, CB/2D, CB/2D-pCB/1D, CB/2D, CB/2D-p
Phase II: SINO within each regionPhase II: SINO within each region Same as in GSINOSame as in GSINO
Phase III: post-routing refinementPhase III: post-routing refinement Same as in GSINOSame as in GSINO
Crosstalk Budgeting for One-dimension Routing (CB/1D Problem)
Given: Given: One-dimension routing solutionOne-dimension routing solution
Find: Find: Partitioning of crosstalk boundsPartitioning of crosstalk bounds
Such that Such that The maximum height is minimizedThe maximum height is minimized
blockageblockage
blockage
sourcesink
hmax
Minimize hmax
CB/1D Problem formulation
blockageblockage
blockage
sourcesink
hmax
max:min h..ts
maxhOGK tGN
ttitt
tit
ijitHR
t LSKKlijt
tit GN
tttitt OCK
RRallfor t
iiij NallandPpallfor
RRallfor t
Given Given two-dimension routing solutiontwo-dimension routing solution
FindFind partition crosstalk bounds among all routing regionspartition crosstalk bounds among all routing regions
Such thatSuch that the weighted sum of maximum height and width is minimized.the weighted sum of maximum height and width is minimized.
Crosstalk Budgeting for Pseudo Two-Dimension Routing (CB/2D-p problem)
blockage
blockage
blockageblockage
sink i1
sink i2
source i
sink j1
sink j1
source j
hmax
wmax
Minimize *wmax + *hmax
CB/2D-p problem formulation
blockage
blockage
blockageblockage
sink i1
sink i2
source i
sink j1
sink j1
source j
hmax
wmax
maxmax:min hw ..ts
max)( hOGK tGN
ttittR titCLMt
ijitHR
t LSKKlijt
tit GN
tttitt OCK
CLMCLMallfor
iiij NallandPpallfor
RRallfor t
max)( wOGK tGN
ttittROWR titt
ROWROWallfor
Given Given two-dimension routing solutiontwo-dimension routing solution
FindFind partition crosstalk bounds among all routing regionspartition crosstalk bounds among all routing regions
Such thatSuch that the total chip area is minimized.the total chip area is minimized.
Crosstalk Budgeting for Two-Dimension Routing (CB/2D problem)
Minimize: wmax * hmax
blockage
blockage
blockageblockage
sink i1
sink i2
source i
sink j1
sink j1
source j
hmax
wmax
CB/2D problem formulation
blockage
blockage
blockageblockage
sink i1
sink i2
source i
sink j1
sink j1
source j
hmax
wmax
maxmax:min hw ..ts
max)( hOGK tGN
ttittR titCLMt
ijitHR
t LSKKlijt
tit GN
tttitt OCK
CLMCLMallfor
iiij NallandPpallfor
RRallfor t
max)( wOGK tGN
ttittROWR titt
ROWROWallfor
Main Theorem
CB/1D and CB/2D-p problem are linear CB/1D and CB/2D-p problem are linear programming (LP) problemprogramming (LP) problem all constraints and the objective are linearall constraints and the objective are linear
CB/2D problem are non-linear programming CB/2D problem are non-linear programming (NLP) problem(NLP) problem The objective is nonlinear (but all constraints are The objective is nonlinear (but all constraints are
linear though)linear though)
Conclusions and Further Study
LP-based noise budgeting reduce routing area by LP-based noise budgeting reduce routing area by 5.71%5.71% Details see reading assignmentDetails see reading assignment
Multi-level routing may be used to reduce Multi-level routing may be used to reduce runtime of iterative deletion and consider runtime of iterative deletion and consider integrity for both power and signal netsintegrity for both power and signal nets Student presentationStudent presentation
Detailed modeling for capacitive noiseDetailed modeling for capacitive noise Bottom-up modelBottom-up model 2-2- model model