Lecture 1 Digital Components

7/30/2019 Lecture 1 Digital Components

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Combinational circuitConverts n coded inputs to a

maximum of 2n outputs.

n x m decoder [2 x 4, 3 x 8 ]Enable (E) inputs to control

the operation of the circuit.






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A D0 D1

0 1 0

1 0 1

A

D 0 = A’

D 1 = A








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Data inputs A and B are decoded into

four outputs D0 ,D1 ,D2 , D3 Each output representing one of the

combinations of the binary input

variables.

Application of decoder is a binary-to-

octal conversion.






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2 inverters provide thecomplement of the inputs, and

4 AND gates generates one of the binary combination.





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The decoder has one enableinput E.

E =1 decoder is enabled

E=0 disabled






A B D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1






When the enable input E is equal to

0, all the outputs are equal to 0

regardless of the values of data

inputs.

When the enable input E is equal to

1, the decoder operates in a normal

fashion.






For each possible inputcombination, there are three

outputs that are equal to 0 and

only one is equal to 1 representsthe octal number equivalent to

the binary number that is

available in the input data line.











Three inputs, A0, A1, A2, are decodedinto eight outputs, D0 -D7

Each output Di represents one of theminterms of the 3 input variables.

Di = 1 when the binary numberA2A1A0 = I

The output variables are mutuallyexclusive; exactly one output has thevalue 1 at any time, And the other sevenare 0.






Digital circuit that performs theinverse operation of a decoder.

2n input lines and n output lines.

The output line generates thebinary code corresponding to theinput line whose value is 1.








It has eight inputs, one for each of the octal digits, and three outputs that generates the corresponding binary number.

It assumes that only one input has a value of 1 at a given time.






The encoder can be implemented with ORgate whose inputs are determined directlyfrom the truth table.

The output A0 = 1 if the input octal digit is 1or 3 or 5 or 7. Similar conditions are appliedfor the other two outputs.

These conditions are expressed by thefollowing Boolean functions:

A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7











A Multiplexer is a combinational

circuit that receives binaryinformation from one of 2n input

data lines and directs it to a

single output line.The selection of a particular

input data line for the output is

determined by a set of selectioninputs.






A 2n-to-1 Multiplexer has 2n input

data lines and n input selectionlines whose bit combinations

determine which input data are

selected for the output.

A 4-to 1 line multiplexer is shownbelow:






I 0

I 1

I 2

I 3

s0

s1

Y

4-to-1 line multiplexer

0

0

1

1. When S1=0, S0= 0






Each of the four data inputs I0 through I3 is applied to one of theAND gate.

The two selection inputs S1, S0 aredecoded to select a particular ANDgate .

The output of the AND gates areapplied to a single OR gate toprovide the single output.






The 4-to1 line multiplexer hassix inputs and one output.

The function table demonstratesthe relationship between the four

data inputs and the single outputas a function of the selectioninputs S1 and S0.

Select

S1 S0

Output

Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3







When the selection inputs areequal to 00, output Y is equal toinput I

0.

When the selection inputs areequal to 01, output Y is equal toinput I1.








I0

I1

I2

I3

I4

I5

I6

I7

ES

2S

1S

0

74151

MUX

D A

T

A

IN

P

U

T

S

SELECT LINES

Z _

Z





Typical Application of a MUX

25

MP3 Player

Docking Station

Laptop

Sound Card

DigitalSatellite

Digital

Cable TV

Surround Sound System

M U X

D0

D1

D2

D3

Y

B A Selected Source

0 0 MP3

0 1 Laptop

1 0 Satellite

1 1 Cable TV

Multiple Sources Single DestinationSelector



4-to-1 Multiplexer Waveforms

26

D0

D1

D2

D3

A

B

Y

D0 D1 D2 D3 D0 D1 D2 D3

Input

Data

Select

Line

Output

Data




A demultiplexer (DMUX) is a

device which essentially performs

the opposite operation to the MUX.

That is, it functions as an electronicswitch (/data distributor)[MUX –

Data Selector] to route an incoming

data signal to one of several outputs.The select lines determine which

output the input is connected to.






DEMUX Types

1-to-2 (1 select line)

1-to-4 (2 select lines) 1-to-8 (3 select lines)

1-to-16 (4 select lines)





Typical Application of a MUX

29

MP3 Player

Docking Station

Laptop

Sound Card

DigitalSatellite

Digital

Cable TV

Surround Sound System

M U X

D0

D1

D2

D3

Y

B A Selected Source

0 0 MP3

0 1 Laptop

1 0 Satellite

1 1 Cable TV

Multiple Sources Single DestinationSelector




the logic symbol 1 x 4

Demux











Demultiplexer- Function

Table






D0

D1

D2

D3X

B A

D E M

U X





1-to-4 De-Multiplexer Waveforms

34

X

S0

S1

D0

D1

D2

D3

Output

Data

Select

Line

InputData




[1x 8]DEMUX
























Combine two or more small decoders

with enable inputs to form a larger

decoder

3-to-8-line decoder constructed from two

2-to-4-line decoders• The MSB is connected to the enable

inputs• if A2=0, upper decoder is enabled; ifA2=1, lower decoder is enabled.











The 2 LSB bits of the input are

connected to both decoders.The MSB bit is connected to the

enable input of one decoder and

through an inverter to the enable

input of the other decoder.

The output of the upper decoder

generate output D0

through D3

depending on the values of A1 and

A0 (while A2 = 0)






When A2 =1, the lower decoder is

enabled and generate binary

equivalent D4 through D7 since these

binary numbers have a 1 in the A2 position

The example shows the usefulness of

the enable input in decoder or anyother combinational logic

component.






Convenient feature for

interconnecting 2 or more circuits for

the purpose of expanding the digital

component with more inputs andoutputs.

C 4 16 d d f






Construct a 4x16 decoder from two

3x8 decoders with 1-enable.






How to construct a 4x16 decoder

using five 2x4 decoders with enable?

Implement the following logic

function using decoders and logic

gates f(Q,X,P) = Σm(0,1,4,6,7)






Example Realize F (X,Y,Z) =

Σ (1, 4, 7) with a decoder:






Two or more MUX are enclosed

within a single IC package.

A quadruple 2-to-1 line MUX is

shown below:

The circuit has 4 MUX, each

capable of selecting one of two

input lines.






Select

EnableE

S

A0

A1

A2

A3

B0

B1

B2

B3

Y0

Y1

Y2

Y3

E S Y

0 x All 0’s

1 0 A

1 1 B

Output Y0 can be

selected to come

from either input A0 or B0.

Output Y1 may

have the value of

A1 or B1 and so

on..

if S=0, the four A

inputs have a

path to the four

outputs.When S=1, the

four B inputs are

applied to the

outputs.

O th i t l ti li S l t






On the input selection line S selects

one of the lines in each of the 4

MUX.The unit is enabled when E = 1, and

the output have all 0’s when E=0,

regardless of the values of S.

A






SEL

B0

A 0F0

B3

A 3F3

B1

A 1F1

B2

A 2F2

En







Combinational circuits which is

used to perform subtraction of two

bits.

Two inputs – X (minuend) and Y

(subtrahend)

Two Outputs – D (Difference ) and

Bout(borrow out)

Logic symbol for HS :






X

Y

D

Bout

HS

(x Y)=D

(X’Y)=B out






INPUTS OUTPUTS

X Y Difference D Borrow Bout

0 0 0 0

0 1 1 1

1 0 1 01 1 0 0

D= X’Y +XY’ = XY

Bout = X’Y











Lecture 1 Digital Components

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