111/06/23 1 VLSI Design and Layout VLSI Design and Layout Practice Practice Lect5 – Stick Diagram & Lect5 – Stick Diagram & Scalable Design Rules Scalable Design Rules Danny Wen-Yaw Chung Danny Wen-Yaw Chung Institute of Electronic Engineerin Institute of Electronic Engineerin g g Chung-Yuan Christian University Chung-Yuan Christian University Sept. 2008 Sept. 2008
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112/04/12 1
VLSI Design and Layout PracticeVLSI Design and Layout PracticeLect5 – Stick Diagram & Scalable Lect5 – Stick Diagram & Scalable
Design RulesDesign Rules
Danny Wen-Yaw ChungDanny Wen-Yaw ChungInstitute of Electronic EngineeringInstitute of Electronic EngineeringChung-Yuan Christian UniversityChung-Yuan Christian University
Sept. 2008Sept. 2008
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IC Layout Concept and Examples
I. Stick Diagram II. Design Rules III. Layout Verification
Ref: http://140.135.9.56/XMS/
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A. Basic Concept 1. Based on the view point of IC layout, the
stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.
Legend:
contactmetal 2
metal 1
poly
ndiff
pdiff
VDD
in
VSS
out
■
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A. Basic Concept 2. Although the stick diagram is an abstract
presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2-diomensional plane and reach the aim same as the physical layout does.
3. The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices, it still can reflect the real condition to layout of the silicon chip.
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B. Notations of the stick diagram
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Stick Diagram Intermediate representation
between the transistor level and the mask (layout) level.
Gives topological information (identifies different layers and their
relationship) Assumes that wires have no width. It is possible
to translate stick diagram automatically to layout with correct design rules.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
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Stick Diagram
1. When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.
2. When polysilicon crosses N or P diffusion, an N or P transistor is formed. Polysilicon is drawn on top of diffusion. Diffusion must be drawn connecting the source and the drain. Gate is automatically self-aligned during fabrication.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
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Stick Diagram
3. When a metal line needs to be connected to one of the other three conductors, a contact cut (via) is required.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
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Stick Diagram 4. Manhattan geometrical rule: When we use only vertical an
d horizontal lines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also allows curve
s to describe circuitry. 5. In order to describe N/PMOS more completely, to add
n-well 、 P+ select 、 well contact and substrate contact are optional for 4-terminal notation.
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Conclusion
1. Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout.
2. Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location.
3. Stick diagram doesn’t include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.
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CMOS Inverter Stick Diagrams
Basic layout
․ More area efficient layout
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
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CMOS inverter described in other way.
VDD
in
VSS
out
CMOS Inverter Stick Diagrams
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CMOS Transmission Gate
The transmission gate Circuit schematic Stick diagram
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CMOS Stick DiagramsNAND/NOR
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[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
CMOS Stick DiagramsNAND
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< Exercise 1 >
To draw the following circuitry by using a stick diagram
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< Exercise 2 > To draw the stick diagram and the schematic for the following layout
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1
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CMOS Stick Diagrams[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
NOR
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CMOS Inverter Mask Layout
Min. spacing andline width consideration
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Lambda-based Design Rules
Lambda design rules are based on a reference metric λthat has units of um.
All widths, spacing and distances are written in the form Value = m λ
Where m is scaling multiplier.<e.g.> λ= 1um w = 2 λ=2um s = 3λ=3um
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Lambda based design: half of technology since 1985. As technologychanges with smaller dimensions, a simple change in the value of canbe used to produce a new mask set.
All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3
6
2
6
3
3
Lambda-based Design Rules
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Active Contact and Surround Rule
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Potential Problem - Misalignment
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Potential Problem – Short between Source and Drain
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Degree of anisotropy A = 1 – rlat/rvert
Where r respective etch rates
Physical Limitations
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Design Rule (0)
Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment.
In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule 。
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Design Rules(1)
Layout rules are used for preparing the masks for fabrication. Fabrication processes have inherent limitations in accuracy. Design rules specify geometry of masks to optimize yield and
reliability (trade-offs: area, yield, reliability). Three major rules:
Wire width: Minimum dimension associated with a given feature.
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Layout Verification
B. DRC(Design Rule Check) : => To check the min. line width and spac
ing based on the design rules.
C. ERC(Electrical Rule Check) : => To check the short circuit between P
ower and Ground, or check the floating node or devices.
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Layout Verification
D. LVS(Layout versus Schematic) : => To verify the consistency between Schematic and L
ayout. For example : to check the amount of transistor numbers, sizes of W/L.
E. LPE or PEX(Layout Parameter Extraction) : => From the database of layout, to extract the device
s with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation 。
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Layout Verification
F. SimulationsPre-Layout Simulation - before layout workPost-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.
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