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Lecture 260 – Buffered Op Amps (3/28/10) Page 260-1
LECTURE 260 – BUFFERED OP AMPSLECTURE ORGANIZATION
Outline• Introduction• Open Loop Buffered Op Amps• Closed Loop Buffered Op Amps• Use of the BJT in Buffered Op Amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 352-368
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-2
OPEN LOOP BUFFERED OP AMPSThe Class A Source Follower as a Buffer• Simple
• Small signal gain gm
gm + gmbs + GL < 1
• Low efficiency
• Rout = 1
gm + gmbs 500 to 1000
• Level shift from input to output• Maximum upper output voltage is limited• Broadbanded as the pole and zero due to the source follower are close so compensation
is typically not a problem
060118-10
VNBias1
VDD
M1
M2
vIN
vOUT
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-4
Compensation of Op Amps with Output AmplifiersCompensation of a three-stage amplifier:This op amp introduces a third pole, p’3 (whatabout zeros?)With no compensation,
Vout(s)Vin(s) =
-Avo
sp’1 - 1
sp’2 - 1
sp’3 - 1
Illustration of compensation choices:
p1'p2'p3' p1
p2
p3
jω
σp1'p2'p3' p1
p2
p3=
jω
σ
Miller compensation applied around both the second and the third stage.
Miller compensation applied around the second stage only. Fig. 7.1-5
Compensated polesUncompensated poles
vin vout+-
x1v2
Unbufferedop amp
Outputstage
Polesp1' and p2'
Pole p3'
+
-
Fig. 7.1-4
CL RL
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-8
Crossover-Inverter, Buffer Stage Op AmpPrinciple: If the buffer has high output resistance and voltage gain (common source), thisis okay if when loaded by a small RL the gain of this stage is approximately unity.
060706-04
-
+vin
M1 M2
M3 M4
M5
M6M7
vout
VDD
VSS
C2
RL
+-
C1
Cross over stage Output StageInputstage
vin'
IBias
• This buffer trades gain for the ability to drive a low load resistance• The load resistance should be fixed in order to avoid changes in the buffer gain• The push-pull common source output will give good output voltage swing capability
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-9
Crossover-Inverter, Buffer Stage Op Amp - ContinuedHow does the output buffer work?The two inverters, M1-M3 and M2-M4 are designed to work over different regions of thebuffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
060706-05
VDDVA
M6 Active
M6 Satur-ated
M5 Active
M5 Saturated
VB
M1-M3Inverter
M2-M4Inverter
0 vin'
M1 M2
M3 M4M7
vout
VDD
VSS
C2C1
vin'
M6
M5 RL
voutVDD
VSS
IBias
Crossover voltage VC = VB-VA 0
VC is designed to be small and positive for worst case variations in processing.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-10
Large Output Current BufferIn the case where the load consists of a large capacitor, the ability to sink and source alarge current is much more important than reducing the output resistance. Consequently,the common-source, push-pull is ideal if the quiescent current can be controlled.A possible implementation:
If W4/L4 = W9/L9 andW 3/L3 = W8/L8, then thequiescent currents in M1and M2 can be determinedby the followingrelationship:
I1 = I2 = Ib W 1/L1W 7/L7
= Ib W 2/L2
W 10/L10
When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,when vin is decreased, M5 turns off M1 and turns on M2 to sink current.
VDD
VSS
Ib
Ib
I=2Ib
M1
M2
M3 M4
M5
M6
M7
M8 M9
M10
vin
I=2Ib
vout
070430-07
vin
VDD
VSS
vout
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-11
Low Output Resistance Op Amp - ContinuedOffset correction circuitry:
-
+vin
A1
M16 M9
vout
VDD
VSS
VBias+
-
Cc
+-
+-
+-M8
M17
M8A
M13M6A
M6
M12 M11
M10
A2
VOS
Error Loop
Fig. 7.1-6
Unbufferedop amp
The feedback circuitry of the two error amplifiers tries to insure that the voltages inthe loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust theoutput for any error in the loop. The circuit works as follows:When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducingIM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreasesby an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-16
Example 260-1 - Low Output Resistance Using Shunt Negative Feedback BufferFind the output resistance of above op amp using the model parameters of KN’ =
120μA/V2, KP’ = 25μA/V2, N = 0.06V-1 and P = 0.08V-1.
SolutionThe current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
Ro = 1
( N+ P)1mA = 10000.14 = 7.143k
To calculate the loop gain, we find that gm2 = 2KN’·10·100μA = 490μS
gm4 = 2KP’·1·100μA = 70.7μSand
gm6 = 2KP’·10·1000μA = 707μS
Therefore, the loop gain is
|LG| = 490
2·70.7 (0.707+0.071)7.143 = 19.26
Solving for the output resistance, Rout, gives
Rout = 7.143k1 + 19.26 = 353 (Assumes that RL is large)
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-20
Example 260-2 - Designing the Class-A, Buffered Op AmpUse an n-well, 0.25μm CMOS technology to design an op amp using a class-A, BJT
output stage to give the following specifications. Assume the channel length is to be0.5μm. The FETs have the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, VTN =
|VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =10-14A and ßF = 50.VDD = 2.5V VSS = 0V GB = 5MHz Avd(0) 2500V/V Slew rate 10V/μsRL = 500 Rout 50 CL = 100pF ICMR = +1V to 2V
SolutionA quick comparison shows that the
specifications of this problem are similarto the folded cascode op amp that wasdesigned in Ex. 240-3. Borrowing thatdesign for this example results in thefollowing op amp.
Therefore, the goal of this examplewill be the design of M12 through Q15 tosatisfy the slew rate and output resistancerequirements.
070430
VPB1
M4 M5Rout
I6
VPB2
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10M11
+−vIN
vO
VNB1
I1 I2
M1 M2
M3I3
C
VNB1
VPB1
M12
M13
M14
Q15
I12
I15
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-25
Assuming the gate of M14 is connected to the gate of M5, the W /L ratio of M14becomes
W14/L14 = (1000μA/125μA)160 = 1280 W14 = 640μm
I15 = 1mA 1/gm15 = 0.0258V/1mA = 25.8
MOS follower:To source 1mA, the BJT requires 20μA (ß =50) from the MOS follower (M12-M13). Therefore, select a bias current of 100μA for M13. If the gates of M3 and M13 areconnected together, then
W13/L13 = (100μA/100μA)15 = 15 W13 = 7.5μm
To get Rout = 50 , if 1/gm15 is 25.8 , then design gm12 as1
gm15 =
1gm12(1+ßF) = 24.2 gm12 =
1(24.2 )(1+ßF) =
124.2·51 = 810μS
gm12 and I12 W/L = 27.3 30 W12 = 15μm
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-26
SUMMARY• A buffered op amp requires an output resistance between 10 Ro 1000
• Output resistance using MOSFETs only can be reduced by,- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is
larger than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate thecompensation of the op amp