Lect 16 Programmable Logic and Hardware Programming (Verilog HDL) Hardware Programming (Verilog HDL) CS221 Di it l D i CS221: DigitalDesign Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Indian Institute of Technology Guwahati 9/2/2018
36
Embed
Lect16 Programmable Logic and Hardware Programming ... · Lect16 Programmable Logic and Hardware Programming (VerilogHDL) CS221: Di it lDigital DiDesign Dr. A. Sahu Dept of Comp.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Sh t h d t ti d 't h tShort‐hand notation so we don't have todraw all the wires!
X at junction indicates a connection 9/2/2018
2. PALsWhat is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?PAL concept — implemented by Monolithic MemoriesPAL concept implemented by Monolithic MemoriesAND array is programmable, OR array is fixed at fabrication
A given column of the OR array has access to only a subset of the
possible product terms
PLA concept — Both AND and OR arrays are programmable9/2/2018
3. ROM as Memory•Read Example: For input (A2,A1,A0) = 011, output is (F0,F1,F2,F3 ) = 0010.What are functions F F F and F in terms of (A A A )?
0 1 1 0 1Address 8x4 ROM
•What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
• Simple Programmable logic deviceSimple Programmable logic device– Single AND LevelFli Fl d f db k– Flip‐Flops and feedbacks
• Complex Programmable logic device– Several PLDs Stacked together
9/2/2018
SPLD ‐ CPLD• Simple Programmable logic device
– Single AND Level– Flip‐Flops and feedbacks
AA BB CC SelectSelectEnableEnable
FFFlip-flopFlip-flop
DD QQ MUXMUX
F1F1
ClockClock
AND planeAND plane9/2/2018
SPLD ‐ CPLD• Complex Programmable logic device
– Several PLDs Stacked together
PLD PLD
I/O B
I/O B• •
Block Block
Block
Block
•••
•••
Interconnection MatrixInterconnection Matrix
PLD PLD
I/O B
I/O B• •
Block Block
Block
Block
•••
•••
9/2/2018
FPGA
9/2/2018
Field Programmable Gate Arrays ( )(FPGAs)
• FPGAs have much more logic than CPLDsFPGAs have much more logic than CPLDs– 2K to >10M equivalent gatesRequires different architecture– Requires different architecture
– FPGAs can be RAM‐based or Flash‐based• RAM FPGAs must be programmed at power on• RAM FPGAs must be programmed at power‐on
– External memory needed for programming data– May be dynamically reconfigured
• Flash FPGAs store program data in non‐volatile memory– Reprogramming is more difficult– Holds configuration when power is off– Holds configuration when power is off
9/2/2018
FPGA ‐ Field Programmable Gate ArrayArray
• Programmable logic blocks (Logic Element “LE”) or CLBElement LE ) or CLB– Implement combinatorial and sequential logic. Based on LUT and DFF.
• Programmable I/O blocks– Configurable I/Os for external connections supports various voltages and tri‐states.
• Programmable interconnect – Wires to connect inputs , outputs and logic blocks. – Clocksshort distance local connections– short distance local connections
– long distance connections across chip9/2/2018
FPGA ‐ Field Programmable Gate Array•Programmable logic blocks or CLB
(Logic Element “LE”)Implement combinatorial and sequential logicImplement combinatorial and sequential logic. Based on LUT and DFF.
9/2/2018
Configuring LUTLUT is a RAM with data width of 1bit.The contents are programmed at power up