3/18/2015 1 X86 ALP & Components of CPU A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/cs222/ Outline • X86: CISC – Registers, Addressing – Assembly Language Programming – NASM Simulator, GCC/C inline Assembly • Components of CPU – Register, Multiplexor, Decoder, IM/DM – Adder, substractor, Varity of Adder – Multiplier : Serial, Parallel – ALU and Floating Point Flow of Our Course Understanding of Overall Computer Understanding of an existing processor architecture and Analysis Understanding of CISC to RISC Understanding of CISC to RISC Assembly language program : MIPS and X86 Assembly language program : MIPS and X86 Components of processor : Reg, Mux. ALU, Mem, Adder Processor Design : Data Path and Control Path Processor Design : Data Path and Control Path Processor Design : Analysis and Improvement Processor Design : Analysis and Improvement X86 Assembly Program • AX ‐ accumulator reg • BX ‐ base address reg • CX ‐ count reg • DX ‐ data reg AH AL BH BL CH CL DH DL SI (Source Idx ) SI (Source Idx ) DI (Dest. Idx) 31 15 7 0 EAX EBX ECX EDX ESI ESI EDI • SI ‐ source index reg • DI ‐ dest index reg • BP ‐ base pointer. • SP ‐ stack pointer. DI (Dest. Idx) BP (Base Ptr ) SP (Stack Ptr) CS (Code Seg Reg) DS (Data Seg Reg ) DS (Data Seg Reg ) ES (Extra Seg Reg ) SS (Stack Seg Reg) IP (Intr Ptr) Z (Flag Reg) EDI EBP ESP ECS EDS EDS EES ESS EIP EZ X86 Compatibility • 8085 (8 bit) == > 8086 (16 bit) == > i386 (32 bit) or ia32== > x86‐64 (64 bit) or ia64 • AX (AH+AL) : 16 bit • EAX 32 bit • RAX 64 bit RAX 64 bit
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X86 ALP & Components of CPU
A. SahuCSE, IIT Guwahati
Please be updated with http://jatinga.iitg.ernet.in/~asahu/cs222/
Outline • X86: CISC
–Registers, Addressing–Assembly Language Programming–NASM Simulator, GCC/C inline Assembly
• Components of CPU–Register, Multiplexor, Decoder, IM/DM–Adder, substractor, Varity of Adder –Multiplier : Serial, Parallel–ALU and Floating Point
Flow of Our Course Understanding of Overall Computer
yUnderstanding of an existing processor architecture
and Analysis
Understanding of CISC to RISCUnderstanding of CISC to RISC
Assembly language program : MIPS and X86 Assembly language program : MIPS and X86
Components of processor : Reg, Mux. ALU, Mem, Adder
Processor Design : Data Path and Control Path Processor Design : Data Path and Control Path
Processor Design : Analysis and ImprovementProcessor Design : Analysis and Improvement
X86 Assembly Program
• AX ‐ accumulator reg• BX ‐ base address reg• CX ‐ count reg• DX ‐ data reg
• SI ‐ source index reg• DI ‐ dest index reg• BP ‐ base pointer. • SP ‐ stack pointer.
DI (Dest. Idx)BP (Base Ptr )SP (Stack Ptr)
CS (Code Seg Reg)DS (Data Seg Reg )DS (Data Seg Reg )ES (Extra Seg Reg )SS (Stack Seg Reg)
IP (Intr Ptr)
Z (Flag Reg)
EDIEBPESP
ECSEDSEDSEESESS
EIP
EZ
X86 Compatibility • 8085 (8 bit) == > 8086 (16 bit) == > i386 (32 bit) or ia32== > x86‐64 (64 bit) or ia64
• AX (AH+AL) : 16 bit • EAX 32 bit • RAX 64 bitRAX 64 bit
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Register • General registers
– EAX, EBX, ECX, EDX– Acc, Base Ptr for Memory, Ctr and Interrupt, Data
• Segment registers– CS DS ES FS GS SSCS, DS, ES FS GS, SS– Code, Data, Extra (far,near,VideoMem), Stack
• Index and pointers– ESI EDI EBP EIP ESP
• Indicator– EFLAGS
Index and Ptr Register• ES:EDI EDI DI : Destination index register
– Used for string, memory array copying and setting and for far pointer addressing with ES
• DS:ESI, EDI SI : Source index register – Used for string and memory array copyingSS EBP EBP BP S k B i i• SS:EBP EBP BP : Stack Base pointer register– Holds the base address of the stack
• SS:ESP ESP SP : Stack pointer register– Holds the top address of the stack
• CS:EIP EIP IP : Index Pointer– Holds the offset of the next instruction, It can only be read
Memory Model: Segment Definition• .model small
– Most widely used memory model.– The code must fit in 64k.– The data must fit in 64k.
• .model medium– The code can exceed 64k.– The data must fit in 64k.
• .model compact– The code must fit in 64k.– The data can exceed 64k.
• .medium and .compact are opposites.
hellodat SEGMENT BYTE 'DATA' ;Define the data segmentdos_pr EQU 9 ;define a constant via EQUstrng DB 'Hello World',13,10,'$‘; Define char stringhellodat ENDS
hellodat SEGMENT ;define a segmentdos_print EQU 9 ;define a constantstrng DB 'Hello World',13,10,'$' ;Define char stringhellodat ENDS
.data dos_print EQU 9 ;define a constantstrng DB 'Hello World',13,10,'$' ;Define char string
Data Allocation Directives• db : define byte dw: def. word (2 bytes) • dd: def double word (4) dq : def quad word (8) • equ : equate assign numeric expr to a name
.data db A 100 dup (?) ; define 100 bytes, with no initial values for bytes
db “Hello” ; define 5 bytes, ASCII equivalent of “Hello”.
dd PtrArray 4 dup (?) ;array[0..3] of dword
maxint equ 32767 ; define maxint=32767
count equ 10 * 20 ; calculate a value (200)
• Assemby code: Loop– Loop simply decreases CX and checks if CX != 0, if so, a Jump to the specified memory location
MOV CX,100_LABEL: INC AX
– LOOPNZ : LOOPs when the zero flag is not setLOOP _LABEL
main procmov bx, Ncall SUM_OF_Nmov ax,4c00Hint 21hmain endp
end main
push bxdec bxcall SUM_OF_Npop bx
BX_O: add ax, bxret
endp
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NASM • The Netwide ASseMbler• Free BSD : Free Berkley Software Distribution• Linux/Unix Version • 16/32/64 bit X86• 16/32/64 bit X86 • Inter operatable with Liux GCC compiler
NASM Hello World SECTION .data ; data section
msg: db "Hello World",10 ; the string to print, 10=crlen: equ $‐msg ; "$" means "here"
; len is a value, not an addressSECTION .text ; code section
global main ; make label available to linker
main: ; standard gcc entry pointmain: ; standard gcc entry pointmov edx, len ; arg3, length of string to printmov ecx, msg ; arg2, pointer to stringmov ebx, 1 ; arg1, where to write, screenmov eax, 4 ; write sysout command to int 80 hexint 0x80 ; interrupt 80 hex, call kernel
Here "add" is the output operand referred to by register eax. And arg1 and arg2 are input operands referred to by registers eax and ebxrespectively. eax=arg1; ebx=arg2; eax=eax+ebx; add=eax;
GCC inline assembly tutorial and some examples are Available in Course website
http://jatinga.iitg.ernet.in/~asahu/cs222/
Flow of Our Course Understanding of Overall Computer
yUnderstanding of an existing processor architecture
and Analysis
Understanding of CISC to RISCUnderstanding of CISC to RISC
Assembly language program : MIPS and X86 Assembly language program : MIPS and X86
Components of processor : Reg, Mux. ALU, Mem, Adder
Processor Design : Data Path and Control Path Processor Design : Data Path and Control Path
Processor Design : Analysis and ImprovementProcessor Design : Analysis and Improvement
Components of CPU
Division into Data path and Control
DATA PATH
CONTROLLER
controlsignals
statussignals
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Building block types
Two types of functional units:• Elements that operate on data values (combinational)– Output is function of current inputOutput is function of current input– No memory
• Elements that contain state (sequential)– Output is function of current and previous inputs– State = memory
Building block types
Two types of functional units:• Elements that operate on data values (combinational)– Output is function of current inputOutput is function of current input– No memory
• Elements that contain state (sequential)– Output is function of current and previous inputs– State = memory