Silicon Photonics (2012/2) Introduction W.-Y. Choi ● Why Si Photonics? Secret of success? ● Special Topics in Optoelectronics: Realization of (hopefully) all photonic functions on Si platform Si Photonics ENIAC (1946) A4(2010) Performance (Clock Speed) 10KHz 1 GHz Power 170 KWatts 20 Watts Weight 28 tons Negligible Size 0.9 m (w) x 2.6 m (h) x 26 m (l) ~ 약 63 m 2 53.3 mm 2 Technology 17468 vacuum tubes 200 million 45nm CMOS TR Cost $ 487,000 $ 637
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Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
● Why Si Photonics?
Secret of success?
● Special Topics in Optoelectronics: Realization of (hopefully) all photonic functions on Si platform
Si Photonics
ENIAC (1946) A4(2010)
Performance(Clock Speed) 10KHz 1 GHz
Power 170 KWatts 20 Watts
Weight 28 tons Negligible
Size0.9 m (w) x 2.6 m
(h) x 26 m (l)~ 약 63 m2
53.3 mm2
Technology 17468 vacuum tubes
200 million 45nm CMOS TR
Cost $ 487,000 $ 637
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
● Why Si Photonics?
- Scaling and Integration
- Can this continue?
More Moore: Continuation of CMOS scaling
More than Moore: New materials, New technology (Photonics )
Moore’s Law
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
Del
ay In
crea
sing
Process Technology Scale Down
Transistor delay(gate delay)
Interconnect bottleneck !
(ITRS Roadmap 2009)Channel length
: 250nm
Interconnect delay(RC time constant)
● Why Si Photonics ?
-Interconnect Bottleneck: On-Chip Interconnect
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
● Why Si Photonics ?
- Chips are getting larger but clocks are getting faster- Difficult to cover the entire chip within one clock cycle- Interconnection within chip becomes very important for performance
-Interconnect Bottleneck: On-Chip Interconnect
“The development of CMOS-compatible optical components is of paramount importance” (ITRS Road 2009 – Interconnect, p.56)
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
● Why photonics for interconect?
-Interconnect Bottleneck: On-Chip Interconnect
Plot of loss for cu-based on-chip interconnect
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
- Chip-to-Chip Interconnect
• T – number of pins
• t – constant
• g – number of logic gates
• p – rent exponent
T = t x gp
Pin number limited by chip periphery ! Performance limited by I/O
System type Rent exponent (p)
Static memory 0.12Microprocessor 0.45
Gate array 0.50High-speed computer 0.63
Rent’s Rule Ref. P. Christie, T. VLSI, Dec. 2000.
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
Chip-to-Chip Interconnect Serialization
Serial Interconnect: Single but faster connection
Data transferred concurrently !!
Data received concurrently !!
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
- More data throughput Higher and higher data rate - Can this trend be maintained? Can photonics help?
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
- Optical communication: transmitting lots of serialized data for long distance!- Strong driving force for evolution from left to right- But barriers on the right: Cost- Can Si help?
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
- Optical interconnects provide higher data rate with less footprint than electrical interconnects!
IBM cloud computing data center (1,994 of servers)
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
Active Optical Cables
- Full duplex 12-channel 850-nm parallel MMF (up to 50 m)- Transmission rate up to 10.3 Gb/s per channel- CXP-based small form-factor hot pluggable interface- 12-channel 850-nm VCSEL/PIN detector array- Power consumption: ~ 3 W (max) Basically an optical communication link
Silicon Photonics (2012/2)
Introduction
W.-Y. Choi
- Full duplex 4-channel 1490-nm SMF (up to 4,000m)- Transmission rate up to 10.3 Gb/s per channel- High-density Quad Small Form-Factor Pluggable (QSFP) connector