ECE2030 Introduction to Computer Engineering Lecture 10: Building Blocks for Combinational Logic (1) Timing Diagram, Mux/DeMux Prof. Hsien-Hsin Sean Lee Prof. Hsien-Hsin Sean Lee School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Tech Georgia Tech
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Lec10 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Multiplexors
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ECE2030 Introduction to Computer Engineering
Lecture 10: Building Blocks for Combinational Logic (1) Timing Diagram, Mux/DeMux
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech
2
Combinational Logic
• Outputs, “at any time”, are determined by the input combination
• When input changed, output changed immediately– Real circuits is imperfect and have “propagation
delay”• A combinational circuit
– Performs logic operations that can be specified by a set of Boolean expressions
– Can be built hierarchically
Combinationalcircuits
Ninputs
Moutputs
3
Timing Diagram• Describe the functionality of a logic
circuit across time• Represented by a waveform• For combinational logic, Output is a
function of inputs
4
Timing Diagram of an AND Gate (Output=AB) Time
A
B
Output(No Delay)
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Note that the Output change can occur “at any Time” forCombinational logic
5
Timing Diagram ExampleXX
YY
ZZ
FFAA
BB
AA
BB
XX
YY
ZZ
FF
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
6
Timing Diagram ExampleXX
YY
ZZ
FFAA
BB
AA
BB
FF
AA BB FF0 1 11 1 00 0 01 0 1
F = AF = A B B
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
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Combinational Logic
• Outputs, “at any time”, are determined by the input combination