Lec. 9: Pipeline ADC (Part I) - IAUNresearch.iaun.ac.ir/pd/farkhani/pdfs/UploadFile_9091.pdf · Lec. 9: Pipeline ADC (Part ... Principle of Pipeline ADC 1. The total resolution of

Lec. 9:

Pipeline ADC (Part –I)

Lecturer: Hooman Farkhani

Department of Electrical Engineering

Islamic Azad University of Najafabad

Feb. 2016.

Email: [email protected]

In The Name of Almighty

2

IDEA: Cascade several low resolution stages to obtain high overall resolution

3

Applications

Suitable for applications where a relatively high BW and a high resolution a

re required.

Versatile: 8...16bits, 1...200MS/s

4

Pipeline ADC:

Conversion occurs along a cascade of stages

Each stage performs a coarse quantization and computes its error (Vres)

Stages operate concurrently

– Throughput is set by the speed of one single stage

Number of components grows linearly with resolution

– Unlike flash ADC, where components ~ 2B

5

Pipeline ADC

6

Principle of Pipeline ADC

1. The total resolution of the pipeline architecture is given by the sum of the bit

s at each stage (N=k1+k2+k3+…+km).

2. Note that the number of bits at each stage (i.e. k) can either equal or differ

from one another depending on design trade-offs.

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Timing control of a 2-bit per stage 10-bit pipeline

Ref: Maloberti’s book

8

Speed of Pipeline ADC

Latency Vs Throughput

Each stage introduces at least ½ clock cycle latency

But new output data every clock cycle

9

Pipeline ADC features:

Number of components grows linearly with resolution

- Unlike flash ADC, where components grow exponentially ~ 2N

Pipeline ADC trades latency for conversion speed

- Throughput limited by speed of one stage

- Enables high-speed operation

- Latency can be an issue in some applications E.g. in

feedback control loops

Pipelining only possible with good analog "memory elements"

- Calls for implementation in CMOS using switched-capacitor circuits

Many analog circuit non-idealities can be corrected digitally

10

Pipeline ADC

1-bit per stage (1-bit MDAC)

Residue stage characteristics:

11

Example of 1-bit per stage 4bit pipeline ADC (with 4

stages)

Ref: Dr. Zare course slide

12

Illustrative Example:

13

Illustrative Example:

14

15 15

Over/Under Flow (1)

This architecture seriously suffers from OVER RANGE and UNDER RANGE.

When the ADC’s input is in x extent, the (N-1)-bit ADC judges 11…11 and also when ADC’s input is in y extent, the (N1)bit ADC judges 00…00.

out

DN-1

DN-2

. ..D2D

1=11.. .11

DN-1

DN-2

. ..D2D

1=00.. .00

x

y

inVref-V ref

16 16

Over/Under Flow (2)

Resulting in Non-Linearity i

n ADC

Flat part of graph is the ext

ent the (N-1)-bit ADC gener

ates similar codes

in

out

(DND

N-1D

N-2...D

2D

1)

17 17

Error Sources

in

Vref

-Vref

D=1D=0

outIdealrefref

refref

VVinVoutVVin

VVinVoutVinV

20

20

18 18

Error Sources – DC Offset

Extra Constant Term

Charge Injection

Op-amp offset

in

Vref

-Vref

outOffset

Vout = 2Vin + VR +

Vout = 2Vin - VR +

; -VR < Vin < 0

; 0 < Vin < VR

19 19

Error Sources – Comparator Offset

comparing level is not e

xactly at zero

Comparator offset is co

nsiderably high

Low offset comparator

s and offset-canceled c

omparators are more p

ower hungry

in

Vref

-Vref

out Comparator

Offset

Vout = 2Vin + VR

Vout = 2Vin - VR

; -VR < Vin <

; < Vin < VR

20 20

Error Sources – Gain Error

Vin multiplies by a coeffi

cient other than 2

If the gain is greater tha

n 2, over/under range h

appens

Causes:

Capacitor Mismatch

OTA Gain & Settling

in

Vref

-Vref

outGain

Mismatch

Vout = (2+)Vin + VR

Vout = (2+)Vin - VR

; -VR < Vin < 0

; 0 < Vin < VR

21 21

Error Sources – Vref Error (1)

Vref’ > Vref

Vref’ < Vref

in

Vref

-Vref

out

Vref

Error

in

Vref

-Vref

out

Vref

Error

22 22

Error Sources – Vref Error (2)

Vref’ > Vref: some of codes at

beginning/end will not appe

ar; the number of codes in it

s defined input swing [-Vref +

Vref] is less than 2N

Vref’ < Vref: the new swing (

Vref’) is smaller than Vref s

o all 2N codes appear betwe

en Vref but the length of ea

ch LSB is smaller than ideal

vref'-vref'-vref vref

Vref'<Vref

vref-vref

-vref' vref'

Vref'>Vref

23 23

Critical Points of Characteristic

Critical points of the gai

n stage’s I-O characteri

stic

1.5-bit Stage, architectu

re that is not sensitive t

o over/under range pro

blem at points B and C

(1.5-bit Stage: Next lect

ure)

in

Vref

-Vref

D=1D=0

outIdeal

A

D

C

B

24

References

Professor Boris Murmann Course slides 2013,

Stanford University- EE315B course

Dr. Reza Lotfi, ADC course slides 2008.