Lec 6-Part 2 2 New

Lecture 6 – part 2_2

DIGITAL SYSTEMS

Sequential Circuit: Counters

Outline

• Asynchronous counters – MOD number

– Up/ Down counters

– Propagation delay

• Synchronous counters

– Analyze synchronous counters

– Design a synchronous counter

• Registers

Synchronous counters

Synchronous (Parallel) Counters

• In synchronous or parallel counters, all FFs are triggered

simultaneously by the clock

• The clock signal is connected to the CLK input of all the FFs

The total propagation delay will be the same for any FFs

Synchronous counters can operate at much

higher frequencies than asynchronous counters

Synchronous (Parallel) Counters

• Each FF has J & K inputs which are HIGH only when outputs of

all lower-order FFs are HIGH

Synchronous (Parallel) Counters

For this circuit to count properly, only those

FFs supposed to toggle on that NGT should

have J = K = 1.

Synchronous MOD-16 Counter

Mod-60 Counter

Counters with MOD Number <2N

Be active CLR input like

the Asynchronous Counter

Synchronous Down Counter

• A synchronous down counter is constructed in a similar manner to

an up counter

– It uses the inverted FF outputs to control the higher-order J, K inputs

Synchronous, MOD-16,

down counter and output

waveforms

Synchronous Up/Down Counters

Up/Down = 1: count up Up/Down = 0: count down

For designing, just concern to current state and

next state, but not care about the positive/negative

edge trigger of FFs

have a difference with Asynchronous Counter

• For the first five clock pulses,

– The counter counts up

Up/Down = 1

Synchronous Up/Down Counters

• For the last five pulses,

– The counter counts down

Up/Down = 0

Synchronous Up/Down Counters

• There are two arrows leaving each state’s bubble

— a conditional transition

The next state for this counter is

dependent upon the logic level

applied to the control input

(Up/Down)

Presettable Counters

• A presettable counter can be set to any desired starting point

any time — synchronously or asynchronously

The presetting operation is also called parallel loading the counter

Synchronous Up Counter

- asynchronous parallel load

1. Apply the desired count

to the parallel data inputs

(P2P1P0)

2. Set PL = 0

Review Questions

Design Synchronous Counters

• Synchronous counters can be custom-designed to generate

any desired count sequence.

• How to design the Synchronous Counter?

Registers

• Registers classification according to

– The way data can be entered into the register for storage

– The way data are outputted from the register

• Serial data flow through register in serial is generally

called shifting — either to the left or to the right

– Serial output data that feedback to the input of the same

register is called a rotate register

– Serial output data that does not feedback is called

a shift register

• Parallel input data is often described as a load register

Register Data Transfer

Register Data Transfer

Parallel in/parallel out (PIPO)

A group of flip-flops that can store multiple

bits simultaneously and in which all bits of

the stored binary value are directly available

Register Data Transfer

Serial in/serial out (SISO)

Data loaded one bit at a time moves one bit at a time,

with each clock pulse through the flip-flops toward

the other end of the register, and exit one bit at

a time in the same order as originally loaded

Register Data Transfer

parallel in/serial out (PISO)

SH/LD = 1 parallel in/serial out

SH/LD = 0 serial in/serial out

Register Data Transfer

serial in/parallel out (SIPO)

Need to classify: - shift left / right - rotate left / right - load

Shift Register Counters

• Shift-register counters use feedback—the output of the

last FF in the register is connected back to the first FF

in some way

Shift Register Counters – Ring counter

• A Ring counter is a circulating shift register connected so the

last FF shifts its value to the first.

Four-bit Ring counter (MOD-4) State diagram

Sequence table waveform

• The frequency on each FF output = ¼ CLK

MOD-4 ring counter

– MOD-N ring counter need N FFs

– Ring counter require more FFs than a binary counter for the

same MOD number (ex. MOD-8 need 8 FFs vs. 3 FFs)

– The decoding signal for each state is obtained at the output

of its corresponding FF without using decoding gates.

• To operate properly, a ring counter must start off with only one

FF in the 1 state and all the others in the 0 state.

– As power-up starting states will be unpredictable, the

counter is preset to the required starting state and cleared

all of others states before clock pulses are applied.

Shift Register Counters – Ring counter

Shift Register Counters – Johnson counter

• In the Johnson or twisted-ring counter inverted output of the

last FF is connected to the input of the first FF.

Three-bit Johnson counter (MOD-6)

Sequence table waveform

State diagram

• For a given MOD-N number (N is even number), a Johnson counter requires only N/2 FFs

• The waveform of each FF is a square wave (50 percent duty cycle) and the

frequency equal to 1/N the clock cycle (CLK)

The FF waveforms are shifted by one clock period with respect to each other

• It requires decoding gates for states — a Ring counter does not.

AND-2 is used for decoding gates regardless of the number of FFs in the counter.

Shift Register Counters – Johnson counter

Review Questions

Any question?