Lec 15 Systems Architecture 1 Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).
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Lec 15 Systems Architecture 1
Systems Architecture
Lecture 15: A Simple Implementation of MIPS
Jeremy R. JohnsonAnatole D. RuslanovWilliam M. Mongan
Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).
Lec 15 Systems Architecture 2
Introduction
• Objective: To understand how to implement the MIPS instruction set.
• Combine components (registers, memory, ALU) and add control
• Fetch-Execute cycle
• Topics– Sequential logic (elements with state) and timing (edge triggered)
Composing the Elements• First-cut data path does an instruction in one clock cycle
– Each datapath element can only do one function at a time
– Hence, we need separate instruction and data memories
• Use multiplexers where alternate data sources are used for different instructions
04/20/23 Chapter 4 — The Processor 22
R-Type/Load/Store Datapath
04/20/23 Chapter 4 — The Processor 23
Full Datapath
Lec 15 Systems Architecture 25
Adding Control
• Selecting the operations to perform (ALU, read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction
op rs rt rd shamt funct
op rs rt 16 bit address
op 26 bit address
R
I
J
Lec 15 Systems Architecture 26
MIPS Instructions
• add $t0,$s1,$s2
• lw $t0,256($t1)
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
100011 01001 01000 0000 0001 0000 0000
op rs rt offset
Lec 15 Systems Architecture 27
MIPS Instructions Continued
• beq $s1,$s2,25 => 100
• j 1024 => 4096 [+PC+4[31-28]]
000010 00 0000 0000 0000 0100 0000 0000
op address
000100 10001 10010 0000 0000 0001 1001
op rs rt offset
Lec 15 Systems Architecture 28
Determining ALU Control Bits• ALUOp determined by instruction
Instruction ALUOp Instruction funct ALU ALUopcode operation action controlLW 00 load word xxxxxx add 010SW 00 store word xxxxxx add 010BEQ 01 branch eq xxxxxx sub 110R-type 10 add 100000 add 010R-type 10 sub 100010 sub 110R-type 10 and 100100 and 000R-type 10 or 100101 or 001R-type 10 slt 101010 slt 111
• Control Lines
000 and
001 or
010 add
110 sub
111 slt
Lec 15 Systems Architecture 29
• Must describe hardware to compute 3-bit ALU control input
– given instruction type 00 = lw, sw01 = beq, 10 = arithmetic
– function code for arithmetic
• Describe it using a truth table (can turn into gates):
ALUOp computed from instruction type
ALU Control
Lec 15 Systems Architecture 30
Datapath with Control
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
Lec 15 Systems Architecture 31
Control Line Settings
• 8 control lines (control read/write and multiplexors)
Instruction RegDst ALUSrcMemto-
RegReg
WriteMem Read
Mem Write Branch ALUOp
R-format 1 0 0 1 0 0 0 Func Codelw 0 1 1 1 1 0 0 addsw X 1 X 0 0 1 0 addbeq X 0 X 0 0 0 1 sub
April 20, 2023 Chapter 4 — The Processor 32
R-Type Instruction
April 20, 2023 Chapter 4 — The Processor 33
Load Instruction
April 20, 2023 Chapter 4 — The Processor 34
Branch-on-Equal Instruction
April 20, 2023 Chapter 4 — The Processor 35
Implementing Jumps
• Jump uses word address
• Update PC with concatenation of– Top 4 bits of old PC
– 26-bit jump address
– 00
• Need an extra control signal decoded from opcode
2 address
31:26 25:0
Jump
April 20, 2023 Chapter 4 — The Processor 36
Datapath With Jumps Added
Lec 15 Systems Architecture 37
Shortcomings of a Single Cycle Implementation
• Limits reuse of hardware components– each functional unit can be used only once per cycle
– e.g. instruction and data memory required
• Inefficient– clock cycle determined by longest possible path in the machine
– E.G. Assume time for:• Memory units = 200 ps
• ALU and adders = 100 ps
• Register file (read or write) = 50 ps
Instruction class
Instruction memory Register read ALU
operation Data memory Register write Total
R-type 200 50 100 0 50 400 ps
Load word 200 50 100 200 50 600 ps
Store word 200 50 100 200 550 ps
Branch 200 50 100 0 350 ps
Jump 200 200 ps
Lec 15 Systems Architecture 38
Single Cycle Model is inefficient!
• Assume 25% loads, 10% stores, 45% ALU instructions, 15% branches, and 5% jumps
CPU execution time = Instruction count x CPI x Clock cycle time
Performance ratio = CPU Performance (Multicycle impl.)