Dept. of CSE Logic Design Lab Manual Bangalore Institute of Technology, Bangalore 1 LOGIC DESIGN LABORATORY 1 (1a) Given a four variable expression, simplify using Entered Variable Map (EVM) and realize the simplified logic using 8:1 MUX. AIM: To simplify Boolean expression using Entered Variable Map method and realize the simplified logic using 8:1 MUX COMPONENTS REQUIRED: IC74151/IC74153, IC7404, IC7432, patch chords, power chords and trainer kit THEORY: Multiplexer sometimes is called universal logic circuit because a 2 n to 1 multiplexer can be used as a design solution for any n variable truth table. Let’s consider A B and C variables to be fed as select inputs, the fourth variable D as data input. We write all the combinations of 3 select inputs in first row along different columns. Now corresponding to each value of 4 th variable D Truth table output Y is written. The 4 th column Y as a function of D. PROCEDURE: Verify all the components and patch chords whether they are in good condition or not. Make connections as shown in the circuit diagram. Give power supply to the trainer kit. Provide input data to the circuit via switches. Record and verify the output sequence for each combination of the select lines. RESULT: All the entries in the truth table are verified.
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Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 1
LOGIC DESIGN LABORATORY 1
(1a) Given a four variable expression, simplify using Entered Variable Map (EVM)and realize the simplified logic using 8:1 MUX.
AIM: To simplify Boolean expression using Entered Variable Map method and realize the
simplified logic using 8:1 MUX
COMPONENTS REQUIRED: IC74151/IC74153, IC7404, IC7432, patch chords, power
chords and trainer kit
THEORY: Multiplexer sometimes is called universal logic circuit because a 2n to 1
multiplexer can be used as a design solution for any n variable truth table. Let’s consider A B
and C variables to be fed as select inputs, the fourth variable D as data input. We write all
the combinations of 3 select inputs in first row along different columns. Now corresponding
to each value of 4th variable D Truth table output Y is written. The 4th column Y as a
function of D.
PROCEDURE:
Verify all the components and patch chords whether they are in good condition or
not.
Make connections as shown in the circuit diagram.
Give power supply to the trainer kit.
Provide input data to the circuit via switches.
Record and verify the output sequence for each combination of the select lines.
RESULT: All the entries in the truth table are verified.
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 2
PIN DIAGRAMS:
E.g.,
Simplify the function using MEV technique
f(A,B,C,D) = ∑m(2, 3, 4, 5, 12, 14)
Y=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
By Entered Variable MAP:
Simplification by K-Map: Y = ABC + ABC + ABD
A B C D Y
0000000011111111
0000111100001111
0011001100110011
0101010101010101
0011110000001010
A B C Y DataInputs
00001111
00110011
01010101
011000DD
D0D1D2D3D4D5D6D7
CD CD CD CD
AB
AB
AB
AB
0 0 1 1
1 1 0 0
1 0 0 1
0 0 0 0
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 3
CIRCUIT DIAGRAM:
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 4
LOGIC DESIGN LABORATORY 2
(2a) Realize a Full Adder using 3 to 8 decoder IC and 4 input NAND gates.
AIM: To realize a full adder using 3:8 decoder and 4 input NAND gates using IC74138
COMPONENTS REQUIRED: IC74LS20 - four input NAND gate, IC74LS138, patch
chords, power chords and trainer kit
THEORY: The simplest Binary adder is a half adder. It has 2 inputs and 2 output bits. One
is the sum and the other is carry. A half adder has no provision to add carry of lower order
bits when binary numbers are added. When two input bits and a carry are to be added, the
number of input bits become 3 and input combination increases to 8. For this, a full adder is
used. Like half adder, it has 2 outputs. One is sum and the other is carry. New carry
generated is denoted as Cn and carry generated from addition of previous lower order bits is
denoted as Cn-1
PROCEDURE:
Verify all the components and patch chords whether they are in good condition or
not.
Make connections as shown in the circuit diagram.
Give power supply to the trainer kit.
Provide the input data to the circuit via switches.
Record and verify the output sequence for each combination of the select lines.
RESULT: All the entries in the truth table are verified.
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 5
PIN DIAGRAMS:
TRUTH TABLE:
A B C SUM CARRY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 6
Simplification by K-Map:
SUM AB AB AB AB
C
C
0 1 0 1
1 0 1 0
Y = ABC + ABC + ABC + ABC Y = ABC + ABC + ABC + ABC
entity mux1 isPort ( I : in std_logic_vector(7 down to 0);
sel : in std_logic_vector(2 downto 0);zout : out std_logic);
end mux1;
architecture Behavioral of mux1 isbegin
zout<=I(0) when sel="000" elseI(1) when sel="001" elseI(2) when sel="010" elseI(3) when sel="011" elseI(4) when sel="100" elseI(5) when sel="101" elseI(6) when sel="110" elseI(7);
end Behavioral;
SEL
MULTIPLEXER8 TO 1
8ZoutI
3
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 24
8:1 MUX SIMULATION RESULTS
output
Dept. of CSE Logic Design Lab Manual
Bangalore Institute of Technology, Bangalore 25
(2B) WRITE THE VERILOG /VHDL CODE FOR FULL ADDER. SIMULATE &VERIFY ITS WORKING.
TRUTH TABLE
INPUTS OUTPUTS
X Y Z SUM CARRY0 0 0 0 0
0 0 1 1 00 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EXPRESSIONS Sum (S) = X Y ZCarry (Cout) = XY + YZ + ZX