LCPMOS technique

CHAPTER-1

INTRODUCTION

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CHAPTER-1

INTRODUCTION

1.1 PURPOSE OF LOW POWER DESIGN

Digital integrated circuits are found everywhere in modern life and many of them are

embedded in mobile devices where limited power resource is available (e.g. mobile

phones, watches, mobile computers…). To permit a usable battery runtime, such devices

must be designed to consume the lowest possible power. Furthermore, low power is also

very important for non-portable devices, too. Indeed reduced power consumption can

highly decrease the packaging costs and highly increase the circuit reliability, which is

tightly related to the circuit working temperature. Hence, low power consumption is a

zero-order constraint for most ICs manufactured today. In fact, higher performance-per-

watt is the new mantra for micro-processor chip manufacturers today.

In order to achieve high density and high performance, CMOS technology feature size

and threshold voltage have been scaling down for decades. Because of this trend, transistor

leakage power has increased exponentially. The reduction of the supply voltage is dictated

by the need to maintain the electric field constant on the ever shrinking gate oxide.

Unfortunately, to keep transistor speed (proportional to the transistor “on” current)

acceptable, the threshold voltage must be reduced too, which results in an exponential

increase of the “off” transistor current, i.e. the current constantly flowing through the

transistor even when it should be “non-conducting”.

As the feature size becomes smaller, shorter channel lengths result in increased sub-

threshold leakage current through a transistor when it is off. Low threshold voltage also

results in increased sub-threshold leakage current because transistors cannot be turned off

completely. For these reasons, static power consumption, i.e. leakage power dissipation

has become a significant portion of total power consumption for current and future silicon

technologies.

To solve the power dissipation problem, many researchers have proposed different

ideas from the device level to the architectural level and above. However there is no

universal way to avoid tradeoffs between power, delay and area, and thus designers are

required to choose appropriate techniques that satisfy application and product needs.

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1.2 SOURCES OF POWER DISSIPATION

The power consumed by CMOS circuits can be classified into two categories:

Dynamic Power Dissipation:

For a fraction of an instant during the operation of a circuit, both the PMOS

and NMOS devices are “on” simultaneously. The duration of the interval depends on

the input and output transition (rise and fall) times. During this time, a path exists

between Vdd and Gnd and a short-circuit current flows. However, this is not the

dominant factor in dynamic power dissipation. The major component of dynamic

power dissipation arises from transient switching behavior of the nodes. The Signals

in CMOS devices transition back and forth between the two logic levels, resulting in

the charging and discharging of parasitic capacitances in the circuit. Dynamic power

dissipation is proportional to the square of the supply voltage. Every time a capacitive

node (CL) switches from Vdd to Gnd (and back), energy of CLVdd2 is consumed. In

deep-submicron processes, supply voltages and threshold voltages for MOS

transistors are greatly reduced. This, to an extent, reduces the dynamic power

dissipation.

Figure 1.1 Dynamic Power Consumption

Static Power Dissipation:

This is the power dissipation due to leakage currents which flow through a

transistor when no transactions occur and the transistor is in a steady state. Leakage

power depends on gate length and oxide thickness. It varies exponentially with

threshold voltage and other parameters. Reduction of supply voltages and threshold

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voltages for MOS transistors, which helps to reduce dynamic power dissipation,

becomes disadvantageous in this case. The sub-threshold leakage current increases

exponentially, thereby increasing static power dissipation.

The main components of leakage current in a MOS transistor are:

Figure 1.2 Static CMOS Leakage sources

Reverse-biased junction leakage current: Junction leakage occurs from the source

or drain to the substrate through the reverse-biased diodes when the transistor is off.

Gate induced drain leakage: This is caused due to the high field effect in the drain

junction of MOS transistors. It is made worse by high drain to body voltage and high

drain to gate voltage.

Gate direct tunneling leakage: Gate leakage flows from the gate through the oxide

insulation layer to the substrate. Direct tunneling current is significant for low oxide

thickness. The gate leakage of a PMOS device is typically one order of magnitude

smaller than that of an NMOS device with identical Tox and Vdd.

Punch-through: Occurs when the drain voltage is high and the drain and source

depletion regions approach each other. In the punch-through condition, the gate totally

loses the control of the channel current and the sub-threshold slope starts to degrade.

Sub-threshold (weak inversion) leakage: This is the drain to source current of a

transistor operating in the weak inversion region, when gate to source voltage (VGS) is

below the transistor threshold voltage (Vth).

Gate oxide tunneling, punch-through, GIDL and band-to-band tunneling are due to

the high electric field. For the low voltage low power CMOS circuits at current

technology, sub-threshold leakage is the dominant component of the leakage current.

Equation 1.1 below approximates the sub-threshold leakage current of a MOSFET.

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I ¿=A . eθ .[1−e(−q V DS

kT ) ] ………… (1.1)

A=μo CoxWL ( kT

q )2

e1.8

θ=[ q

n' kT(V GS−V t h0

−γ ' V s−η V DS )] μo is the carrier mobility;

Cox is the gate oxide capacitance per unit area;

W and L denote the transistor width and length;

kTq

is the thermal voltage at temperature T;

n' is the sub-threshold swing coefficient of the transistor;

V GS is the gate to source voltage of the transistor;

V t h0is the zero-bias threshold voltage;

γ ' V s is the body effect where γ 'is the linearized body effect coefficient; and

η is the Drain Induced Barrier Lowering (DIBL) coefficient.

V DS is the drain to source voltage of the transistor.

Pleak=∑i

I ¿i.V DSi …………… (1.2)

Equation 1.2 gives the total leakage power for all the transistors.

Dynamic power consumption was previously (at 0.18µ technology and above)

the single largest concern for low-power chip designers since dynamic power

accounted for 90% or more of the total chip power. Therefore, many previously

proposed techniques, such as voltage and frequency scaling etc., focused on dynamic

power reduction. However, as the feature size shrinks, e.g., to 0.09µ and 0.065µ, static

power has become a great challenge for current and future technologies. Based on

International Technology Roadmap for Semiconductors (ITRS) report, the sub-

threshold leakage power dissipation of a chip may exceed dynamic power dissipation

for deep sub-micron technologies.

One of the main reasons causing the leakage power increase is increase of sub-

threshold leakage power. When technology feature size scales down, supply voltage

and threshold voltage also scales down. Sub-threshold leakage power increases

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exponentially as threshold voltage decreases. Furthermore, the structure of the short

channel device lowers the threshold voltage even lower. In addition to sub-threshold

leakage another contributor to leakage power is gate-oxide leakage power due to the

tunneling current through the gate-oxide insulator. Since gate-oxide thickness will be

reduced as technology decreases, in nanoscale technology, gate-oxide leakage power

may be comparable to sub-threshold leakage power if not handled properly.

Minimization of sub-threshold leakage is the primary goal in this thesis.

1.3 MOTIVATION FOR LEAKAGE CONTROL MECHANISMS

Cell phones and pocket PCs have burst-mode type integrated circuits, which for the

majority of the time are in an idle state. For such circuits, it is acceptable to have leakage

during the active mode. However, during the idle state it is extremely wasteful to have

leakage, as power is unnecessarily consumed with no useful work being done. Given the

present advances in power management techniques, leakage loss is a major concern in

deep-submicron technologies, as it drains the battery, even when a circuit is completely

idle. Let us compare the impact of static (leakage) power consumption in the context of a

cell phone example. It is assumed that in general, the cell phone considered is always on

(i.e., 24 hours a day). However, the actual usage of the cell phone is very limited. If a 500

minutes calling plan with 500 minutes total used per month is assumed, the cell phone is

active only 1.15% (500min / (30days_24hours_60min)) of the total on time. This means

that during rest – 98.85% of the time – the cell phone is non-active; however, due to static

power consumption, during rest (standby) the cell phone still consumes energy and

reduces battery life.

Power dissipation of high-performance processors and servers is predicted to

increase linearly over the next decade. The 2006 International Technology Roadmap for

Semiconductors projects power dissipation to reach 300 Watts by the year 2018. Multi-

core integrated processors deliver significantly greater compute power through

concurrency, offer greater system density and run at lower clock speeds, thereby reducing

thermal dissipation and power consumption to an extent. Leakage power will contribute

towards the majority of the total power consumption for such servers fabricated with deep-

submicron technologies.

As technology goes deeper into the sub-micron era, the impact of leakage power

is huge compared to the dynamic power as shown in figure 1.3.

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Figure 1.3 Moore’s Law

Although there are many low-leakage techniques existing, the best prior low-

leakage technique in terms of leakage power reduction, the sleep transistor technique,

loses logic state during sleep mode. Therefore, the sleep transistor technique requires

non-negligible time to wake-up the device from the sleep mode. In an emergency

calling situation to use cell phone, this wake-up time may not be acceptable. Therefore,

an ultra low-leakage technique that can save state even in non-active mode can be quite

important in nanoscale technology.

In this thesis, a novel circuit structure named “LECTOR”, a new remedy for

designers in terms of static power is provided. The LECTOR has a novel structure that

reduces leakage current while saving exact logic state. LECTOR uses two additional

transistors, in a path from supply to ground, which are self-controlled. In short, like the

sleep and zigzag approaches, our approach also obtains the leakage power reduction but

with an advantage of maintaining exact logic states.

Table 1.1 shows the technology scaling of the components and the estimated

power consumption. The number of transistors per circuit will continue to increase as

predicted by Moore’s law, whereas the transistor sizes will continue to shrink. Despite a

decreased supply voltage, the total power will continue to increase.

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2006 2007 2008 2009 2010 2011 2012 2013 2014

Technology node [nm] 90 65 65 65 45 45 45 32 32

Printed Gate Length

[nm]

48 42 38 34 30 27 24 21 19

Transistors Number

[M]

193 386 386 386 773 773 773 1546 1546

Chip Size [mm2] 88 140 111 88 140 111 88 140 111

Voltage Supply [V] 1.2 1.1 1.1 1.1 1 1 1 0.9 0.9

Internal Frequency

[GHz]

6.7 9.2 10.9 12.3 15 17 20 22 28

Total Power [W] 98 104 111 116 119 119 125 137 137

Table 1.1 Technology Scaling

1.4 PROBLEM STATEMENT

This project work addresses low power approaches for very large scale

integration (VLSI) logic. Power dissipation is one of the major concerns when

designing a VLSI system. Until recently, dynamic power was the only concern.

However, as technology feature size shrinks, static power, which was negligible before,

becomes an issue as important as dynamic power. Since static power increases

dramatically (indeed, even exponentially) in nanoscale technology, the importance of

reducing leakage power consumption cannot be overstressed.

A well known previous technique called the sleep transistor technique cuts off

Vdd and/or Gnd connections of the transistors to save leakage power consumption.

However, when transistors are allowed to float, a system may have to wait a long time

to reliably restore lost state and thus may experience seriously degraded performance.

Therefore, retaining state is crucial for a system that requires fast response even while

in an inactive state. The next approach sleepy stack however saves the state using stack

transistors but occupies a lot of area as each transistor is replaced by three transistors.

Our thesis provides new leakage reduction technique that achieves ultra-low leakage

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power consumption while maintaining logic state and occupying less area, and thus can

be used for a system with long inactive times but a fast response time requirement.

1.5 THESIS ORGANIZATION

The report is organized into Five chapters.

Chapter 1: Introduction

This chapter introduces purpose of low power design. This chapter also explains

the sources of power dissipation, addresses the motivation and problem statement and

finally summarizes the organization of the thesis.

Chapter 2: Previous Work

This chapter describes previous work in power reduction research and explains key

differences between our solution and previous work.

Chapter 3: LCPMOS Technique

This chapter introduces the LCPMOS technique. First, the structure of the

LCPMOS is described followed by a detailed explanation of LCPMOS operation.

This chapter also explains reducing area overhead in implementation of LCPMOS

technique, finally explains the experimental methodology carried out in this thesis.

Chapter 4: Applying LCPMOS

This chapter explores various implementations of LCPMOS approach. The

implementation includes generic logic circuits. For each implementation of LCPMOS,

comparisons with respective base cases and with LECTOR are carried out.

Chapter 5: LCPMOS Experimental Results

This chapter discusses the experimental results from various applications of the

LCPMOS approach.

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CHAPTER-2

PREVIOUS WORK

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CHAPTER-2

PREVIOUS WORK

Modern technologies are suffering from a dramatic increase in leakage current.

Constant scaling dictates that the supply voltage has to be reduced when downsizing the

technology feature size. Low threshold voltage devices are used to maintain the

required current drive and to satisfy performance specifications. Low threshold devices

have caused a dramatic increase in leakage current. A direct and live solution for that is

to utilize low threshold devices in the critical path and high threshold devices

elsewhere. The threshold voltage can be controlled utilizing the well bias of the device

in the so called Variable Threshold CMOS (VTCMOS).

A technique for leakage control is power gating, which turns off the devices by

cutting off their supply voltage. This technique makes use of bulky NMOS and/or

PMOS device (sleep transistor) in the path between the supply voltage and ground. The

sleep transistor is turned on when the circuit is active and turned off when the circuit is in

idle state with the help of sleep signal. This creates virtual power and ground rails in the

circuit. Hence, there is a significant detrimental effect on the switching speed when the

circuit is active. The identification of the idle regions of the circuit and the generation of

the sleep signal need additional hardware capable of predicting the circuit states

accurately. This additional hardware consumes power throughout the circuit operation

even when the circuit is in an idle state to continuously monitor the circuit state and

control the sleep transistors.

The use of multiple threshold voltage CMOS (MTCMOS) technology for leakage

control is another technique. The transistors of the gates are at low threshold voltage and

the ground is connected to the gate through a high-threshold voltage NMOS gating

transistor. The logical function of a gating transistor is similar to that of a sleep transistor.

The existence of reverse conduction paths tend to reduce the noise margin or in the worst

case may result in complete failure of the gate. Moreover, there is a performance penalty

since high-threshold transistors appear in series with all the switching current paths. A

variation of MTCMOS technique is the Dual Vt technique, which uses transistors with two

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different threshold voltages. Low-threshold transistors are used for the gates on the critical

path and high-threshold transistors are used for those not in the critical path. It reduces the

noise margin or in worst case may result in complete failure of the gate. In both MTCMOS

and Dual methods, additional mask layers for each value of threshold voltage are required

for fabricating the transistors selectively according to their assigned threshold voltage

values. It is a complicated task to deposit two different oxides thickness, which makes the

fabrication process complex.

In addition to these limitations, the techniques discussed above suffer from

turning-on latency, that is, when the idle subsections of the circuit are reactivated, they

cannot be used immediately because some time is needed before the sub-circuit returns to

its normal operating condition. The latency for power gating is typically a few cycles, and

for Dual technology, is much higher. Also, these techniques are not effective in controlling

the leakage power when the circuit is in active state.

Techniques for leakage power reduction can be grouped into two categories:

(i) State-saving techniques where circuit state (present value) is retained

(ii) State-destructive techniques where the current Boolean output value of the

circuit might be lost.

A state-saving technique has an advantage over a state-destructive technique in that

with a state-saving technique the circuitry can immediately resume operation at a point

much later in time without having to somehow regenerate state.

2.1. SLEEP technique

State-destructive techniques cut off transistor (pull-up or pull-down or both)

networks from supply voltage or ground using sleep transistors (Figure 2.1). this technique

is Multi-Threshold voltage CMOS (MTCMOS), which adds high-Vth sleep transistors

between pull-up networks and Vdd and between pull-down networks and ground while

logic circuits use low-Vth transistors in order to maintain fast logic switching speeds. By

isolating the logic networks using sleep transistors, the sleep transistor technique

dramatically reduces leakage power during sleep mode. However, the additional sleep

transistors increase area and delay. Furthermore, the pull-up and pull-down networks will

have floating values and thus will lose state during sleep mode. These floating values

significantly impact the wakeup time and energy of the sleep technique due to the

requirement to recharge transistors which lost state during sleep.

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Figure 2.1 Sleep Transistor Technique

2.2. FORCED STACK technique

For the stack approach every transistor in the base case network is duplicated with

both original and duplicate bearing half the original transistor width (Figure 2.2).

Duplicated transistors cause a slight reverse bias between the gate and source when both

transistors are turned off. Because sub-threshold current is exponentially dependent on

gate bias, a substantial current reduction is obtained.

The stack effect can be understood from the forced stack inverter example

shown in Figure 2.3. Unlike a generic CMOS inverter, this forced stack inverter consists

of two pull-up transistors and two pull-down transistors. All the transistor inputs share the

same input ‘A’. If A = 0, then both transistors M1 and M2 are turned off. Due to the

internal resistance of M2, the intermediate node voltage Vx is higher than Gnd. The

positive potential of Vx results in a negative gate-source voltage (Vgs) for M1 and

negative source-base voltage (Vsb) for M1. Furthermore, M1 has a reduced drain-source

voltage (Vds), which degrades the Drain Induced Barrier Lowering (DIBL) effect. All

three effects together change the leakage reduction factor, reducing leakage current by an

order of magnitude for today’s channel lengths (0.18μ, 0.13μ, 0.09μ, 0.065μ, 0.045μ).

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Figure 2.2 Forced Stack Figure 2.3 Forced Stack Inverter

Since all transistors are placed in between two parallel rows of continuous VDD

and GND, stack approach design forces an increase in the number of transistors and

decrease in transistor width.

2.3. ZIGZAG Technique

To reduce the wake-up cost of the sleep transistor technique, the zigzag technique

is introduced. The zigzag technique reduces the wake-up overhead by choosing a

particular circuit state (e.g., corresponding to a “reset”) and then, for the exact circuit state

chosen, turning off the pull-down network for each gate whose output is high while

conversely turning off the pull-up network for each gate whose output is low.

Figure 2.4 Zigzag Approach 14

For example, the zigzag technique in Figure 2.4 assumes that the input ‘A’ is

asserted such that the output values result as shown in the figure. If the output is ‘1,’ then a

pull-down sleep transistor is applied; if the output is ‘0,’ then a pull-up sleep transistor is

applied. By applying, prior to going to sleep, the particular input pattern chosen prior to

chip fabrication, the zigzag technique can prevent floating. Although the zigzag technique

retains the particular state chosen prior to chip fabrication, any other arbitrary state during

regular operation is lost in power-down mode. Although the zigzag technique can reduce

wake-up cost, the zigzag technique still loses state. Thus, any particular state (from prior

to going to sleep) which is needed upon wakeup must be regenerated somehow. The

technique may need extra circuitry to generate a specific input vector (in case reset values

are not used for sleep mode input vector).

2.4. SLEEPY STACK technique

The sleepy stack technique has a combined structure of the forced stack

technique and the sleep transistor technique. When applying the sleepy stack technique,

each existing transistor is replaced with two half sized transistors and add one extra sleep

transistor as shown in figure 2.5.

Figure 2.5 Sleepy Stack

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(a) (b)

Figure 2.6 Sleepy Stack (a) active mode (b) sleep mode

The sleepy stack technique has a structure merging the forced stack technique and

the sleep transistor technique. Figure 2.6 shows a sleepy stack inverter. The sleepy stack

technique divides existing transistors into two transistors each typically with the same

width W1 half the size of the original single transistor’s width W0 (i.e., W1 = W0/2), thus

maintaining equivalent input capacitance. The sleepy stack inverter in Figure 2.6(a) uses

W/L = 3 for the pull-up transistors and W/L = 1.5 for the pull-down transistors, while a

conventional inverter with the same input capacitance would use W/L = 6 for the pull-up

transistor and W/L = 3 for the pull-down transistor (assuming μn = 2μp). Then sleep

transistors are added in parallel to one of the transistors in each set of two stacked

transistors. Half size transistor width of the original transistor (i.e., we use W0/2) is used

for the sleep transistor width of the sleepy stack. Although using of W0/2 for the width of

the sleep transistor, changing the sleep transistor width may provide additional tradeoffs

between delay, power and area.

Sleepy Stack operation

Below is an explanation how the sleepy stack works during active mode and during

sleep mode, along with leakage power saving using the sleepy stack structure. The sleep

transistors of the sleepy stack operate similar to the sleep transistors used in the sleep

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transistor technique in which sleep transistors are turned on during active mode and turned

off during sleep mode. Figure 2.6 depicts the sleepy stack operation using a sleepy stack

inverter.

During active mode (Figure 2.6(a)), S = 0 and S’ = 1 are asserted, and thus all

sleep transistors are turned on. This sleepy stack structure can potentially reduce circuit

delay in two ways. First, since the sleep transistors are always on during active mode, the

sleepy stack structure achieves faster switching time than the forced stack structure;

specifically, in Figure 2.6(a), at each sleep transistor drain, the voltage value connected to

the sleep transistor source is always ready and available at the sleep transistor drain, and

thus current flow is immediately available to the low-Vth transistors connected to the gate

output regardless of the status of each transistor in parallel to the sleep transistors.

Furthermore, we can use high-Vth transistors (which are slow but 1000 times or so less

leaky), for the sleep transistors and the transistors parallel to the sleep transistors (see

Figure 2.6) without incurring large delay increase.

During sleep mode (Figure 2.6(b)), S = 1 and S’ = 0 are asserted, and so both of

the sleep transistors are turned off. Although the sleep transistors are turned off, the sleepy

stack structure maintains exact logic state. The leakage reduction of the sleepy stack

structure occurs in two ways. First, leakage power is suppressed by high-Vth transistors,

which are applied to the sleep transistors and the transistors parallel to the sleep

transistors. Second, two stacked and turned off transistors induce the stack effect, which

also suppresses leakage power consumption. By combining these two effects, the sleepy

stack structure achieves ultra-low leakage power consumption during sleep mode while

retaining exact logic state. The price for this, however, is increased area.

2.5. LEAKAGE FEEDBACK technique

The leakage feedback approach is based on the sleep approach. However, the

leakage feedback approach uses two additional transistors to maintain logic state during

sleep mode, and the two transistors are driven by the output of an inverter which is driven

by output of the circuit implemented utilizing leakage feedback. As shown in Figure 2.7, a

PMOS transistor is placed in parallel to the sleep transistor (S) and a NMOS transistor is

placed in parallel to the sleep transistor (S'). The two transistors are driven by the output of

the inverter which is driven by the output of the circuit. During sleep mode, sleep

transistors are turned off and one of the transistors in parallel to the sleep transistors keep

the connection with the appropriate power rail.

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Figure 2.7 Leakage Feedback approach

For the sleep, zigzag, sleepy stack and leakage feedback approaches, dual

Vth technology can be applied to obtain greater leakage power reduction. Since high-Vth

results in less leakage but lowers performance, high-Vth is applied only to leakage

reduction transistors, which are sleep transistors, and any transistors in parallel to the sleep

transistors; on the other hand, low-Vth is applied to the remaining transistors to maintain

logic performance.

2.6. SLEEPY KEEPER technique

Figure 2.8 Sleepy Keeper approach

The basic problem with traditional CMOS is that the transistors are used only in

their most efficient and naturally inverting way: namely, PMOS transistors connect to 18

VDD and NMOS transistors connect to GND. It is well known that PMOS transistors are

not efficient at passing GND; similarly, it is well known that NMOS transistors are not

efficient at passing VDD. However, to maintain a value of ‘1’ in sleep mode, given that

the ‘1’ value has already been calculated, the sleepy keeper approach uses this output

value of ‘1’ and an NMOS transistor connected to VDD to maintain output value equal to

‘1’ when in sleep mode. As shown in Figure 2.8, an additional single NMOS transistor

placed in parallel to the pull-up sleep transistor connects VDD to the pull-up network.

When in sleep mode, this NMOS transistor is the only source of VDD to the pull-up

network since the sleep transistor is off.

Similarly, to maintain a value of ‘0’ in sleep mode, given that the ‘0’ value has

already been calculated, the sleepy keeper approach uses this output value of ‘0’ and a

PMOS transistor connected to GND to maintain output value equal to ‘0’ when in sleep

mode. For this sleepy keeper approach to work, all that is needed is for the NMOS

connected to VDD and PMOS connected to GND to be able to maintain proper logic state.

Consider figure 2.8. Note that there is a sleepy keeper PMOS transistor connecting GND

to the pull-down network. When in sleep mode, this PMOS transistor is the only source of

GND since the sleep transistor is off. On the other hand, there is an additional single

NMOS transistor connecting VDD to the pull-up network. During sleep mode, this NMOS

transistor is the only source of VDD which is the dual case of the PMOS transistor case

explained above.

Sleepy keeper transistors (the NMOS connected to VDD and the PMOS connected

to GND) are not used to dynamically change the output voltage but instead only use them

to maintain an already calculated output voltage. Specifically only a few clock cycles after

entering sleep to a few clock cycles prior to exiting sleep do the sleepy keeper transistors

acts as the sole connection to keep the output voltage unchanged.

The sleep transistor is turned on when the circuit is active and turned off when the

circuit is in idle state with the help of sleep signal. This creates virtual power and ground

rails in the circuit. Hence, there is a significant detrimental effect on the switching speed

when the circuit is active. The identification of the idle regions of the circuit and the

generation of the sleep signal need additional hardware capable of predicting the circuit

states accurately. Additional hardware used to provide the sleep signal increases the area

requirement of the circuit. This technique creates a negative effect when the circuit is

operating in active mode. This additional hardware consumes power throughout the circuit

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operation even when the circuit is in an idle state to continuously monitor the circuit state

and control the sleep transistors.

2.7. LECTOR technique

The basic idea behind this approach for reduction of leakage power is the effective

stacking of transistors in the path from supply voltage to ground. In LECTOR technique

two leakage control transistors (one p-type and one n-type) are introduced between pull-up

and pull-down circuit within the logic gate for which the gate terminal of each leakage

control transistor (LCT) is controlled by the source of the other. This arrangement ensures

that one of the LCTs always operates in its near cutoff region.

2.7.1 LECTOR Structure

Figure 2.9 Generalized structure for leakage controlled gates

The generalized structure of leakage controlled gates using lector technique which

introduces two self controlled transistors between pull up and pull down network. There

by increases the resistance in path from Vdd to ground. But the circuit becomes bulky. The

area overhead in implementation of lector is as shown in section 2.7.2.

2.7.2 LECTOR CMOS Gate

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Figure 2.10 LECTOR CMOS Gate

Figure 2.10 illustrates the topology of a LECTOR CMOS gate. Two Leakage Control

Transistors (LCTs), LCT1 and LCT2, are introduced between nodes N1 and N2. The gate

terminal for each LCT is controlled by the source of the other. Hence, these LCTs act as

self-controlled stacked transistors. No external control circuitry is required using the

LECTOR implementation. The introduction of LCTs increases the resistance of the path

from Vdd to Gnd, thereby reducing leakage.

2.7.3 LCT NAND Gate

Leakage Control TransistOR (LECTOR) technique is illustrated with the case of a

NAND gate. A CMOS NAND gate with the addition of two leakage control transistors is

shown in Figure 2.11 (we later refer to it as the LCT NAND gate). As the NAND logic is

satisfied, thus it is clearly observed that insertion of two leakage control transistors

between the supply and ground path does not affect the basic characteristics of NAND

gate.

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Figure 2.11 LECTOR based CMOS NAND gate

2.7.4 Area overhead in implementation of LECTOR

A method to control the leakage power in a two-input NAND gate was described

above. If we extend this idea to all the basic logic gates, then the area overhead on the

entire circuit will increase up to an upper bound of 60% depending on the logic gates used.

The area overhead on various logic gates implemented using LCTs is tabulated in Table

2.1.

Table 2.1 Area Overhead for various LCT Gates

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CHAPTER-3

LCPMOS TECHNIQUE

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CHAPTER-3

LCPMOS TECHNIQUE

3.1 INTRODUCTION

The basic idea behind this approach for reduction of leakage power is the effective

stacking of transistors in the path from supply voltage to ground. This is based on the

observation that “a state with one transistor OFF in a path from supply voltage to ground

is far less leaky.” In LCPMOS technique one leakage control transistor (one p-type) is

introduced between pull-down and ground circuit within the logic gate for which the gate

terminal of leakage control transistor (LCT) is controlled by the output of the circuit itself.

Figure 3.1 LCPMOS CMOS Gate

Figure 3.1 illustrates the topology of a LCPMOS CMOS gate. One Leakage Control

Transistor (LCT), is introduced between pull down network and ground. The gate terminal

of LCT is controlled by the output of circuit itself. No external control circuitry is required

using the LCPMOS implementation. The introduction of LCT increases the resistance of

the path from pull down network (PDN) to Gnd, which increases the resistance from Vdd to

Gnd, thereby reducing leakage.

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3.2 LCPMOS NOT Gate

Figure 3.2 LCPMOS based CMOS NOT gate

Leakage Control PMOS (LCPMOS) technique is illustrated with the case of a NOT gate.

A CMOS NOT gate with the addition of one leakage control transistor is shown in Figure

3.2 (we later refer to it as the LCPMOS NOT gate). As the NOT logic is satisfied which

can be seen through the input output graphs of LCPMOS based NOT gate, thus it is clearly

observed that insertion of one leakage control transistor between the Pull down network

and ground path does not affect the basic characteristics of NOT gate.

3.3 LCPMOS NAND Gate

Leakage control transistor LCT (PMOS) is introduced between the nodes N1and

N2 of the pull-down and ground logic of the NAND gate. The gate of the LCT is

connected to the output node of the NAND gate. Consider the dc characteristics of the

LCT NAND gate. When Ain = 1V and Bin = 0V, the voltage at the output node is high.

Hence the LCT (PMOS) will be in off state. So it offers very high resistance path from Vdd

to ground so there no path exists from source to ground. Similarly, when A in = 1V and Bin

= 1V, the voltage at the output node is low, operating the transistor to be in on state.

25

Figure 3.3 LCPMOS based CMOS NAND gate

Thus, the introduction of LCT increases the resistance of the path from Vdd to

ground. This also increases the propagation delay of the gate. To reduce this hostile effect,

the transistors of LCT gate are sized such that the propagation delay is equal to its

conventional counterpart.

The transistors of the LCT NAND gate are sized to study its effect on the

propagation delay of the gate. Also, we have tried to adjust the widths of all the transistors

of the LCT NAND gate such that its propagation delay is almost equal to that of a

conventional NAND gate. (We refer to this gate as Iso-LCT NAND gate.) The widths of

PMOS and NMOS transistors, except LCT transistor, used in simulation of gates are set to

two and three times the minimum feature width of the respective process variation.

In the previous technique discussed, the sleep transistors have to be able to isolate

the power supply and/or ground from the rest of the transistors of the gate. Hence, they

need to be made bulkier dissipating more dynamic power. This offsets the savings yielded

when the circuit is idle. Moreover, this technique is input-vector dependent and needs 26

additional circuitry to monitor and control the switching of sleep transistors. Thus, it

consumes power in both active and idle states. In comparison, LCPMOS is vector

independent and the required control signals are generated within the gate.

Forced stacks have 100% area overhead. LECTOR requires exactly two additional

transistors for every path from supply voltage to ground irrespective of the logic function

realized by the gate. In comparison, LCPMOS requires only one additional transistor for

every path from pull down network to ground irrespective of the logic function realized by

the gate. The loading requirements of the gate with forced stacks are huge and depend on

the number of additional transistors added. In comparison, the loading requirement with

LCT is much lower and is a constant. Hence, the performance degradation is insignificant

in the case of LCPMOS, and we overcome the major drawback faced by forced stack and

LECTOR techniques. Figure 3.3 shows the general scheme for converting any SCCG gate

to leakage-controlled gate.

Figure 3.4 Generalized structure for leakage controlled gates

3.4 Experimental methodology

The results of LCPMOS technique is compared with that of the base case

(conventional) and with LECTOR circuits for various CMOS circuits. Experiments are

done on various technologies for some circuits to show the effect of technology scaling on

different parameters. Later we concentrate only on one technology. Also the effects of

varying widths are studied.

27

Schematics are being designed using Tanner S-Edit tool. Schematics are used to

obtain the net lists of test circuits. Schematics are to be created using any process

parameters. And the width and length of the transistors both NMOS and PMOS are varied

for various technologies. Spice commands are used for generating the power and input –

output values. W-edit generates the graphs for power and input –output values. The power

consumptions for LCPMOS circuits are measured with varying the LCT width as

mentioned in Table 3.1.

Technology Length

(in µm)

WIDTH

Normal transistors Leakage Control Transistor

NMOS PMOS PMOS

180nm L (0.18) 4L 8L L, L

90nm L (0.09) 4L 8L L, L

65nm L(0.065) 4L 8L L, L

Table 3.1 Width parameter for LCPMOS circuits

The supply voltage for various technologies are considered as mentioned in the Table 3.2

Technology 180nm 90nm 65nm

Supply Voltage 1.8V 1.1V 0.9V

Table 3.2 Vdd parameter

The threshold voltages for NMOS and PMOS are to be maintained as shown in the table

3.3 for various technologies

Technology NMOS PMOS

180nm 0.3999 -0.42

90nm 0.2607 -0.303

65nm 0.22 -0.22

Table 3.3 Threshold voltage parameter

The experimental setup is as shown in figure 3.5

28

Figure 3.5 Experimental Methodology

Static power consumption is measured for all the CMOS circuits in the

technologies considered for the particular circuits.

Dynamic Power

Dynamic power is measured by asserting sets of input vectors in S-EDIT. The

input vectors include all the possible input combinations. The dynamic power is

determined by considering the average of all the power dissipations obtained for all the

possible input combinations

29

CHAPTER-4

APPLYING LCPMOS

30

CHAPTER-4

APPLYING LCPMOS

4.1. Applying LCPMOS to Logic circuits

In chapter 3, the proposed low-leakage “LCPMOS” structure is explained.

Furthermore, various circuit applications of the LCPMOS techniques are explored. The

applications are categorized into two kinds: generic logic circuits and memory circuits.

Generic logic circuits are considered in this project and results are tabulated. The

generic logic circuits – including universal gates (NAND & NOR), AND-OR-Invert,

and full adder – are implemented using LCPMOS and also the base case (conventional

circuits) and LECTOR circuits. The LCPMOS technique is applied to various generic

logic circuits to show that LCPMOS technique is applicable to general logic design.

4.1.1. NOT GATE

Figure 4.1 NOT Gate

A NOT gate is shown in Figure 4.1. The functionality of NOT can be given

through its truth table as shown in table 4.1.

INPUT OUTPUT

A Z

0 1

1 0

Table 4.1 NOT Truth Table

The transistor-level schematic of NOT is as shown in figure 4.2. For the

realization of transistor-level schematic of NOT, the PMOS should be arranged in series

in the Pull-Up network and NMOS should be arranged in series in the Pull-Down

network.

31

Figure 4.2 CMOS NOT Schematic

The sizes of the transistor in the NOT gate are maintained as mentioned in chapter 3.

The NOT schematics that are designed through the Tanner S-EDIT for the base

case (conventional NOT), LECTOR NOT and LCPMOS NOT are shown in figure 4.3

(a) and figure 4.3 (b) and 4.3(c).

Figure 4.3 (a) Conventional NOT

32

Figure 4.3 (b) LECTOR NOT

PMOS_1: Normal PMOS transistors in Pull-Up network

NMOS_1: Normal NMOS transistors in Pull-Down network

PMOS_2: Leakage Control PMOS Transistor (LCT1) for Pull-Up network

NMOS_2: Leakage Control NMOS Transistor (LCT2) for Pull-Down network

33

Figure 4.3 (c) LCPMOS NOT

PMOS_1: Normal PMOS transistors in Pull-Up network

NMOS_1: Normal NMOS transistors in Pull-Down network

PMOS_2: Leakage Control PMOS Transistor (LCT)

4.1.2. Universal Gates

NAND and NOR are called UNIVERSAL GATES since any logic can be

implemented using either of the gates.

4.1.2.1. NAND Gate

Figure 4.4 2-input NAND Gate

A 2-input NAND gate is shown in Figure 4.5. The functionality of NAND can

be given through its truth table as shown in table 4.2.

34

INPUT OUTPUT

A B Z

0 0 1

0 1 1

1 0 1

1 1 0

Table 4.2 NAND Truth Table

The transistor-level schematic of NAND is as shown in figure 4.2. For the

realization of transistor-level schematic of NAND, the PMOS should be arranged in

parallel in the Pull-Up network and NMOS should be arranged in series in the Pull-

Down network.

Figure 4.5 CMOS NAND Schematic

The sizes of the transistor in the NAND gate are maintained as mentioned in chapter 3.

Dynamic Power

For a 2-input NAND gate, as there are four (i.e., 22) possible input combinations,

four input vectors are considered. Therefore to measure the dynamic power of NAND

gate, the average of the power dissipation of all the four input vectors (i.e., (0, 0), (0, 1),

(1, 0), (1, 1)) is to be considered.

35

The NAND schematics that are designed through the Tanner S-EDIT for the

base case (conventional NAND), LECTOR NAND and LCPMOS are shown in figure

4.6 (a) and figure 4.6 (b) and 4.6(c).

Figure 4.6 (a) Conventional NAND

Figure 4.6 (b) LECTOR NAND

36

PMOS_1, PMOS_2: Normal PMOS transistors in Pull-Up network

NMOS_1, NMOS_2: Normal NMOS transistors in Pull-Down network



Figure 4.6 (c) LCPMOS NAND




To verify the designed transistor level schematic and the net list obtained from

the schematic correctness, we have gone through the simulation waveforms through the

W-EDIT

4.1.2.2. NOR Gate

A 2-input NOR gate is shown in Figure 4.7. The functionality of NOR can be

given through its truth table as shown in table 4.3.

37

The transistor-level schematic of NOR is as shown in figure 4.8. For the

realization of transistor-level schematic of NOR, the PMOS should be arranged in series

in the Pull-Up network and NMOS should be arranged in parallel in the Pull-Down

network.

Figure4.8 CMOS NOR Schematic

The sizes of the PMOS and NMOS transistors in the NOR gate are maintained as

mentioned in chapter 3.

Dynamic Power

For a 2-input NOR gate, as there are four (i.e., 22) possible input combinations,

four input vectors are considered. Therefore to measure the dynamic power of NOR

gate, the average of the power dissipation of all the four input vectors (i.e., (0, 0), (0, 1),

(1, 0), (1, 1)) is to be considered.

38

The NOR schematics that are designed through the Tanner S-EDIT for the base

case (conventional NOR), LECTOR NOR and LCPMOS NOR are shown in figure 4.9


Figure 4.9 (a) Conventional NOR

39

Figure 4.9 (b) LECTOR NOR





40

Figure 4.9 (c) LCPMOS NOR






W-EDIT

4.1.2.3 -Input AND-OR-Invert

This application of LCPMOS is considered as a reference to section 3.3 of this

thesis. As mentioned in section 3.3, the AND-OR-Invert is implemented as SCCG

(static CMOS complex gates) instead of considering as gate level. The difference in both

can be clearly identified through the two different implementations as shown in Figure

4.10.

41

Figure 4.10 SCCG implementation of AOI

Dynamic Power

For a 4-input AOI, as there are 16 (i.e., 24) possible input combinations, sixteen

input vectors are considered. Therefore to measure the dynamic power of AOI, the

average of the power dissipation of all the sixteen input vectors (i.e., (0, 0, 0, 0), (0, 0,

0, 1)… (1, 1, 1, 1)) is to be considered.

The AOI schematics that are designed through the Tanner S-EDIT for the base

case (conventional NOR), LECTOR AOI and LCPMOS AOI are shown in figure 4.11


42

Figure 4.11 (a) Conventional AOI

43

Figure 4.11 (b) LECTOR AOI

PMOS_1, PMOS_2, PMOS_3, PMOS_4: Normal PMOS transistors in Pull-Up

network

NMOS_1, NMOS_2, NMOS_3, NMOS_4: Normal NMOS transistors in Pull-Down

network



44

Figure 4.11 (c) LCPMOS AOI




The advantage with SCCG implementation can be observed from Figure 4.10

(c). Irrespective of the number of transistors in the Pull-Up Network and the Pull-Down

network, only one transistor i.e., one PMOS (LCT) in Pull-down network and ground is

to be added for the LCPMOS case to obtain the leakage reduction.



W-EDIT.

45

CHAPTER-5

LCPMOS

Experimental Results

46

CHAPTER-5

LCPMOS Experimental Results

The experimental results for various CMOS circuits are given in this chapter.

For all the circuits we considered the results in three cases i. conventional (base case)

ii. LECTOR iii. LCPMOS and they are listed in the tables and their corresponding

graphs.

Y-axis of the graphs in Figure 5.1 to Figure 5.17 represents the POWER DISSIPATED

in MICRO WATTs (uW)

X-axis of the graphs in Figure 5.1 to Figure 5.17 represents the TECHNOLOGIES i.e.

180nm , 90nm,65nm.

5.1 Basic CMOS Inverter

At first impact of technology scaling on static power is shown analyzing the

NOT gate using all the technologies i.e., 180nm, 90nm, 65nm. The leakage power in

each technology obtained through our technique, i.e., LCPMOS is compared with the

leakage power obtained in the LECTOR Case and base (conventional) case. Fig 5.1 to

5.17 represents the simulation results of NOT, NAND, NOR and AOI GATES

respectively.

5.1.1 NOT Gate

TABLE I. NOT RESULTS FOR VARIOUS TECHNOLOGIES

TECHNOLOG

Y

LEAKAGE POWER IN MICRO

WATTS(uW)

%

decrease

in power

d

issipation

(LECTOR)

%

decrease

in power

d

issipation

(LCPMOS)

BASE

CASE

LECTO

R

LCPMO

S

180nm 130 78 39 40% 70%

90nm 110 35 9.3 68.19% 91.54%

47

65nm 98 5 3.8 94.89% 95.4%

Table 5.1 Results of NOT GATE for various technologies

5.1.2 NOT Gate simulation results for 180nm technology

Fig 5.1(a): Simulation graph of BASE CASE NOT GATE in 180nm technology.

Fig 5.1(b): Simulation graph of LECTOR NOT GATE in 180nm technology.

48

Fig 5.1(c): Simulation graph of LCPMOS NOT GATE in 180nm technology.



49




50



51


180nm 90nm 65nm0

20

40

60

80

100

120

140

BASE CASELECTORLCPMOS

TECHNOLOGY SCALING

LEAK

AGE

POW

ER IN

(uW

)

Figure 5.4 Plot of leakage Power for NOT GATE in various technologies

5.2 NAND Gate

TABLE II. NAND RESULTS FOR VARIOUS TECHNOLOGIES

TECHNOLOG LEAKAGE POWER IN MICRO % %

52

Y WATTS(uW) decrease

in power

d

issipation

(LECTOR)

decrease

in power

d

issipation

(LCPMOS)

BASE

CASE

LECTO

R

LCPMO

S

180nm 140 90 70 35.72% 50%

90nm 125 37 30 70.4% 76%

65nm 115 75 12.5 34.7% 89.13%

Table 5.2 Results of NAND GATE for various technologies

5.2.1 NAND Gate simulation results for 180nm technology

Fig 5.5(a): Simulation graph of BASE CASE NAND GATE in 180nm technology.

53

Fig 5.5(b): Simulation graph of LECTOR NAND GATE in 180nm technology.

Fig 5.5(c): Simulation graph ofLCPMOS NAND GATE in 180nm technology.


54



55

Fig 5.6(c): Simulation graph ofLCPMOS NAND GATE in 90nm technology.



56


Fig 5.7(c): Simulation graph of LCPMOS NAND GATE in 65nm technology.

57

180nm 90nm 65nm0

20

40

60

80

100

120

140

160


TECHNOLOGY SCALING

LEA

KA

GE P

OW

ER

IN

(uW

)

Figure 5.8 Plot of leakage Power for NAND in various technologies

5.3 NOR Gate

TABLE III. NOR RESULTS FOR VARIOUS TECHNOLOGIES

TECHNOLOG

Y


WATTS(uW)

%

decrease

in power

d

issipation

(LECTOR)

%

decrease

in power

d

issipation

(LCPMOS)

BASE

CASE

LECTO

R

LCPMO

S

180nm 98 33 21 66.32% 78.57%

90nm 76 27 18 64.4% 76.31%

65nm 57 8.2 7 85.61% 87.71%

Table 5.3 Results of NOR GATE for various technologies

5.3.1 NOR Gate simulation results for 180nm technology

58


Fig 5.9(b): Simulation graph of LECTOR NOR GATE in 180nm technology.

59

Fig 5.9(c): Simulation graph of LCPMOS NOR GATE in 180nm technology.


Fig 5.10(a): Simulation graph of BASE CASE NOR GATE in 90nm technology.

60




61

Fig 5.11(a): Simulation graph of BASE CASE NOR GATE in 65nm technology.


62


180nm 90nm 65nm0

20

40

60

80

100

120


TECHNOLOGY SCALING

LEA

KA

GE P

OW

ER

IN

(uW

)

Fig 5.12 Plot Of leakage Power for NOR in various technologies

5.4 AND OR INVERT

TABLE IV. AOI RESULTS FOR VARIOUS TECHNOLOGIES

TECHNOLOG

Y


WATTS(uW)

%

decrease

in power

d

%

decrease

in power

d

BASE

CASE

LECTO

R

LCPMO

S

63

issipation

(LECTOR)

issipation

(LCPMOS)

180nm 210 130 60 38.09% 71.42%

90nm 100 41 28 59% 72%

65nm 20 9.6 2.8 52% 86%

Table 5.4 Results of AOI for various technologies

Fig 5.13 Input output waveforms of AOI

5.4.1 AOI Gate simulation results for 180nm technology

64

Fig 5.14(a) Simulation graph of BASECASE AOI GATE in 180nm technology.

Fig 5.14(b) Simulation graph of LECTOR AOI GATE in 180nm technology.

65

Fig 5.14(c) Simulation graph of LCPMOS AOI GATE in 180nm technology.


Fig 5.15(a) Simulation graph of BASECASE AOI GATE in 90nm technology.

66

Fig 5.15(b) Simulation graph of LECTOR AOI GATE in 90nm technology.



67

Fig 5.16(a) Simulation graph of BASE CASE AOI GATE in 65nm technology.

Fig 5.15(b) Simulation graph of LCPMOS AOI GATE in 65nm technology.

68


180nm 90nm 65nm0

50

100

150

200

250


TECHNOLOGY SCALING

LEA

KA

GE P

OW

ER

IN

(uW

)

Figure 5.17 Plot of leakage Power for AOI in various technologies

69

CONCLUSION AND FUTURE SCOPE

The scaling down of device dimensions, supply voltage, and threshold voltage for

achieving high performance and low dynamic power dissipation has largely contributed to

the increase in leakage power dissipation. With deep-submicron and nanometer

technologies, the leakage current becomes more critical in portable systems where battery

life is of primary concern.

In nanometer scale CMOS technology, sub-threshold leakage power is compatible

to dynamic power consumption, and thus handling leakage power is a great challenge. In

this thesis, we present a new circuit structure named “LCPMOS” to tackle the leakage

problem. LCPMOS yields better leakage reduction as the threshold voltage decreases and

hence aids in further reduction of supply voltage and minimization of transistor sizes.

LCPMOS uses one additional transistor. Compared to other leakage reduction techniques,

like LECTOR ,sleepy stack, sleepy keeper, etc, LCPMOS achieves leakage power

reduction but with the advantage of not effecting the dynamic power as this technique

does not having any additional control and monitoring circuitry like in sleep techniques

and it also maintains exact logic state.

The LCPMOS technique can retain logic state, so it can be used for both generic

logic circuits as well as memories, i.e., SRAM. When applied to generic logic circuits, the

LCPMOS technique achieves up to 85-90% leakage reduction over the conventional

circuits without affecting the dynamic power.

As technology tends to scale down towards deep sub-micron era i.e., 22nm, 16nm,

12nm etc, there is much necessity of techniques such as LCPMOS which plays a

prominent role in decreasing the static power which is the dominant factor in the total

power. Methods to decrease the delay which will also be prominent part in the techniques

as going down the technology should be investigated; which can be considered as future

work.

70

BIBLIOGRAPHY

BIBLIOGRAPHY

71

1. H. Narender and R. Nagarajan, “LECTOR: A technique for leakage reduction in

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72

http://www.electronics-tutorials.ws/logic/logic_1.html

http://en.wikipedia.org/wiki/CMOS