LC Voltage-Controlled Oscillators

LC VoltageLC Voltage--Controlled OscillatorsControlled OscillatorsZhangwen Tang

Advisor : Professor Hao Min

[email protected], http://10.12.240.202

Jun. 4th, 2004

ASIC & System State-Key Laboratory, Fudan University

Copyright © 2001-2004, All Rights Reserved by Zhangwen Tang

-2-ASIC & System State-Key Laboratory, Fudan University

http://10.12.240.202, Copyright © 2001-2004, Zhangwen Tang

ContentContentIntroductionFundamentals of LC VCOs On-chip inductorsVaractors and F-V tuning curve Optimization of LC VCOsTechniques of lowering phase noiseDesign examplesConclusion and prospect



IntroductionIntroduction

PLL

Band LimitedFilter LNA

FirstVCO

Up ConversionMixer Image-

RejectedFilter

AGC

DLIF Architecture of TV tuner for DVB system

SecondVCO

Down ConversionMixer

IF

Off-Chip

Local Oscillators

Novel Architecture for CMOS TV Tuner: DLIFDouble Conversions with Low IF

Discrete TV Tuner Module



PFD LPF

92~158÷ 50÷

PFD LPF

4253~4387÷

12.5MHz

250KHz

LO1

LO2

1150－1975MHz

1063.5－1096.5MHz

LC Tank VCO

LC Tank VCO

Frequency SynthesizersFrequency Synthesizers



2L

C

Vc

Mn1 Mn2

Mp1 Mp2

Mn3

C

High Q, Low Parasitic Resistor Inductors High Q, High Tuning Range MOS Varators

LC VoltageLC Voltage--Controlled OscillatorsControlled Oscillators

CMOS Complementary Cross-coupled –Gm LC VCO

Design issues• Low phase noise• Low power• Wideband tuning range • F-V tuning curve • Quadrature output• etc …



OutlineOutlineIntroductionFundamentals of LC VCOs

Oscillator viewsMathematics of LC VCOsStructures of different LC-VCOs

On-chip inductorsVaractors and F-V tuning curve Optimization of LC VCOsTechniques of lowering phase noiseDesign examplesConclusion and prospect



Oscillator ViewsOscillator Views

( )H s∑inV outV

Two-port view : feedback system One-port view : Negative Resistance

CP RPLPActiveCircuit

RP

( ) ( )( )

=+1

out

in

H sV sV H s

Transfer function

= −active PR R

Active circuit

Barkhausen criterion

( ) ( )ω ω≥ ∠ = °0 01 & 180H j H j ωω

= −1j L

j C

Inductance cancels capacitance



Ring Oscillator and LC OscillatorRing Oscillator and LC Oscillator

+ -

- +

+ -

- +

+ -

- +

A1 A2 An…

Ring oscillator LC-Tank oscillator

Transfer function

( )ωω

= −⎛ ⎞+⎜ ⎟

⎝ ⎠

0

0

1

n

n

AH sj

ω ω°⎛ ⎞

= ⋅ ⎜ ⎟⎝ ⎠

0180tanosc N

°⎛ ⎞⎛ ⎞= + ⎜ ⎟⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

2

01801 tanA

N

Mn1 Mn2

CP

RP

LP

−2

mg

X Y

•Advantage: Large tuning range•Disadvantage: High phase noise

•Advantage: Low phase noise•Disadvantage: Small tuning range

Inductors &MOS Varactor designs



Mathematics of LC Mathematics of LC VCOsVCOs

outω

ctrlV

0ω

1ω

2ω

1V 2V

VKslope

0out V ctrlK Vω ω= + ⋅

( )ex V

ctrl

KsV sφ

=

F-V characteristic function

An ideal integrator in Phase-Locked Loop

Performance parametersCenter frequencyTuning rangeVoltage-controlled gainTuning linearityPhase noiseOscillating amplitudePower dissipation



Narrowband LC Narrowband LC VCOsVCOs

2L

Vc

Mn1 Mn2

Mp1 Mp2

Mn3

CV

LL

Cv

Vc

Mn2Mn1

Itail

Vdd

Vdd

Mn3Itail

Y

Vdd Vdd X Y

Vdd Vdd

VssVss

X

Cfix Cfix Cfix Cfix

Cv CV

NMOS-only –Gm LC VCO Complementary MOS –Gm LC VCO

[Ali Hajimiri, JSSC, May, 1999]



Wideband LC Wideband LC VCOsVCOs

LL

CVCv

Vc

Mn2

Itail

Vdd

Mn3

YX

Cfix

Mn1

C2C4C8C

B0B1B2B3

W/L2W/L4W/L8W/L

8Cd 4Cd2Cd Cd

C 2C 4C 8C

B0 B1 B2 B3

W/L 2W/L 4W/L 8W/L

8Cd4Cd2CdCd

Wideband LC VCO with Switched CapacitorsTradeoffs

MIM capacitorSwitched NMOS transistorQuality of capacitors

[A, Kral, A.A. Abidi, CICC, 1998]



QuadratureQuadrature LC LC VCOsVCOs

Vdd

ItailMp

L1 L2C1 C2

LL

Cv

Vc

Mn2Mn1

X2X1

Cfix Cfix

Cv

LL

Cv

Vc

Mn4Mn3

X4X3

Cfix Cfix

Cv

S1 S2

Quadrature LC VCO with Superharmonic coupling

[S. L. J. Gierkink, JSSC, July, 2003]

Superharmonic couplingat Common-mode, S1 & S2Very simpletwo same LC-VCOsLow phase noiseLow power dissipation



OutlineOutlineIntroductionFundamentals of LC VCOsOn-chip inductors

Inductor’s ClassModeling of on-chip inductors Optimization of equivalent capacitanceQuality Factor improvement

Varactors and F-V tuning curve Optimization of LC VCOsTechniques of lowering phase noiseDesign examplesConclusion and prospect



Three types of On-chip inductors

Gyrator-based active inductors(a) single-ended，(b) floating configurations

Bondwire inductors

On-chip spiral inductors

InductorInductor’’s Classs Class



Planar Spiral InductorPlanar Spiral Inductor

Number of tuners, nMetal width, wSpacing, sOuter diameter, dout

Inner diameter, din

Fill ratio, Number of sides, N

(a) Square Spiral (b) Hexagonal Spiral

(c) Octagonal Spiral (d) Circular Spiral

( )/( )out in out ind d d dρ= − +



Multilayer Spiral InductorMultilayer Spiral Inductor

5M

4M

3M

5M

4M

5M

4M

3M

5M

3M

Stacked spiral inductor Miniature 3D spiral inductor

Differential multilayer inductor

[A. Zolfaghari, B. Razavi, JSSC, April, 2001] [C.C Tang, S.I. Liu, JSSC, April, 2002]



Modeling of OnModeling of On--chip Inductorschip InductorsCharacteristic of inductance of a typical

integrated inductors with frequencyEM Field Solver

High accuracyVery slowComplex for Spice

Segmental circuit modelsSimpler than EM field solverEasy integration into Spice

Compact, scalable, lumped circuit models

Simple, versatile and robustPhysical intuition



Optimization of Equivalent CapacitanceOptimization of Equivalent CapacitanceWhat is the equivalent capacitance

At resonance frequency, the peak magnetic and electric energies are equal.Given a peak voltage V0, electric energy is

First resonance frequency fSR

The proposed equivalent capacitance modelsElectric energy in interlayer metals, CM-M

Electric energy in single metal to substrate, CM-S

20 2eqC V

( ) 12SR eq eqf L Cπ

−=



Electric Energy in CElectric Energy in CMM--MM and Cand CMM--SS

1 2V V−

i

i

CC

CCCC

C

C

C

1 2V V−nM

1nM −

1V

2V

i

CC

CCCC

CnM

1V

C C

Substrate

2V2V

1V1 2V V V∆ = −

CM-M

CM-S

1

2, ,

1 1

21 2

12

1 ( )2

m m

n n

N N

e C e C m Cm m

M M

E E C V

C wl V V−

= =

−

= =

= −

∑ ∑

2, ,

1 1

21

1

2 21 2 1 2

12

1 ( )2

16

m m

n

n

N N

eC eC m Cm m

NM S

m

N

M S

E E C V

C wl mV VN N

C wl V V VV

= =

−

=

→∞

−

= =

= − ∆

≈ + +

∑ ∑

∑

Electric Energy

Electric Energy



Voltage ProfileVoltage Profile

5M

4M

1C

2C

Substrate

5M

4M

1C

2C

Substrate

0V

0

2V

,1M SC −

1st Turn 2nd Turn 3rd Turn,1M MC −

,2M SC −

,2M MC −

,3M MC −

,3M SC −

Top

Top

Top

Bottom

BottomBottom

0V

0

2V ,1M MC − ,2M MC −

,3M MC −

,3M SC −

,2M SC −

,1M SC −

1st Turn 2nd Turn 3rd Turn

Stacked

Miniature 3D

[A. Zolfaghari, B. Razavi, JSSC, April, 2001]

[C.C Tang, S.I. Liu, JSSC, April, 2002]



Capacitance CoefficientsCapacitance Coefficients

Stacked

Miniature 3D

1κ 2κ

1 1 2 2eqC C Cκ κ= +

Higher fSR

Small Area

3D or Stacked



Pattern ground shield

Dual reverse-bias PN-junction isolation in deep NwellStop eddy current in skin channel

Quality Factor ImprovementQuality Factor ImprovementMultipath metal

DNW

NWELL

DNW

NWELL NWELL

Psub

PWELL PWELL

Deep Nwell Process

Vdd Gnd

Gnd



OutlineOutlineIntroductionFundamentals of LC VCOsOn-chip inductorsVaractors and F-V tuning curve

Varactors’ classPeriod calculation of LC VCO with step-like varactors

Optimization of LC VCOsTechniques of lowering phase noiseDesign examplesConclusion and prospect



VaractorsVaractors’’ ClassClass

n-well

P+N+ N+

n-well

P+P+ N+

n-well

N+N+

n-well

P+P+ N+

(b) D=S=B MOS(a) p+/n-well Junction

(c) Inversion MOS (d) Accumulation MOS

G

G

G VddVctrl

Vctrl

GVctrl

Vctrl

p-sub p-sub

p-subp-sub

Four Types of Varactors in Silicon CMOS: PN Junction, Standard MOS, Inversion-MOS, Accumulation-MOS



DC Capacitance of MOS DC Capacitance of MOS VaractorsVaractorsD

C C

apac

itanc

e C

ss

DC

Cap

acita

nce

Css

DC

Cap

acita

nce

Css

(a) S=D=B PMOS Varactor (b) Inversion PMOS Varactor (c) Accumulation NMOS Varactor

Vgs@Vctrl=1.65V Vgs@Vctrl=1.65V Vgb@Vctrl=1.65V

2.0p

1.8p

1.6p

1.4p

1.2p

1.0p

0.8p

2.0p

1.8p

1.6p

1.4p

1.2p

1.0p

0.8p

0.6p

2.0p

1.8p

1.6p

1.4p

1.2p

1.0p

0.8p

0 1 2 3 0 1 2 30 1 2 3



StepStep--like like VaractorsVaractors

( ) max effss

min eff

C V VC V

C V V≥⎧

= ⎨ ≤⎩eff G ctrl THV V V V= − −Effective control voltage

( ) ( )= + + − −1 1( ) ( )2 2ss max min max min effC V C C C C sign V V

Small-signal capacitance of step-like varactors

L

Css(V)

Vdd

Vctrl

Cmax

Cmin

VC

1

-1

0

V

Css(V) sign(V)

(a) Serial LC Tank (b) Step-like Varactor (c) Unit Step Function

Vout

Veff



Oscillating Waveforms in LCOscillating Waveforms in LC--TankTank

I-V locus of Step-like varactorOscillating waveforms at different Veff

Two ellipses of different sizes joint with a step transition at Veff

Vdc

Region (2)

Region (4)

Region (3)

Region (1)

Veff=3.5V

Veff=3.0V

Veff=2.0V

Veff=2.5V

T2T1

T

Veff=2.00VVeff=2.25VVeff=2.50VVeff=2.75VVeff=3.00VVeff=3.25VVeff=3.50V

Amin Amax

Imax



Oscillating Period CalculationOscillating Period Calculation

Vvdd<Veff <Vvdd＋Amax

Vvdd－Amin<Veff <Vvdd

Veff> Vvdd＋Amax

Veff<Vvdd－Amin

Oscillating Period of LC TankEffective Control Voltage, Veff

2max maxT T LCπ= =

2min minT T LCπ= =

( )1

1 12

eff effmax min max min

min max

V VT T T asin T asin T

A Aπ θ⎛ ⎞⎛ ⎞ ⎛ ⎞

= + + −⎜ ⎟⎜ ⎟ ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠⎝ ⎠

Ellipse Similar Factor22

1 1 eff eff

min max

V VA A

θ⎛ ⎞⎛ ⎞

= − + ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠

( )2

1 12

eff effmax min max min

min max

V VT T T asin T asin TA Aπ θ

⎛ ⎞⎛ ⎞⎛ ⎞= + + − +⎜ ⎟⎜ ⎟⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠⎝ ⎠

Ellipse Similar Factor2 2

2 1 eff eff

max min

V VA A

θ⎛ ⎞ ⎛ ⎞

= − +⎜ ⎟ ⎜ ⎟⎝ ⎠⎝ ⎠



Simulation Verification in HSPICESimulation Verification in HSPICE

L=10nH; Vdc=2.5VFmax=1.591GHz; Fmin=0.795GHzCmin=1.0pf; Cmax=4.0pf

Simulation agrees well with the proposed calculation



Comparison with OthersComparison with Others’’ ModelModel

Hegazi’s effective capacitance model

( ) ( )21 1 1

2eff eff eff

eff max min min maxV V VC C C C C asinA A Aπ

⎛ ⎞⎛ ⎞ ⎛ ⎞ ⎛ ⎞⎜ ⎟= + + − + −⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎝ ⎠

Point A

Point B

⋅=

+,2 min max

eff Amin max

F FFF F

⋅=

+, 2 2

2 min maxeff B

min max

F FFF F

The reasons for difference between two method:a) Hegazi’s model is small-signal analysis; b) Neglect 2rd and higher order harmonics;

[E. Hegazi, A.A. Abidi, JSSC, June, 2003]

L=10nH; Vdc=2.5VFmax=1.591GHz; Fmin=0.795GHzCmin=1.0pf; Cmax=4.0pf

Amin=1.0V

Amin=0.5V

Amin=0.25V

feff of Our CaculationA

feff of the effective capacitance model

B

Vdc

≤, ,eff B eff AF F



Validation with OthersValidation with Others’’ LCLC--VCOsVCOs

[Y.B. Choi, 5th ASICON, 2003] [H.L.Lao, 5th ASICON, 2003]

Frequency-Voltage Curves

L=2.825nH; Vdc=1.128VFmax=2.543GHz; Fmin=2.317GHzCmin=1.387pf; Cmax=1.671pfAmin=1.124V; Amax=1.233V

L=2.8nH; Vdc=0.742VFmax=3.984GHz; Fmin=3.537GHzCmin=0.570pf; Cmax=0.723pfAmin=0.749V; Amax=0.844V



OutlineOutlineIntroductionFundamentals of LC VCOsOn-chip inductorsVaractors and F-V tuning curveOptimization of LC VCOs

Low power design and low phase noise Underlying physics of LC oscillatorsOptimization method: Linear and Geometric Programming

Techniques of lowering phase noiseDesign examplesConclusion and prospect



LowLow--power Designpower Design

L C

RL RC

-R

L

C

R

RLC Tank2 2

2 2peak peakCV LI

=

Energy Conservation Theorem

The loss in RLC tank

2 2 2 20 2 2

0loss peak peak

RP RC V VL

ωω

= =0

1LC

ω =

Low-power designLower serial resistance RIncrease the tank inductanceWork at high frequency

0

0

1 1tank

L LQR CR R Cω

ω= = =

[M. Tiebout, JSSC, Jul. 2001]



LowLow--phasephase--noise Designnoise Design

( )20

2 22 sig

KTLP Q

ωω

ω∆ ∝

∆

Phase noise (SSCR)

Low-phase-noise designLower serial resistance RIncrease the tank inductanceIncrease amplitude voltage

( )3

2 2 2peak

KT RLV L

ωω

∆ ∝∆

0

0

1 1tank

L LQR CR R Cω

ω= = =

tankQ



Underlying Physics of LC OscillatorsUnderlying Physics of LC Oscillators

2L

Vc

Mn1 Mn2

Mp1 Mp2

Mn3

CV

Vdd

Itail

X Y

CV

C Li(t)

Itail

-Itail

i(t)

tankgactiveg- Current limited

Voltage limited

Vdd=2.5V

Vdd=2.0V

Vdd=1.5V

(4 / ) ( )( )

bias tanktank

limit

I g I limitedV

V V limitedπ −⎧

= ⎨ −⎩

tankV

limitV

voltage limited−

Inductance limited−

2L 1L

2A 1A

>2 1tank tank

E E

L

20

( )2( )

tanktank

limit

L limitedE LVV limitedV

ω⎧ −⎪= ⎨ −⎪⎩[A. Hajimiri, JSSC, May 1999]



NoiseNoise--toto--Carrier Rate, NCRCarrier Rate, NCR

2 / 2 / 2nC v KT⟨ ⟩ =

CR C L R2 2

0nKTv KT LC

ω⟨ ⟩ = =

The equipartition theorem of thermodynamics states that:Any system in equilibrium has a mean energy of KT/2

2

2

1 ( )( )

tankn

tank

E L limitedvV L V limited

−⎧⟨ ⟩∝ ⎨ −⎩

2 2 2 2/ / ( )tank tail tank tail LE I Lg I Lg L limited∝ ≈ −

2 22

2

( )/( )

L tailn

tank

L limitedLg IvV V limitedL

−⎧⟨ ⟩∝ ⎨ −⎩

[D. Ham and A. Hajimiri, JSSC, Jun. 2001]



Design Insight2LLg

L

tankV

limitedV

,tank minV

NCR

minNCR

optL

feasiblenon feasible−

2LLg

L

tankV

limitedV

,tankminV

NCR

minNCR

optLvoltage linited−inductance limited−

(a) (b)

L L

L L

2LLg increasing with L

Startup conditionMinimum tank amplitudeOptimization at feasible point

descreasing with LOptimization at the verge of inductance-limited and voltage-limited regime

2LLg



12 initial design variablesMOS transistors

On-chip spiral inductors

MOSCAP varators

Load cap and tail current

loadC loadC

L s pC C C= + L s pC C C= +

pR pR

L LsR sR

vRvRvC vC

NMOS PMOSC C+ NMOS PMOSC C+

( )mn mpg g− + ( )mn mpg g− +

on opg g+ on opg g+

SpiralInductor

MOSVarators

NMOS &PMOS

Transistors

LC VCO TopologyLC VCO Topology

Equivalent oscillator model

, ,v max v minC C

load tailC I

n n p pW L W L

outd w s n



LC VCO ParametersLC VCO ParameterssC

pR pRpC pC

L sR

vRvC

n-well

N+N+

GVctrl

p-sub

G Vctrl

21 /( )L p sg R R Lω= +

( ) /v v vg C Qω=

2 tank on op v Lg g g g g= + + + 2 active mn mpg g g= +

2tamnkL L= 2 tank PMOS NMOS L v loadC C C C C C= + + + +

, , ,4NMOS gs n db n gd nC C C C= + + , , ,4PMOS gs p db p gd pC C C C= + +



Design ConstraintsDesign Constraints(1) Power dissipation

(2) Oscillator voltage amplitude

(3) Tuning range

(4) Startup condition

(5) Maximum diameter of spiral inductor

etc. …

tail maxI I≤

,,

2 2tail tail tailtank tank min

tank max on op v L L

I I IV Vg g g g g g

= = ≈ ≥+ + +

, ,2 2

1 1tamnk tank min tank tank max

max min

L C L Cω ω

≤ ≥

( ) ( ), 2max min t min max minrω ω ω ω ω ω− = + =

,active min tank maxg gα≥

maxd d≤



Phase Noise OptimizationPhase Noise Optimization

2 2

2

2

( )

( )

L

tail

tail

sunpply

L gL limitedI

LL I V limited

V

ω

⎧−⎪

⎪∆ ∝ ⎨⎪ −⎪⎩

In 1/f2 region, Phase noise (SSCR)

2

4

2

2

1( )

( )

s

tail

tail

sunpply

RL limited

L IL

L I V limitedV

ωω

⎧⎛ ⎞⋅ −⎪⎜ ⎟

⎝ ⎠⎪∆ ∝ ⎨⎪ −⎪⎩

( )22/( ) s

L sR

Lg L R LL

ωω

≈ =

Design strategyLower Rs/L of on-chip inductor, or select high QL inductorAt maximum current Imax

At verge of inductance-limited and voltage-limited regime

[D. Ham, and A. Hajimiri, JSSC, 2001] Proposed optimization equation



0 20 40 60 80 100

4

3

2

1

0

Wn (μm)

Cv(p

F)

T.R.1

T.R.2

Tank amplitude

start-up

Inductance/current-limited

voltage-limited

min 3α < min 3α ≥

A

B

C

regime-divider

0 20 40 60 80 100

4

3

2

1

0

Wn (μm)

Cv(p

F)

T.R.1

T.R.2 Tank amplitude

start-up

A

B

C

Graphical OptimizationGraphical Optimization

Lower Rs/L in on-chip inductor, Decrease or increase Itail



Geometric ProgrammingWhat?

2 2

2 210 log2

rms n

max

i fLq

ωω

⎛ ⎞Γ ∆∆ = ⋅ ⋅⎜ ⎟⎜ ⎟⋅ ∆⎝ ⎠

00 0

1( ) ( )

2 n nn

c c cos nω τ ω τ θ∞

=

Γ = + +∑ 2 22 2

00

1 ( ) 2n rmsn

c x dxπ

π

∞

=

= Γ = Γ∑ ∫

Object Function: phase noise



OutlineOutlineIntroductionFundamentals of LC VCOsOn-chip inductorsVaractors and F-V tuning curveOptimization of LC VCOsTechniques of lowering phase noise

Limited noise factor for white noiseNoise filtering techniquesInductive control voltage

Design examplesConclusion and prospect



Limited Noise Factor for White NoiseLimited Noise Factor for White NoiseVdd

Mp1 Mp2

Mn1 Mn2

Mn3

LRs

21pi

22pi

21ni

22ni

2taili

2sRv

C

2sRvRsL

ωω

ω

⎛ ⎞⎜ ⎟ ⎛ ⎞⎛ ⎞∆⎜ ⎟∆ = ⋅ = ⋅ ⎜ ⎟⎜ ⎟⎜ ⎟⎜ ⎟ ∆⎝ ⎠⎝ ⎠⎜ ⎟⎝ ⎠

2, 2

0210 log 10 log

2

n SSBP

sig sig

vR KTfL F

P P Q

Phase noise

γ γγ

+⎛ ⎞= = + = +⎜ ⎟

⎝ ⎠1 1

2n pN

P

RFR

Limited noise factor

C RPL

-RG

2

4nN

VKTR

f=

∆

[F. Herzel and M .Tiebout, TCASII, Jan. 2000]



Noise Sources of CloseNoise Sources of Close--in Phase Noisein Phase Noise

L ω∆

ω∆

3

1f

2

1f

31f

ω∆

210logs

FkTP

⎛ ⎞⎜ ⎟⎝ ⎠

Flicker noise of tail currentAM-FM modulation

Flicker noise of differential pairsDifferential pairs looks like a “Mixer”.Flicker noise modulates the basebandand 2nd harmonics voltage at the tail.

Varactor nonlinearityAM-FM modulation of common noise, power and substrate noise.

ωω

ωω ω

⎧ ⎫⎡ ⎤ ∆⎛ ⎞⎛ ⎞⎪ ⎪⎢ ⎥∆ = ⋅ ⋅ + ⋅ +⎜ ⎟⎨ ⎬⎜ ⎟ ⎜ ⎟∆ ∆⎢ ⎥⎝ ⎠⎪ ⎪⎝ ⎠⎣ ⎦⎩ ⎭

32

10210 log 1 12

f

s L

FkTLP Q

Leeson’s model



Noise Filtering Techniques (1)Noise Filtering Techniques (1)

Lower channel length modulationFiltering noise from tail current

[A. Hajimiri, JSSC, May. 1999]

Large capacitor filter at common nodeVdd

Mp1 Mp2

Mn1 Mn2

Mn3

C

L

X Y

S

Ctail

VX VY

VS

VX VY

VS

Without large capacitor

With large capacitor



Noise Filtering Techniques (2)Noise Filtering Techniques (2)Remove of tail current

Vdd

Mp1 Mp2

Mn1 Mn2

C

L

X Y

S

Vdd

Mp1 Mp2

Mn1 Mn2

Mn3

C

L

X Y

S

Output Voltage

Load Impedance Load Impedance

Output Voltage

(a) Without tail current (b) With tail current

Off Triode Zero

High

Low

High

Roles of the tail current:Supply DC currentBoost high impedance at common-source nodeAvoiding Q-degradation by triode region FETs

[S. Levantino, JSSC, Aug. 2002]



Noise Filtering Techniques (3)Noise Filtering Techniques (3)LC filter at 2nd harmonic

V d d

M p 1 M p 2

M n 1 M n 2

M n 3

C

L

X Y

S 1

C ta il

V XV Y

V S 1

C 1

C 2

L 1

L 2

S 2

V S 2

N o isea t ω 02

[E. Hegazi, JSSC, Dec. 2001]

L1 & C1, L2 & C2 resonates at 2nd harnonicBoost the impedance at each common-source node, avoiding Q-degradationImprove the oscillating amplitude voltage, and voltage-limited moves into current-limited



Inductive Control Voltage (Proposed)Inductive Control Voltage (Proposed)

Vctrl

CV CV

Vdd

Mp1 Mp2

Mn1 Mn2

Mn3

L

X Y

S1

Ctail

C1

C2

L1

L2

S2

C3

L3

S3

VX VY

VS1

VS2

VS3Vctrl

L3 & C3 resonates at 2nd harnonicLower even harmonics in oscillating voltageThe oscillating voltage is more symmetric in one period



OutlineOutlineIntroductionFundamentals of LC VCOsOn-chip inductorsVaractors and F-V tuning curveOptimization of LC VCOsTechniques of lowering phase noiseDesign examples

1.08 GHz narrow LC VCO1.0-2.0 GHz wideband LC VCO

Conclusion and prospect



Example I : 1.08GHz Narrowband LC VCOExample I : 1.08GHz Narrowband LC VCO

Chartered CMOS 0.35µm 2P4M RF/MS process72-side inductor and A-MOS Varactor in Chartered libraryDie Size: 1120µm×820µm



Simulation and Measurement of FSimulation and Measurement of F--V Curve V Curve

L=5.755nH; V0=2.208VFmax=1.164GHz; Fmin=0.970GHzCmin=3.247pf; Cmax=4.675pfAmin=0.811V; Amax=0.973V

L=5.760nH; V0=2.083VFmax=1.134GHz; Fmin=0.978GHzCmin=3.421pf; Cmax=4.610pfAmin=0.860V; Amax=1.000V

NM5 NM6LC VCOCore

Bias-T

Vdd

Bias-T

Vdd

Spectrum Analyzer50Ωmatching

Bias Current

Test

Simulation Measurement



Phase Noise (Simulation)Phase Noise (Simulation)

Simulation in Cadence SpectreRF : Bias at 3.1mAPhase Noise < -82.2dBc/Hz@10kHz

-84dBc

-108.6dBc

-129.3dBc

1/f3 Region

1/f2 Region

±8.9%Tuning Range

-82.2dBc/Hz@10kHz-108dBc/Hz@10kHz

-129.3dBc/Hz@10kHz

Phase Noise(Simulation)

945MHz-1137MHzOscillating Frequency

3.1mACurrent

3.3VPower Voltage



Example II : 1Example II : 1--2 GHz Wideband LC VCO2 GHz Wideband LC VCO

Switched-Capacitor ArrayLC

OscillatorCore

Switched-Current

Array

Encoder

LC oscillator coreSwitched-capacitor arraySwitched-current arrayEncoder



Differential OnDifferential On--Chip InductorChip Inductor

G GG

GG GS S

S S

OPENTHRU P+

NW

GS

S G

G

G

GL12

>5Single-end Q

5.2nHInductance

1.5 µmSpacing

15 µmWidth

5Turns

16Sides

100µmCore Diameter

De-embeded PAD

Single-end Q

Single-end Inductance



Simulation and Measurement of FSimulation and Measurement of F--V CurveV Curve

Simulation

Measurement



Phase Noise (Simulation)Phase Noise (Simulation)

Simulation in Cadence SpectreRF : Bias at 1.15mAPhase Noise < -80dBc/Hz@10kHzDie Size: 1120µm×1200µm

1/f3 Region

1/f2 Region

-79dBc

-104.4dBc

-125.3dBc

±31%Tuning Range

-79dBc/[email protected]/[email protected]/Hz@10kHz

Phase Noise(Simulation)

1041MHz-1968MHzOscillating Frequency

3.5-10mACurrent

3.3VPower Voltage



PFTN (PFTN (PowerPower--FrequencyFrequency--TuningTuning--NormalizedNormalized))

( )⎡ ⎤⎛ ⎞⎢ ⎥= −⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦

2

sup

10log tuneoff

off

fkTPFTN L fP f

[email protected][20]








[email protected]

[email protected]

OrderPFTN(dB)

Phase noise(dBc/Hz)

Fo(GHz)

ftune(MHz)

Power(mW)

Process(µm)

Reference



ConclusionsConclusionsOn-chip inductors

Equivalent capacitanceDifferential multilayer inductorQuality factor improvement techniques

Varactors and F-V tuning curvePeriod calculation of LC-VCO with step-like varactor

Optimization of LC VCOHigh Q inductor, Lower Rs/L in on-chip inductor

Techniques of lowering phase noiseInductive control voltage

Two design examples



Prospect(1):Prospect(1): Switched MIMSwitched MIM--Cap Cap Varactor Varactor

C1//C2

C1

VTH VC

Css(V)

C-V Curve

Switched MIM-Cap

Direct Model

Cross Model

C2

G

Vc

C1

M1

C2 C2

Vdd

X Y

Vdd

C2 C2

Vdd

X Y

Vdd

Vc

Vc

C1 C1

C1 C1

M1 M2

M1 M2



Prospect(2):Prospect(2): VaractorVaractor and and VaructorVaructor

Variable Resonator: Varactor Variable Inductor: Vaructor

C2

G

Vc

C1

M1 L1

Vdd

Y

VL

L2

M1



1.08GHz LC VCO with MIM 1.08GHz LC VCO with MIM VaractorsVaractors

TSMC CMOS 0.25um 1P5M RF/MS Process

Simulation in SpectreRFF-V curves, 3.3mAPhase Noise < -89.7dBc/Hz@10kHz

Better phase noise in LC-VCO with MIM Varactor than in one with MOS VaractorSimulation agrees well with the calculationTSMC 0.25µm 2P5M RF/MS process



AcknowledgementsAcknowledgements

Prof. Hao Min (Adivsor), Fudan UniversityProf. Chengshou Sun, Guoquang Zhang, Feng Zhou, Wenhong Li, Fudan UniversityProf. Qianling Zhang, Junyan Ren, Zengyu Zheng, Lianxing Yang, Zhiliang Hong, Dian Zhou, Fudan UniversityProf. Lingling Sun, Jiang Hu, HIZEE University Fuxiao Li, Zhengyu Zhu, No. 55 Institute of Science and TechnologyProf. Xiaowei Sun, Rong Qian, Shanghai Institute of M.S & IT Hongyan Jian, Jie He, Shi Shu, Fengling Yang, TV Tuner GroupQiang Li, Yifeng Han, RFID Group, Haiqing Zhang, Yawei GuoMPW service at ICCSupported in part by Shanghai Science & Technology Committee under SDC Project Supported in part by Fudan-Infineon Joint Lab



Thanks!Thanks!

LC Voltage-Controlled Oscillators

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