Laxmi Institute of Technology , Sarigam Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad TEACHING SCHEME SYLLABUS Unit Topics Teaching Hours Module Weightage I Number Systems: Decimal, Binary, octal, and hexa- decimal number, systems, binary arithmetic. Number base conversion, Complements Codes: Binary code, excess-3 code, gray code, error detection and correction codes. 07 20 2 Logic families: Positive logic and Negative Logic, AND, OR,NOT,NAND,NOR, X-OR GATE, INHIBIT CIRCUIT, Significance and type like TTL, CMOS, interface with different logic families, application relevant information, electrical characteristics, 04 08 3 Boolean Algebra: Introduction, Logic Operators, Postulates and theorems, properties –Product of Sums and Sum of Products– Karnaugh Map method – Two, three, four, five variable K-maps, Converting Boolean expressions to Logic and Vice versa, NAND and NOR implementation – Don’t-Care conditions – The tabulation method 10 20 4 Combinational Logic Circuit: Half and full Adder – Half and full Subtracter – Binary parallel adder– BCD Adder, Decimal adder – Magnitude comparator – Encoders & Decoders – Multiplexers–De- multiplexer 06 14 5 Flip Flops and Sequential Logic and Circuits: Basic difference between Combinational logic and Sequential logic –Flip-Flops like S-R , J-K, D, Master Slave– Triggering of (level andEdge) flip-flops –Asynchronous and Synchronous Inputs –Excitation tables for flip-flops 07 15 Semester Course Title Course Code Theory Paper L T P 4 Digital Electronics 2140910 4 0 2 70
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Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad
TEACHING SCHEME
SYLLABUS
Unit Topics Teaching Hours
Module Weightage
I Number Systems: Decimal, Binary, octal, and hexa-decimal number, systems, binary arithmetic. Number base conversion, Complements Codes: Binary code, excess-3 code, gray code, error detection and correction codes.
07 20
2 Logic families: Positive logic and Negative Logic, AND, OR,NOT,NAND,NOR, X-OR GATE, INHIBIT CIRCUIT, Significance and type like TTL, CMOS, interface with different logic families, application relevant information, electrical characteristics,
04 08
3 Boolean Algebra: Introduction, Logic Operators, Postulates and theorems, properties –Product of Sums and Sum of Products– Karnaugh Map method – Two, three, four, five variable K-maps, Converting Boolean expressions to Logic and Vice versa, NAND and NOR implementation – Don’t-Care conditions – The tabulation method
10 20
4 Combinational Logic Circuit: Half and full Adder – Half and full Subtracter – Binary
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad
Subject In Charge Head of the Dept.
Total Planned Lectures 48
Total Actual Lectures
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad
Mid semester -1 : Examination Paper:
Laxmi Institute of Technology , Sarigam Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmedabad
Academic Year 2018-19 Centre Code: 086 Examination : Mid Semester Examination Branch: EE Semester: 4 Sub Code: 2140910 Sub: Digital Electronics Date: 01/02/2019 Time:- 9:00 am TO 10:00am Marks: 20 Note: Attempt any TWO QUESTION
Q.1
Do as given direction: marks 1. (43)8 =( )10= ( )2 2 2. ( B9F.AE)16= ( )8 1 3. (214)10= ( )8 1 4. (10110)2=( )10=( )16 2 5. Find 1’s and 2’s complement of given binary number: (10110010)2 2 6. Compare BCD & binary Codes. State advantage & disadvantage of the same. 2
Q-2
Do as given direction: 1. Add ( 569) and (687) in BCD 3 2. Perform ( 83)10 – (21)10 using 9’s complement method 3 3. Convert (29)10 into Excess-3 and Gray code 2 4. Perform Subtraction using 2’s complement method: (1101101)2 – (11010)2 2
Q-3
Do as given direction: 1. Give the classification of Logic gates. Which gates can be consider as Universal Gate
and why? Implement Ex-OR gate using only NOR Gate. 4
2. Write the statement for De-Morgan’s theorem. Explain the terminology with logic diagram and Truth table.
3
3. What is hamming code. Write its limitations. Generate hamming code for 1 1 1 0 1 1 0 0 1 with even parity.
3
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad
Department of Electrical Engineering Academic Year : 2018 -2019
ASSIGNMENT – I
Name of the Subject: Digital Electronics Date: 02.01.2019 Subject Code : 2140910 S. No Question Remarks
2. How can we obtain one's and two's compliment of a binary ? Explain with example ?
3. Find out 2's compliment of the following numbers :- (1). ( 110110)2 (2). ( 010101 )2
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad Date of Submission: 09.01.2019
QUESTION BANK
UNIT- I
1) Convert the following numbers to decimal (i) (10001.101)2 (ii) (101011.11101)2 (iii) (0.365)8 (iv) A3E5 (v) CDA4 (vi) (11101.001)2 (vii) B2D4 2) Perform the operation of subtractions with the following binary numbers using 2’ complement (i) 10010 - 10011 (ii) 100 -110000 (iii) 11010 -10000 3) Define: Digital System Convert following Hexadecimal Number to Decimal : B28, FFF, F28 Convert following Octal Number to Hexadecimal and Binary: 414, 574, 725.25 4)Convert the following Numbers as directed: (1) (52)10 = ( )2 (2) (101001011)2 = ( )10 (3) (11101110) 2 = ( )8 (4) (68)10 = ( )16 5)Convert decimal 225.225 to binary ,octal and hexadecimal. 6) Represent the decimal number 8620 in BCD , Excess-3 , and Gray code 7) Convert the Decimal Number 250.5 to base 3, base 4, base 7 & base 16. 8) Perform the subtraction with the following decimal numbers using 1’s compliment and 2’s compliments. (a) 11010-1101 , (b) 10010-10011
UNIT- II
1) Obtain the simplified expressions in sum of products for the following Boolean functions: (i)F(A,B,C,D,E) =Σ(0,1,4,5,16,17,21,25,29) (ii) A’B’CE’+AB’C’D’+B’D’E’+B’CD’
2) Demonstrate by means of truth tables the validity of the following Theorems of Boolean algebra (i) De Morgan’s theorems for three variables
(ii) The Distributive law of + over-
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad 3) Implement the following Boolean functions (i) F= A (B +CD) +BC′ with NOR gates (ii) F= (A + B′) (CD + E) with NAND gates
3) Explain SOP and POS expression using suitable examples Reduce the expression:
(1) A+B(AC+(B+C’)D) (2) (A+(BC)’)’ (AB’+ABC)
4) Simplify the Boolean function: (1)F(w,x,y,z) = Σ (0,1,2,4,5,6,8,9,12,13,14)
(2)F(w,x,y) = Σ (0,1,3,4,5,7)
5) Explain with figures how NAND gate and NOR gate can be used as Universal gate. 6) Simplify the Boolean function:
1) F = A’B’C’+B’CD’+A’BCD’+AB’C’
2) F =A’B’D’+A’CD+A’BC d=A’BC’D+ACD+AB’D’ Where “d ” indicates Don’t care conditions.
7) What is the principle of Duality Theorem? 8) Explain briefly: standard SOP and POS forms. 9) What are Minterms and Maxterms? 10) Define: Noise margin , Propagation delay 11) Explain NAND and NOR as an universal gates 12) Give classification of Logic Families and compare CMOS and TTL families
13)Draw the logic symbol and construct the truth table for each of the following gates. [1] Two input NAND gate [2] Three input OR gate
[3] Three input EX-NOR gate [4] NOT gate
14) Explain briefly : SOP & POS , minterm & maxterm, canonical form,propagation delay, fan out 15) Given Boolean function F= x y + x′ y′ + y′ z 1. Implement it with only OR & NOT gates 2. Implement it with only AND & NOT gates 16) Express following Function in Product of Maxterms F(x,y,z)= ( xy + z ) ( y + xz ) 17) Simplify the following Boolean functions to a minimum numbers of literals. (a) xyz+x’y+xyz’ and (b)(A+B)’(A’+B’)’
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad 18) Simplify the following Boolean function using K-map F( w,x,y,z) = Σ( 1 , 3 , 7 , 11 , 15 )
with don’t care conditions d( w,x,y,z ) = Σ( 0, 2 ,5 ) 19) Simplify the following Boolean function by using Tabulation method.
F = Σ ( 0,1,2,8,10,11,14,15 ) 20) Simplify Boolean function F ( w,x,y,z ) = Σ ( 0,1,2,4,5,6,8,9,12,13,14 )using
K-map and Implement it using (i) NAND gates only (ii) NOR gates only
21) Determine the Prime Implicants of following Boolean Function using Tabulation Method. F(A,B,C,D,E,F,G)=Σ(20,28,38,39,52,60,102,103,127) 22) btain the simplified expression in sum of product for the following Boolean functions. (a) F= Σ(0,1,4,5,10,11,12,14) and(b) F=Σ(11,12,13,14,15). 23) Implement the functions F=Σ(1,3,7,11,15) with don’t care conditions d=Σ(0,2,5) Discuss the effect of don’t care conditions.
UNIT- III
1) Design a combinational circuit whose input is four bit binary number and output is the 2’s complement of the input binary number.
2) Design a combinational circuit that accepts a three bit binary number and generates an output binary number equal to the square of the input number.
3) Discuss 4-bit magnitude comparator in detail 4) With necessary sketch explain full adder in detail.
5) Design a 4 bit binary to BCD code converter 6) Implement Boolean expression for Ex-OR gate using NAND gates only 7) Convert decimal 8620 into BCD , excess-3 code and Gray code. 8) Design a full-adder with two half-adders and an OR gate . 9) Design a combinational circuit whose input is a four bit number and whose Output is the 2’s complement of the input number. 10) Design BCD to Excess-3 code converter using minimum number of NAND gates. 11) Design the Combinational Circuits for Binary to Gray Code Conversion. 12) Explain Design Procedure for Combinational Circuit & Difference between Combinational Circuit & Sequential Circuit. UNIT- IV
1) Explain half and full adders in detail. 2) Design and implement BCD to excess 3 code converter.
Laxmi Institute of Technology , Sarigam
Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad
3) Show how a full-adder can be converted to a full-subtractor with the addition of one inverter circuit.
4) Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generate the 9’s complement of the input digit.
UNIT- V
1) Draw the general model of sequential circuits and explain. 2) Compare synchronous and asynchronous sequential circuits. 3) Explain the analysis procedure for a state machine. 4) Write a note on the excitation tables of flip flops. 1) Discuss D- type edge triggered flip flop in detail. 2) With neat sketch explain the operation of clocked RS flip flop. 3) Draw and explain the working of following flip flops (a) Clocked RS (b) JK 4) Convert SR flip flop into JK flip flop 5) With logic diagram and truth table explain the working of JK flip flop. Also obtain its
characteristics equation. How JK flip flop is the refinement of RS flip flop? 6) Draw logic diagram, graphical symbol, and characteristic table for D flip flop. (3 marks) 7) Explain working of master slave JK flip flop with necessary logic diagram, state equation
and state diagram. 8) Design sequential circuit with JK flip flop to satisfy the following state equation.
9) Explain the procedure followed to analyze a clocked sequential circuit with suitable example.
UNIT- VI 1) Role of memory in computer system. 2) Explain RAM, ROM, EROPM, PROM EEPROM in detail. 3) Explain basic types and terminology of memory system.
UNIT- VII
1) Explain in detail digital to analog conversion analogy.
2) Explain in detail analog digital to conversion analogy.
3) Explain type of D/A conversion procedures.
4) Application of D/A and A/D technology.
1
Seat No.: ________ Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER–IV(New) EXAMINATION – SUMMER 2016
Subject Code:2140910 Date:30/05/2016 Subject Name:Digital Electronics Time:10:30 AM to 01:00 PM Total Marks: 70 Instructions:
1. Attempt all questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks.
Q.1 Short Questions 14
1 (365.24)8 = ( )10
(a) 542.5213 b) 245.5213 c) 245.3125 d) 542.3125
2 In design of ripple counter using J-K flip flop the inputs of all flip flop are
14 Race around condition occurs in J-K F/F when its inputs are
(a) J = 0, K = 0 (b) J = 0, K = 1 (c) J = 1, K= 0 (d) J = 1, K = 1
Q.2 (a) Perform the following subtraction by using 2’s, 9’s and 10’s compliments.
26 – 34
03
(b) Perform the following operations.
(1) 101.11 x 111.01 (2) (1110110) ÷ (101)
04
(c) Explain Hamming codes. A seven bit Hamming code is received as 1110101. What is
the correct code for even parity?
07
OR
(c) Write a short note on Gray code. 07
Q.3 (a) Define the following general characteristics of logic families. 03
2
(i) Propagation delay time (ii) Fan-in (iii) Fan - out
(b) Reduce the expression:
a) A + B (AC + (B+C’) D)
b) (A + (BC)’ )’(AB’ + ABC)
04
(c) Explain two input TTL NAND gate. 07
OR
Q.3 (a) Simplify the following Boolean function using K-map
F (w, x, y, z) = ∑ m(1, 3, 7, 11, 15) with don’t care, d (w, x, y, z) = ∑m(0, 2, 5 ) 03
(b) Design NOR gate by using CMOS logic family. 04
(c) Simplify the following Boolean function using tabulation method
F (w, x, y, z) = ∑ (0, 1, 2, 8, 10, 11, 14, 15)
07
Q.4 (a) Implement the following Boolean function by using 8:1 MUX
F(A,B,C,D) = ∑m(0,1,3,4,8,9,15).
03
(b) Design a full adder circuit using decoder and multiplexer (4:1 MUX). 04
(c) Discuss 4 – bit magnitude comparator in detail. 07 OR
Q.4 (a) Discuss Left Mode serial in serial out shift register. 03
(b) Explain working of master-slave JK flip-flop with necessary logic diagram. 04
(c) Design 4 – bit synchronous up - counter (Use T flip-flop). 07
Q.5 (a) Compare various DAC techniques. 03
(b) Write a short note on different types of ROM. 04
(c) How many types of RAM? Describe the internal organization of RAM. 07
OR
Q.5 (a) State the applications of A to D converters. 03
(b) Explain R-2R ladder DAC network. 04
(c) Write down various ADC networks and explain any one in brief. Which is best ADC? 07
*************
1
Seat No.: ________ Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER–IV (New) EXAMINATION – WINTER 2015
Subject Code:2140910 Date:22/12/2015
Subject Name: Digital Electronics
Time: 2:30pm to 5:00pm Total Marks: 70 Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
Q.1 (a) Give classification of binary codes with some example and short explanation. 07
(b) Define universal gate. Prove that NAND and NOR gates are universal gates. 07
Q.2 (a) Convert:
(i) (314.24)8 to (________)10 (ii) (250.58)10 to (_________)8
07
(b) Explain in brief about error detection and correction codes. 07
OR
(b) Simplify Y=A’BCD’ + BCD’ + BC’D’ + BC’D and implement using NAND
gates only.
07
Q.3 (a) Explain CMOS NOR gate. 07
(b) Write short note on K-map. 07
OR
Q.3 (a) Explain two input TTL NAND gate. 07
(b) Express A’B + A’C as sum of minterms and also plot K-map. 07
Q.4 (a) Write short note on half adder and full adder. 07
(b) What is positive and negative edge triggering? Explain SR flip flop with
negative edge triggering.
07
OR
Q.4 (a) Explain multiplexer. 07
(b) Differentiate between excitation table and truth table. Write excitation table for
J-K flip flop.
07
Q.5 (a) Write a note on EEPROM. 07
(b) Explain working of ring counter. 07
OR
Q.5 (a) Explain binary weighted resistor digital to analog converter. 07
(b) Classify memory. Differentiate between RAM and ROM. 07
*************
1
Seat No.: ________ Enrolment No.___________
GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER– IV(NEW) EXAMINATION – SUMMER 2015
Subject Code: 2140910 Date: 28/05/2015 Subject Name: DIGITAL ELECTRONICS Time: 10:30am-1.00pm Total Marks: 70 Instructions:
1. Attempt all questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks.
Q.1 (a) Explain the working of Master-Slave J-K flip-flop. 07
(b) Explain why NAND and NOR are known as universal gates and construct AND, OR and NOT using the universal gates.
07
Q.2 (a) State and explain De Morgan’s theorems with truth tables. 07 (b) Explain how four bit combined binary adder and subtractor circuit can be
constructed using full adders? 07
OR (b) Explain TTL and CMOS logic. 07 Q.3 (a) Do as directed :-
I. Find the XS-3 code of following decimal numbers (i) 26 (ii) 42 (iii) 63 II. (4CD)16 = ( )10 = ( )2 III. Solve the following using 2’s complement
(i) (-4)-(-8) (ii) (3)-(6)
07
(b) Do as directed:- I. Add the following decimal numbers using 8421 BCD equivalent codes 679.6 + 536.8 II. Convert the following Binary to Gray Code (i)1001 (ii)1010 (iii) 1011 III. Multiply the binary numbers (1011.01) X (10.1)
07
OR Q.3 (a) Define the following general characteristics of logic families.
(i) Propagation delay time (ii) Noise margin (iii) Fan-in (iv) Hold time (v) Clear (vi) Fan-out (vii) Power dissipation
07
(b) Describe multiplexer and de-multiplexer with circuit and application of each. 07 Q.4 (a) Apply De Morgan’s theorem to solve the following
07
(b) What are SOP and POS forms of boolean expressions? Minimize the following expression using K-map Y= Σm(4,5,7,12,14,15) + d( 3,8,10)
07
OR Q.4 (a) Describe the working of look-ahead-carry adder. 07
(b) Explain in brief the working of decoders. 07 Q.5 (a) Classify the various modes of operation of shift registers. Explain the serial in
parallel out operation of shift register. 07
(b) Discuss the applications of shift registers. 07
2
OR Q.5 (a) What is the basic difference between synchronous and asynchronous counter?
Describe synchronous 3-bit up counter. 07
(b) Explain the working of Analog to Digital converter with necessary diagrams. 07