EE M216A .:. Fall 2010 Lecture 10 Latches and Flip‐Flops Prof. Dejan Marković [email protected]Brief Introduction to Clocking / Latches & FFs Means to synchronize – By allowing events to happen at known timing boundaries, we can sequence these events Greatly eases building of FSMs – Clock strobe indicates the moment when states are stored No need to worry about variable delay through the CL – All signals are delayed until the clock edge (clock imposes the worst case delay) Dataflow FSM D. Markovic / Slide 2 register register register Comb Logic Comb Logic Lecture 10: Latches and Flip‐Flops | 2 EEM216A .:. Fall 2010
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– If 2:1 mux then sel2 can be sel1’– Instead of inverter, use simple logic gates
D2
ClkS2bQb
D. Markovic / Slide 34
ClkS1
Pb
D1
ClkS2Ds
Clkb
QClk
Ps
2
ClkS1b
Lecture 10: Latches and Flip‐Flops | 34EEM216A .:. Fall 2010
18
Enabled Flip‐Flop (or Latch)
New data is accepted only when Enable is HOtherwise retain old data
0D Q
EnD Q
QD Q
Conceptually, a mux before the F/F. Can use a built‐in mux
Or we can use a “qualified” clock
D. Markovic / Slide 35
1D Q
Clk
D
QEn
Clk
Lecture 10: Latches and Flip‐Flops | 35EEM216A .:. Fall 2010
Synchronous Reset
Some flip‐flops or latches embed very useful functions to help its operationSynchronous reset assumes that the reset (output L) occurs with the clock transitionthe clock transition
PbD DsQ
Clk
Ps
Qb
D. Markovic / Slide 36
Clk
PbDs
Clkb
Psrstb
Lecture 10: Latches and Flip‐Flops | 36EEM216A .:. Fall 2010
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Asynchronous Reset
The output is cleared to Low whenever a reset signal arrivesNeed to clear the held value (state)A Set/Reset can also be made using feedback NAND gates
PbD
Ds QbClk
Ps
Q
rstb
D. Markovic / Slide 37
Clk
D
Clkbrstb
Lecture 10: Latches and Flip‐Flops | 37EEM216A .:. Fall 2010
C2MOS Flip‐Flop: Insensitive to Clock Overlap
Uses clocked inverter
φbφb
in
out
φb
φin
out
φ
inout
φ
φb
in
φb
φ outφb
φDs
One nice feature of this F/F is that
D. Markovic / Slide 38
φ outφb One nice feature of this F/F is thatit is not sensitive to φ‐to‐φb skew
Lecture 10: Latches and Flip‐Flops | 38EEM216A .:. Fall 2010
No current
20
Charge Injection
A problem with dynamic nodes is that it is high‐impedance and therefore very sensitive to noiseClock/Data switching can easily introduce charge
Often known as clock feedthrough– Often known as clock feedthrough
in Dynamic out
φb
φ
Ccoup
Coutin
φb
φData held is Low
Input L‐H transition
D. Markovic / Slide 39
φ
outcoup
coupinout CC
CVV
+∆=∆
Not a big concern for this FF, but it can be for other designs
Lecture 10: Latches and Flip‐Flops | 39EEM216A .:. Fall 2010
Charge Sharing
Similar to injection, charge on floating nodes can share (depending on the gate voltage) degrading the value of the floating nodesExample:Example:
inDynamic out
φb
φ
Cout
CP
in
φb
φ
Input H-L transition causes CP and Cout to share
D. Markovic / Slide 40
outfinalPfinalafteroutGNDPDDbefore CVCVQCVCVQ +==+=Cout discharged L
CP charged H
outP
PDDfinal CC
CVV+
= Be careful because if Cout!>>Cp, VCP !< -VTP.
Note that C2MOS inverter is not designed like this… for this reason.
Lecture 10: Latches and Flip‐Flops | 40EEM216A .:. Fall 2010
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Pulsed Latch (Flip‐flop) Example
Hybrid Latch – Flip‐flop (HLFF)Used in AMD K‐6 and K‐7
P1
M3
M2D
CLK P3
M6
Qx
M5P2
D. Markovic / Slide 41EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 41
M1M4
CLKD
Hybrid Latch Flip‐flop (HLFF), AMD K6 & K7
QClk
S
D
Q
Clk1
D. Markovic / Slide 42
Transparent to D only when Clk and Clk1 are both highLimited clock uncertainty absorptionSmall D→Q delaySmall clock load
EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 42
Partovi et al. 1996
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Vdd
Q
2nd Stage LatchPulseGenerator
HLFF Analysis
D
Clk
Q
D=1
D. Markovic / Slide 43
Clk
D=1
D=0
signal atnode X
D=0
From: Oklobdzija et al.Digital System Clocking, Wiley’03
Lecture 10: Latches and Flip‐Flops | 43EEM216A .:. Fall 2010
Clk
D
Q
Logic Representation of HLFF
Enable
2nd Stage Latch
PulseGenerator
D. Markovic / Slide 44
D=1
D=0signal atnode X
D=1
D=0Lecture 10: Latches and Flip‐Flops | 44EEM216A .:. Fall 2010
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HLFF Logical Effort Sizing
The critical path is for D: 0→1. The first stage is a skewed NAND.
Q1 10 4
8x
Load
Clk
D
3
3
3
2
1
2
1
28x
4
From: Oklobdzija et al.Digital System Clocking, Wiley’03
D. Markovic / Slide 45EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 45
( ) ( )( )1,0 1
13 1 3 431 1 2 3
g →
⋅ ⋅ += =
⋅ +
( )
( )2,1 0
1 4 1010 1 721 1 2 6
g →
⋅ + − = =
⋅ +
1,0 1
4 4 10 4.73 3 1
f →
+= ⋅ =
+( ) ( )
2,1 0
8 2 4 1 27 4.256 4 10
f →
⋅ + + += ⋅ =
+
Digital System Clocking, Wiley 03
HLFF Sizing Notes
Second stage is slightly more complicated because of the keeper– Current that is sourced by the PMOS transistor to node Q can
be taken into account as negative conductance– Negative conductance is accounted for by subtracting the
conductance of the NMOS transistor (1) of the shaded keeperconductance of the NMOS transistor (1) of the shaded keeper inverter from the conductance of the driving PMOS (10/2)
For the particular load, efforts per stage were calculated to be 4.7 and 4.25, which is near the optimum value of 4, indicating that this example sizing is nearly optimal– The stack effect not taken into account (the logical effort values
for the NMOS transistor stack are somewhat pessimistic)
D. Markovic / Slide 46
for the NMOS transistor stack are somewhat pessimistic)– The alternative is to use an automated circuit optimizer. It is
not recommend it as initial method, because designer needs to know the circuit through manual sizing
– This builds intuition about the circuit and ability to verify optimizer results
EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 46
24
HLFF Delay (norm. to FO4 inverter) vs. Fanout
HLFF size‐optimized for three different loads (small, med, large)– Objective: minimize delay– This results in different sizing / buffering (A, B, C)
Th f t d ti t d l– Then we sweep fanout and estimate delayThere is only one optimal solution for each load size
Fanout 4 16 42 64 128
Load‐Size (#stages)
Small‐A (2) 1.60 2.06 3.11 4.19 7.80
D. Markovic / Slide 47EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 47
Medium‐B (2) 1.80 2.06 2.59 3.05 4.62
Large‐C (2+1) 2.27 2.44 2.74 2.96 3.56
Sizing vs. Load
The optimal delay versus fan‐out curve should have logarithmic shape, which indeed holds for the "best sizing vs. load curve”
5Delay [FO4]Delay [FO4]
3
4
Delay [FO4] Delay [FO4]
A B
C
D. Markovic / Slide 48EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 48
0 20 40 60 80 100 120 1401
2 Best sizing vs. load
Fanout
25
Delay Comparison
Pulsed latches are faster than master‐slaveMaster‐slave circuits have better race immunityPulsed‐latches scale better with VDD than master‐slave latches
0.25µm technology
D. Markovic / Slide 49EEM216A .:. Fall 2010 Lecture 10: Latches and Flip‐Flops | 49
Energy Comparison
D. Markovic / Slide 50Lecture 10: Latches and Flip‐Flops | 50EEM216A .:. Fall 2010
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Summary
Clocks are a convenient constraint to simplify system design– Essentially forces delay of all logic paths to equal TClk
St l t b b ilt b ith (1) i itiStorage elements can be built by either (1) using positive feedback to keep the value or (2) using capacitance to dynamically store the value– Dynamic elements are faster but are less robust
Dynamic storage is sensitive to noise
D. Markovic / Slide 51
– Particularly charge injection and charge sharing
Lecture 10: Latches and Flip‐Flops | 51EEM216A .:. Fall 2010