Latch vs. Flip-Flopbwrcs.eecs.berkeley.edu/.../ee241_s01/Lectures/lecture22-flipflops.pdf · Pulse-Triggered Latches Case 3: Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass,

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UC Berkeley EE241 B. Nikolić

EE241 - Spring 2001Advanced Digital Integrated Circuits

Lecture 22Flip-Flop Design


Latch vs. Flip-Flop� Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

� Flip-Flopstores data when clock rises

Clk Clk

D D

Q Q

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Latch Pair vs. Flip-Flop� Performance metrics� Delay metrics

» Delay penalty» Clock skew penalty» Inclusion of logic» Inherent race immunity

� Power/Energy Metrics» Power/energy» PDP, EDP

� Design robustness


Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

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Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch


Latches

Courtesy of IEEE Press, New York. 2000

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Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?


TSPC - True Single Phase Clock Logic

M1

M2

M3

VDD

In

Outφ

φ

M1

M2

M3

VDD

InOut

φ

φ M1

M2

M3

VDD

In

Out

φ

M1

M2

M3

VDD

InOut

φ

Precharged N Precharged P Non-precharged N Non-precharged P

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TSPC - True Single Phase Clock Logic

φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStaticLogic

PUN

PDN

Including logic intothe latch

Inserting logic betweenlatches


Doubled TSPC Latches

φ

VDD

Out

φ

VDD

Doubled n-TSPC latch

Inφ

VDD

Outφ

VDD

Doubled p-TSPC latch

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Master-Slave TSPC Flip-flops

φ

VDD

D

VDD

φ

VDD

D

φ

VDD

φ

VDD

D

VDD

φ

φ

Dφ

VDD

φ

VDD

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY


DEC Alpha 21064

Dobberpuhl, JSSC 11/92

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DEC Alpha 21064

L1: L2:


DEC Alpha 21064Integrating logic into latches• Reducing effective overhead

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DEC Alpha 21164

L1 Latch L2 Latch

L1 Latch with logic


Flip-Flop as a Latch Pair

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Latch vs. Flip-Flop



Requirements in the Flip-Flop Design

• High speed of operation:• Small Clk-Output delay• Small setup time• Small hold time→Inherent race immunity

• Low power• Small clock load• High driving capability• Integration of the logic into flip-flop• Multiplexed or clock scan• Robustness• Crosstalk insensitivity

- dynamic/high impedance nodes are affected

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Sources of Noise



Gate Isolation


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Flip-Flop Robustness� Robustness of the storage node� Input isolation� Data stored statically, max resistance limit� Min capacitance limit� Preventing exposure


Types of Flip-Flops

Latch Pair(Master-Slave)

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

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Flip-Flop Delay � Sum of setup time and Clk-output delay is the only

true measure of the performance with respect to the system speed

� T = TClk-Q + TLogic + Tsetup+ 2Tskew

D Q

Clk

D Q

Clk

LogicN

TLogicTClk-Q TSetup


Delay vs. Setup/Hold Times

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200Data-Clk [ps]

Clk

-Out

put [

ps]

Setup Hold

Minimum Data-Output

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Master-Slave Latches

� Positive setup times� Two clock phases:

» distributed globally» generated locally

� Small penalty in delay for incorporating MUX

� Some circuit tricks needed to reduce the overall delay


Master-Slave LatchesCase 1: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk

QClk Clkb

Clkb

D

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T-G Master-Slave LatchFeedback added for static operationUnbuffered inputinput capacitance depends on the phase of the clockover-shoot and under-shoot with long routeswirelength must be restricted at the inputClock load is highLow powerSmall clk-output delay, but positive setup


Master-Slave LatchesCase 2: C2MOS

VddVdd Vdd

Vdd

Vdd Vdd

Vdd

VddClk Ck

Ck

Ck

Ck

CkCkb

Ckb

Ckb

CkbQD

Feedback added for static operationLocally generated clockPoor driving capabilityRobustness to clock slope

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Pulse-Triggered LatchesFirst stage is a pulse generatorgenerates a pulse (glitch) on a rising edge of the clockSecond stage is a latchcaptures the pulse generated in the first stagePulse generation results in a negative setup timeFrequently exhibit a soft edge property

Note: power is always consumed in the pulse generator


Pulse-Triggered LatchesCase 1: Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96

Vdd

D

Clk

Q

Q

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HLFF Operation1-0 and 0-1 transitions at the input with 0ps setup time


Hybrid Latch Flip-Flop

Flip-flops features: single phase clockedge triggered, on one clock edgeLatch features: Soft clock edge propertybrief transparency, equal to 3 inverter delaysnegative setup timeallows slack passingabsorbs skewHold time is comparable to HLFF delayminimum delay between flip-flops must be controlledFully staticPossible to incorporate logic

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Soft Edge PropertyAlso known as cycle borrowing, or slack passingIn latch based designs, if longest path datum reaches latch before its setup time, clock skew does not affect cycle timeIf longest path reaches latch close to setup time, clock skew isdirectly subtracted from cycle timeFlip-flop presents a ‘hard’ edge - no slack passing.HLFF is a compromise - has a controlled transparency period, that can absorb skewPrice is paid in the hold time


Hybrid Latch Flip-Flop

Partovi et al, ISSCC’96

Skew absorption

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Pulse-Triggered LatchesCase 2: AMD K-7



Pulse-Triggered LatchesCase 3: Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits’98

Clk

D

Vdd Vdd

Q

Q

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transitionLatch has one transistor less in stack - faster than HLFF, but 1-1 glitch existsSmall penalty for adding logic

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Pulse-Triggered LatchesCase 3: 7474, Texas Instruments’64

Clk

D

Q

Q

S

R


7474Karnaugh maps for signals S and R

x 1

x 1

Clk, D 00 01

00

11 10

1 1

1 1

x 1

x 1

1 0

0 0

01

11

10

S R R

S

DClk

SDR

Clk

x 1

x 1

Clk, D 00 01

00

11 10

1 1

1 1

x 0

x 0

0 1

1 1

01

11

10

S R R

S

DClk

RSD

Clk

Clk

D

Q

Q

S

R

D

SDRClkS ⋅⋅⋅= RDSClkR ⋅⋅⋅=

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Pulse-Triggered Latches

First stage is a sense amplifier,precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edges

Case 4: Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110


Sense Amplifier-Based Flip-FlopThe first stage is unchanged sense amplifierSecond stage is sized to provide maximum switching speedDriver transistors are largeKeeper transistors are small and disengaged during transitions

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Sense Amplifier-Based Flip-Flop



Flip-Flop Performance Comparison

Total power consumedinternal powerdata power clock powerMeasured for four casesno activity (0000… and 1111…)maximum activity (0101010..)average activity (random sequence)

Test bench

Delay is (minimum D-Q)Clk-Q + setup time

Clk

Data

Clock

50fF

200fF

200fFD Q

Q

Stojanovic, Oklobdzija JSSC 4/99

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Flip-Flop Performance Comparison

Delay vs. power comparison of different flip-flopsFlip-flops are optimized for speed with output transistor sizes limited to 7.5µm/4.3 µmTotal transistor gate width is indicated

0

10

20

30

40

50

60

70

100 150 200 250 300 350 400 450 500

Delay [ps]

Tota

l pow

er [u

W]

mSAFF64µm SDFF 49 µm

HLFF 54µm

C2MOS80µm

TG M-S52µm Original SAFF 60µm


Energy Consumption• Always consume

� ECLK = E0-0 = E1-1

• When Q : 1-0 or 0-1� Eint = E1-0 – E0-0

• Only when Q : 0-1� Eext = E0-1 – E1-0

Energy Breakup in TG-MS (PowerPC603)

8%

3854%

External Load Internal Nodes

Clo

cked

Nod

es

42fJ 29fJ

6fJ

• Non-inverting Flops:� Eavg = ECLK + α • Eext + (1- α) • Eint

• Inverting Flops:� Eavg = ECLK + (1-α) • Eext + α • Eint

(α - probability of D : 0-1)

[Markovic]

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Energy DissipationComparison of Master Slave and Pulse-Triggered Flip-Flops

1423

3036

5964

85

101

198

114

3142

102 103114

1423

94

183

57

0

50

100

150

200

250

TG FF C2MOS HLFF SDFF SAFF

Ene

rgy

[fJ]

0--00--11--01--1

Resized for Energy/Delay


Local Clock Gating

D

QCKI

CKIB

0.85 0.85

2

0.850.5 0.5

0.5

1.2

CP

0.50.85 0.50.85

XNOR

CKIB

CKI

CKIB 0.5

0.5

0.85

0.5

PulseGenerator

Data-TransitionLook-Ahead

DI

‘Clock on demand’Flip-flop

Latch vs. Flip-Flopbwrcs.eecs.berkeley.edu/.../ee241_s01/Lectures/lecture22-flipflops.pdf · Pulse-Triggered Latches Case 3: Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass,

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