Laser Spike Annealing for sub-20nm Logic Devices Jeff Hebb, Ph.D. July 10, 2014 1 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014 1
Laser Spike Annealing for sub-20nm Logic Devices
Jeff Hebb, Ph.D.July 10, 2014y ,
1 NCCAVS Junction Technology Group Semicon West Meeting July 10, 20141
Outline
• Introduction• Pattern Loading Effects• LSA ApplicationsLSA Applications
• Dopant Activation• Ti silicideTi silicide
• Summary
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LSA Overviewvs
CO2 Laser Temperature Power Control 2
(10.6μm) ConversionControl Algorithm
Hot Chuck
p-polarizedReflective
OpticsEmission Detector
Laser Beam
Vs
Dwell ti =
wHot Chuck
Scanning Stage
Silicon
time vx
Note: Beam is stationary, wafer scans
Key Attributes• CO2 Laser: λ ~ 10umWithin die
Within-wafer • Temperature feedback
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CO2 Laser: λ 10um• P-polarized, brewster angle
Within-dieUniformity
&Wafer-to-wafer
• Temperature feedback control
Pattern Loading Effects
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Pattern Effects and Parametric YieldSystem-on-a-Chip
• Variations in pattern density lead to local variations in the absorbed
A B
to local variations in the absorbed radiation during RTP or millisecond anneal
• This can lead to local variations in THighTLow
This can lead to local variations in peak temperature, and variations in performance of devices which are supposed to be matched
Device A gets colder during annealD i B t h tt d i lDevice B gets hotter during anneal
Device Performance Mismatch!
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Pattern loading effects during millisecond annealing or RTP can cause device performance mismatch within the die parametric yield loss and degraded circuit speed
Pattern Loading Effects in RTP: Equipment Solution
Highlights• Lots of recent work on how to
change RTP equipment solutions to suppress pattern effects: backside heating1 or Differential Thermal Energy Control2
• These approaches are being Ref 1
pp gimplemented in Fabs for critical processes at advanced nodes
• Current implementations for p“dummification” are not adequate for critical processes
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1. X. Yu et al, IEDM 20122. P. Timans et al., IWJT 2014
Ref 2
Pattern Effects in MSA: Layout Design Solution
Pre-dummification Post-dummification
Simulation showed “ΔT < 50oC”ΔT > 100oC (typical) Simulation showed ΔT < 50 C( yp )
SC Lin et al., “Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing”, J. Intell. Man. (2012)
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• Difficult to reduce to acceptable levels due to short heat diffusion length (~100um)• Difficult to make design rules to cover all layouts in a foundry environment
Pattern Loading Effects: Thin Film Interference
PLE: DL > FLA >> LSA
Di d L
FLA/RTP
Di d L
FLA/RTP
80
100Bare Si wafer340 nm oxide on Si+10% oxide thickness-10% oxide thickness120 nm poly on oxide+10% poly thickness
θCO2
80
100Bare Si wafer340 nm oxid
80
100Bare Si wafer340 nm oxide on Si+10% oxide thickness
e on Si+10% oxide thickness-10% oxide thickness120 nm poly on oxide+10% poly thickness
-10% oxide thickness120 nm poly on oxide+10% poly thickness
θCO2
θCO2
Diode Laser(λ=0.8um)Diode Laser(λ=0.8um)
40
60
efle
ctiv
ity(%
)
10% poly thickness-10% poly thickness
LSACO2 (λ =10.6um)P-polarizedBrewsters Angle40
60
40
60
efle
ctiv
ity(%
)ef
l ect
ivity
(%)
10% poly thickness10% poly thickness-10% poly thickness
LSACO2 (λ =10.6um)P-polarizedBrewster’sAngleef
l ect
ivity
(%)
efl e
ctiv
ity(%
)
20
Re g
2020
Re
Re g
Re
Re
PLE d b thi fil i t f i ti t h t λ
9.0 9.5 10.0 10.5 11.0 11.5 12.0Wavelength (μm)
09.0 9.5 10.0 10.5 11.0 11.5 12.0
09.0 9.5 10.0 10.5 11.0 11.5 12.0
Wavelength (μm)Wavelength (μm)
0
Wavelength (μm)Wavelength (μm)
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• PLE caused by thin film interference variations severe at short λ• Long λ+p-pol+Brewster’s angle make LSA insensitive to device film variations
Pattern Loading Effects in Millisecond Annealing: E i t S l ti (LSA)Equipment Solution (LSA)
LSA Flash Anneal / Diode Laser
θ
• Long λ• Brewsters Angle• No shadowing
or light trapping b Fi
• Short λ• Near normal
incidence• Can have light
t i b FiFins
0
5
10
15
20
by Fins trapping by FinsFinsFins
SiliconSilicon
25
Measured reflectance
map
Measured reflectance
map
ΔT ~ 10oC ΔT > 100oC
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LSA provides an equipment solution for PLE in millisecond annealing
Applications
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LSA Applications for 14/10nm FinFET Devicespp
Hi-kanneal
Device Applications
Extensionanneal
• Source/Drain extension annealingFin
• Deep Source/Drain annealing
Hi k lTi silicide
S/D Anneal&
• Hi-k anneal
• Dopant re-activation& Re-activation • Ti Silicide
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LSA enables device performance improvements and leakage reduction for FinFETs
Source/Drain (epi) Activation Post-dep properties of Si:P Epi 1 Post-LSA properties of Si:P Epi 1
• As-deposited activation efficiency is low• Trade-off between growth rate and activation
• Activation greatly improves with LSA• Further improvement with cryogenic a-Si + LSA
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Sources: 1.Itokawa et al., IWJT 2012, 2.Yamashita et al, VLSI 2011
LSA improves activation and device performance by S/D activation in FinFETs2
Thermal Profiles of LSA vs. Flash Anneal
1.E+21
ear T2=1100C, As 3keV 2e15(cm
-3 ) 1021
De-activation during FLA anneal
ntratio
n ne
3) ncen
trat
ion
(
rier Con
cen
peak (cm‐
e C
arrie
r Con
T2 T2
1 E+20
Activ
e Carr
T1
Peak
Act
ive
1020Ref: H. Kennel (Intel), RTP 2010
1.E+20600 700 800 900 1000
Intermediate Temperature, T1 (C)
10
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• LSA is a true low thermal budget anneal with no dopant de-activation• Extra thermal budget of FLA can cause dopant de-activation slower devices
New Channel Materials
16007 FET
1200
1400
erat
ure (
C)7nm pFET
800
1000
1200
eltin
g Tem
pe7nm nFET
600
800Me
Si In.5Ga.5As InP Ge
7nm nFET
A. Steegen, Imec Technology Forum, Semicon 2014
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• New channel materials will suffer damage at much lower thermal budgets than Si• Low thermal budget of LSA compatible with new channel materials
Arsenic Activation and Diffusion in GeHighlights• Ge substrates* implanted SPE Regrowth Thickness for
with As 5keV 2e15 (creates ~10nm self amorphizinglayer)
g200usec LSA (calculated)
Ge• Since SPE happens in Ge at
much lower temperatures than Si, use low chuck temperatures to reduce
Si
temperatures to reduce thermal budget**
• Splits:P k t t 600 t 900C• Peak temperature: 600 to 900C
• Dwell time: 200 and 800usec• Chuck temperature: RT and
200C
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*Note: Substrates were Ga doped to ~ 6e17cm-2** A higher SPE temperature typically results in higher activation * Y. Wang et al., IWJT 2014
Arsenic Activation in Ge: Results
Chuck T=200oC Chuck T=200oC
200usec 200 and 800 usec
• Significant diffusion starts above 760C at 200usecSi ifi tl diff i t 800 th 200
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• Significantly more diffusion at 800usec than 200usec* Y. Wang et al., IWJT 2014
Arsenic Activation in Ge: Results (cont’d) Rs vs. Temperature Rs vs. Xj
• Significant Rs reduction at 800usec due to extra diffusion
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• Chuck temperature RT vs. 200C did not make significant difference
* Y. Wang et al., IWJT 2014
LSA for Titanium Silicide
⎟⎞
⎜⎛
BφAdvantages of LSA for Ti silicide
• Higher temperature than RTA
Schottky barrier height
⎟⎟⎠
⎜⎜⎝
∝D
Bc N
φρ exp • Higher temperature than RTA lower contact resistance
• Minimal interdiffusion of gate stack Dopant concentration
layers• Process control
• Minimal pattern effects• Closed loop temperature control• Becomes critical for Ti silicide• Becomes critical for Ti silicide
where process window is smaller than Ni silicide
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Refs: D. James, AVS JTG Semicon West (2013) and C. Sohn et al.,” IEEE Trans. Elec. Dev., Apr. 2013.
LSA for Ti silicide: Phase Transformation StudyY. Wang et al, IWJT 2014 • Phases detected by XRD:
A1: TiA2: Ti Ti SiA2: Ti, Ti5Si3A3: Ti5Si3, possible Ti5Si4 or TiSiB2/B3: TiSi2 (C40)B4/B5: TiSi (C54)
20nmTi with10nm TiN cap
B4/B5: TiSi2 (C54)
• Examples of φB (G. Qttaviani et al, Ph R L tt 1980)850-1000oC Phys. Rev. Lett., 1980):
• TiSi2: 0.6V• TiSi: 0.5V
NiSi 0 67V
• Low Rs not required Low Rc is the goal (low φB )
• NiSi: 0.67V
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• No need to anneal at temperatures greater than ~1000C, where gate stack could be compromised
Pattern Loading Effects (PLE) For Silicides
40
Measured reflectance:
LSA (10.6um)Within-die temperature distribution:
Simulated from measured reflectance maps
30
ensi
ty LSAΔT ~ 10CTi SilicideProcess
10
20
obab
ility
DMeasured
reflectance:Diode Laser Diode
Window (estimated)
0
10PrDiode Laser
(0.8um)Diodelaser
ΔT > 100C700 750 800 850 900 950
T (oC)
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• Severe PLE of diode laser could impact yield for Ti silicide (PLE >100C)• PLE of LSA is well within the process window (PLE~10C)
Summaryy• Long-wavelength LSA provides an equipment-design
solution for pattern loading effects in millisecond p gannealing
• LSA plays a critical role in reducing series resistanceLSA plays a critical role in reducing series resistance and leakage in today’s FinFETs through multiple applications
• As sub-10nm devices migrate to new channel materials, low thermal budget annealing approaches such as LSA will be become more criticalsuch as LSA will be become more critical
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