LAB1COA

COMPUTER ORGANIZATION AND DESIGN

SUBMITTED BY: NAILA REHMAN(11PWCSE0944) QANDEEL FATIMA(11PWCSE0949)LAB REPORT: ONESECTION: BSUBMITTED TO: ENGR.AMAD

QUESTION#1:IMPLEMENT 2*1 MUX ON GATE LEVEL.

module mux21(a,b,sel,out); input a,b,sel; output out; wire aout,bout,sout; and a1(aout,a,sel); not n1(sout,sel); and b1(bout,sout,b); or o1(out,aout,bout); endmodule

TOP MODULE:

module top_m; reg a,b,sel; wire out; mux21 m1(a,b,sel,out); initial begin b=0; sel=1; a=1; #2 a=0; #2 b=1; end endmodule

OUTPUT:

QUESTION#2: IMPLEMENT 4*1 MUX BY USING 2*1 MUX ON GATE LEVEL. module mux_4(a,b,c,d,s0,a0,out); input a,b,c,d,s0,a0; output out;

wire w1,w2,w3,w4,s1,a1; mux_2 m1(a,b,s0,w3); mux_2 m2(c,d,s0,w4); not n(s1,s0); and (w1,s1,w3); and (w2,s0,w4); or r(out,w1,w2); endmodule

TOP MODULE:

module mux_4_top; reg a,b,c,d,s0,a0; wire out; mux_4 mu(a,b,c,d,s0,a0,out); initial begin a=1; b=1; c=1; d=1; s0=0; a0=0; end initial $monitor($time,":a=%b b=%b c=%b d=%b s0=%b a0=%b out=%b\n" ,a,b,c,d,s0,a0,out); endmodule

OUTPUT:

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