Introduction The TMS320C6000 digital signal processor (DSP) platform is part of the TMS320 DSP family. The TMS320C62DSP generation and the TMS320C6! DSP generation comprise fied"point de#ices in the C6000 DSP platform$ and the TMS320C6%DSP generation comprises floating point de#ices in the C6000 DSP platform. The C62and C6!DSPs are code"compati&le. The C62and C6%DSPs are code"compati&le. 'll three DSPs se the elociT* architectre$ a high"p erformance$ ad#anced #ery long instrctio n +ord (,*-) archi tectr e$ main g these DSPs ecellent choices for mltichannel and mltifnction applications. TMS320C62x DSP Architecture Figure 1--1 is the block diagram for the C62x DSP. The C6000 devices come with program memory, hich, on some devices, can be used as a program cache. The devices also have varying sizes of datamemory. Perip herals such as a direct memor y access (DMA) control ler, power-do wn logic, and exter nal memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are on onl y cer tai n dev ices . Check you r dat a man ual for you r dev ice to det ermine the specif ic per ipheral configurations. Figure 1--1. TMS320C62x DSP Block Diagram
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
The TMS320C6000 digital signal processor (DSP) platform is part of the TMS320 DSP family.The TMS320C62 DSP generation and the TMS320C6! DSP generation comprise fied"pointde#ices in the C6000 DSP platform$ and the TMS320C6% DSP generation comprises floatingpoint de#ices in the C6000 DSP platform. The C62 and C6! DSPs are code"compati&le. The
C62 and C6% DSPs are code"compati&le. 'll three DSPs se the elociT* architectre$ ahigh"performance$ ad#anced #ery long instrction +ord (,*-) architectre$ maing theseDSPs ecellent choices for mltichannel and mltifnction applications.
TMS320C62x DSP ArchitectureFigure 1--1 is the block diagram for the C62x DSP. The C6000 devices come with program memory, hich,on some devices, can be used as a program cache. The devices also have varying sizes of datamemory.Peripherals such as a direct memory access (DMA) controller, power-down logic, and external memoryinterface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are ononly certain devices. Check your data manual for your device to determine the specific peripheralconfigurations.
Central Processing Unit (CPU)The C62x CPU, in Figure 1--1, contains:- Program fetch unit- Instruction dispatch unit- Instruction decode unit- Two data paths, each with four functional units-
32 32-bit registers- Control registers- Control logic- Test, emulation, and interrupt logicThe program fetch, instruction dispatch, and instruction decode units candeliver up to eight 32-bit instructions to the functional units every CPU clockcycle. The processing of instructions occurs in each of the two data paths (Aand B), each of which contains four functional units (.L, .S, .M, and .D) and16 32-bit general-purpose registers. The data paths are described in moredetail in Chapter 2. A control register file provides the means to configure andcontrol various processor operations. To understand how instructions arefetched, dispatched, decoded, and executed in the data path, see Chapter 4.
Internal Meor!The C62x DSP has a 32-bit, byte-addressable address space. Internal(on-chip) memory is organized in separate data and program spaces. Whenoff-chip memory is used, these spaces are unified on most devices to a singlememory space via the external memory interface (EMIF).The C62x DSP has two 32-bit internal ports to access internal data memory.The C62x DSP has a single internal port to access internal program memory,with an instruction-fetch width of 256 bits.
Meor! and Peri"heral #"tionsA variety of memory and peripheral options are available for the C6000platform:- Large on-chip RAM, up to 7M bits- Program cache- 2-level caches- 32-bit external memory interface supports SDRAM, SBSRAM, SRAM,
and other asynchronous memories for a broad range of external memoryrequirements and maximum system performance.TMS320C62x DSP Architecture
1-8 Introduction SPRU731A
- The direct memory access (DMA) controller transfers data betweenaddress ranges in the memory map without intervention by the CPU. TheDMA controller has four programmable channels and a fifth auxiliarychannel.- The enhanced direct memory access (EDMA) controller (C6211 DSPonly) performs the same functions as the DMA controller. The EDMA has16 programmable channels, as well as a RAM space to hold multipleconfigurations for future transfers.- The host port interface (HPI) is a parallel port through which a host processor
can directly access theCPUmemory space. The host device functionsas amaster to the interface, which increases ease of access. The host andCPU can exchange information via internal or external memory. The hostalso has direct access tomemory-mappedperipherals. Connectivity to theCPU memory space is provided through the DMA/EDMA controller.- The expansion bus is a replacement for the HPI, as well as an expansionof the EMIF. The expansion provides two distinct areas of functionality(host port and I/O port) that can co-exist in a system. The host port of theexpansion bus can operate in either asynchronous slavemode, similar tothe HPI, or in synchronous master/slave mode. This allows the device to
interface to a variety of host bus protocols. Synchronous FIFOs andasynchronous peripheral I/O devices may interface to the expansion bus.- The peripheral component interconnect (PCI) port supports connection ofthe C62x DSP to a PCI host via the integrated PCI master/slave businterface.- The multichannel buffered serial port (McBSP) is based on the standard
serial port interface found on the TMS320C2000
and TMS320C5000
devices. In addition, the port can buffer serial samples in memory automaticallywith the aid of theDMA/EDMAcontroller. It also has multichannelcapability compatible with the T1, E1, SCSA, and MVIP networkingstandards.
$a%&a re"ort
Lab 1 – TMS320C6713 DSK and Code Composer Studio1.1. IntroductionThe hardware experiments in the DSP lab are carried out on the Texas Instruments TMS320C673 DSPStarter !it "DS!#$ based on the TMS320C673 %loatin& point DSP runnin& at 22' M()* The basic cloc+ c,cle
instruction time is /(22' M())=
-.-- nanoseconds* Durin& each cloc+ c,cle$ up to ei&ht instructionscan be carried out in parallel$ achie.in& up to /×22' = /00 million instructions per second "MIPS#*The C673 processor has 2'6! o% internal memor,$ and can potentiall, address -1 o% externalmemor,* The DS! board includes a 6M SDM memor, and a '2! 4lash 5M* It has an onboard6bit audio stereo codec "the Texas Instruments IC23# that ser.es both as an D and a D con.erter*There are %our 3*' mm audio 8ac+s %or microphone and stereo line input$ and spea+er and headphoneoutputs* The IC23 codec can be pro&rammed to sample audio inputs at the %ollowin& samplin& rates9
f s = /, 6, 2-, 32, --., -/, :6 +()The DC part o% the codec is implemented as a multibit thirdorder noiseshapin& deltasi&ma con.erter"see Ch* 2 ; 2 o% <= %or the theor, o% such con.erters# that allows a .ariet, o% o.ersamplin&
ratios that can reali)e the abo.e choices o% f s* The correspondin& o.ersamplin& decimation %ilters act
as antialiasin& pre%ilters that limit the spectrum o% the input analo& si&nals e%%ecti.el, to the >,?uist
inter.al [−f s/2, f s/2]* The DC part is similarl, implemented as a multibit secondorder noiseshapin&
deltasi&ma con.erter whose o.ersamplin& interpolation %ilters act as almost ideal reconstruction %ilterswith the >,?uist inter.al as their passband*
The DS! also has %our userpro&rammable DIP switches and %our @ADs that can be used to controland monitor pro&rams runnin& on the DSP*ll %eatures o% the DS! are mana&ed b, the CCS$ which is a complete inte&rated de.elopment en.ironment"IDA# that includes an optimi)in& CCBB compiler$ assembler$ lin+er$ debu&&er$ and pro&ramloader* The CCS communicates with the DS! .ia a S connection to a PC* In addition to %acilitatin& allpro&rammin& aspects o% the C673 DSP$ the CCS can also read si&nals stored on the DSPs memor,$ orthe SDM$ and plot them in the time or %re?uenc, domains*The %ollowin& bloc+ dia&ram depicts the o.erall operations in.ol.ed in all o% the hardware experiments
in the DSP lab* Processin& is interruptdri.en at the samplin& rate f s$ as explained below*
The IC23 codec is con%i&ured "throu&h CCS# to operate at one o% the abo.e samplin& rates f s* Aachcollected sample is con.erted to a 6bit twos complement inte&er "a sort data t,pe in C#* The codecactuall, samples the audio input in stereo$ that is$ it collects two samples %or the le%t and ri&ht channels*t each samplin& instant$ the codec combines the two 6bit le%tri&ht samples into a sin&le 32bitunsi&ned inte&er word "an unsi!ned int$ or "int32 data t,pe in C#$ and ships it o.er to a 32bit recei.ere&istero% the multichannel bu%%ered serial port "McSP# o% the C673 processor$ and then issues aninterrupt to the processor*pon recei.in& the interrupt$ the processor executes an interrupt ser.ice routine "IS# that implementsa desired sample processin& al&orithm pro&rammed with the CCS "e*&*$ %ilterin&$ audio e%%ects$ etc*#*
Durin& the IS$ the %ollowin& actions ta+e place9 the 32bit input sample "denoted b, x in the dia&ram# isread %rom the McSP$ and sent into the sample processin& al&orithm that computes the correspondin& TMS320C673 DS! >D C5DA C5MP5SA STDI5 /
32bit output word "denoted b, y#$ which is then written bac+ into a 32bit transmitre&ister o% theMcSP$ %rom where it is trans%erred to the codec and reconstructed into analo& %ormat$ and %inall, theIS returns %rom interrupt$ and the processor be&ins waitin& %or the next interrupt$ which will come atthe next samplin& instant*