VLSI CIRCUIT AND SYSTEMS EC-605 EXPERIMENT-1 AIM:- To study and design BCD to SEVEN segment display by the use of verilog module. APPARTUS REQUIERD:- CPLD kit, Computer, Power supply for VLSI platform , JTAGE CABLE. PROGRAM:- module bcd_seven_seg(bcd_in,seven_seg,tran_in); input [3:0] bcd_in; output [5:0]tran_in; output [6:0] seven_seg; reg [6:0] seven_seg; reg [5:0]tran_in; always@(bcd_in) begin case(bcd_in) 4'b0000 : begin seven_seg <= 7'b0111111;tran_in <= 6'b100000; end 4'b0001 : begin seven_seg <= 7'b0000110 ;tran_in <= 6'b100000; end 4'b0010 : begin seven_seg <= 7'b1011011 ;tran_in <= 6'b100000; end 4'b0011 : begin seven_seg <= 7'b1001111 ;tran_in <= 6'b100000; end 4'b0100 : begin seven_seg <= 7'b1100110 ;tran_in <= 6'b100000; end 4'b0101 : begin seven_seg <= 7'b1101101 ;tran_in <= 6'b100000; end 4'b0110 : begin seven_seg <= 7'b1111101 ;tran_in <= 6'b100000; end 4'b0111 : begin seven_seg <= 7'b0000111 ;tran_in <= 6'b100000; end 4'b1000 : begin seven_seg <= 7'b1111111 ;tran_in <= 6'b100000; end 4'b1001 : begin seven_seg <= 7'b1101111 ;tran_in <= 6'b100000; end 4'b1010 : begin seven_seg <= 7'b1110111 ;tran_in <= 6'b100000; end BI LAB MANUAL AND WORKBOOK 6 LAB MANUAL AND WORK BOOK
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT1
AIM:
To study and design BCD to SEVEN segment display by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer, Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module bcd_seven_seg(bcd_in,seven_seg,tran_in);
input [3:0] bcd_in;
output [5:0]tran_in;
output [6:0] seven_seg;
reg [6:0] seven_seg;
reg [5:0]tran_in;
always@(bcd_in)
begin
case(bcd_in)
4'b0000 : begin seven_seg <= 7'b0111111;tran_in <= 6'b100000; end
4'b0001 : begin seven_seg <= 7'b0000110 ;tran_in <= 6'b100000; end
4'b0010 : begin seven_seg <= 7'b1011011 ;tran_in <= 6'b100000; end
4'b0011 : begin seven_seg <= 7'b1001111 ;tran_in <= 6'b100000; end
4'b0100 : begin seven_seg <= 7'b1100110 ;tran_in <= 6'b100000; end
4'b0101 : begin seven_seg <= 7'b1101101 ;tran_in <= 6'b100000; end
4'b0110 : begin seven_seg <= 7'b1111101 ;tran_in <= 6'b100000; end
4'b0111 : begin seven_seg <= 7'b0000111 ;tran_in <= 6'b100000; end
4'b1000 : begin seven_seg <= 7'b1111111 ;tran_in <= 6'b100000; end
4'b1001 : begin seven_seg <= 7'b1101111 ;tran_in <= 6'b100000; end
4'b1010 : begin seven_seg <= 7'b1110111 ;tran_in <= 6'b100000; end
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-6054'b1011 : begin seven_seg <= 7'b1111100 ;tran_in <= 6'b100000; end
4'b1100 : begin seven_seg <= 7'b0111001 ;tran_in <= 6'b100000; end
4'b1101 : begin seven_seg <= 7'b1011110 ;tran_in <= 6'b100000; end
4'b1110 : begin seven_seg <= 7'b1111011 ;tran_in <= 6'b100000; end
4'b1111 : begin seven_seg <= 7'b1110001 ;tran_in <= 6'b100000; end
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is seven segment display ?
Ans: Seven segment display is device that displays digits from 0 to 9 in according to programming
Ques2: What is application of seven segment display ?
Ans: It is most widely uses in calculator, digital logic devices and many more.
Ques3: What is VHDL ?
Ans: VHDL stands for VHSIC Hardware Description Language, used to model any digital system.
Ques4: What is VHSIC ?
Ans: VHSIC stands for Very High Speed Integrated Circuit.
Ques5: What is CPLD ?
Ans: CPLD is Complex Programmable Logic Device.
There are 3 types of PLD :
1. SPLD
2. CPLD
3. FPGA
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT2
AIM:
To study and design de_mux_1_4 by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE cable.
PROGRAM:
module de_mux_1_4(sel,de_mux_in,de_mux_out);
input [1:0] sel;
input de_mux_in;
output [3:0]de_mux_out;
reg [3:0]de_mux_out;
always@(sel or de_mux_in)
begin
case (sel)
2'b00 : de_mux_out[0] <= de_mux_in;
2'b01 : de_mux_out[1] <= de_mux_in;
2'b10 : de_mux_out[2] <= de_mux_in;
2'b11 : de_mux_out[3] <= de_mux_in;
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is De multiplexer ?
Ans: De multiplexer is circuit, which has only 1 input and many outputs.
Ques2: What is 1: 4 De multiplexer ?
Ans: It has 1 input and 4 output lines.
Ques3: What do you mean by IEEE ?
Ans: IEEE is Institution for electronic and electrical engineering.
Ques4: What is use of case statement in programming ?
Ans: Case statement selects one of branches for execution, based on the value of the expression.
Ques5: Explain syntax of case statement ?
Ans: Syntax:
case()
when choice 1 = statement;
when choice 2 = statement;
when others = statement;
end case;
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT–3
AIM :
To study and design LED_Flasher by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE cable.
PROGRAM:
module LED_Flasher(clock,sel,leds,rst);
output [15:0]leds;
reg [15:0]leds;
reg [3:0]counter;
input clock; // 8 MHz system clock
input rst; // External reset
input [2:0]sel; // Output rate select
reg div256;
reg [3:0]cnt1; // Div by 13
reg [7:0]cnt2; // Div by 2 to 256
reg [5:0]cnt3; // Div by 8
wire clk_out;
assign clk_out = cnt3[5];
always@(posedge clock or negedge rst)
begin
if (!rst)
begin
cnt1 <= 8'b0;
end
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605 else if (cnt1 == 4'b1100) // Div by 13
begin
cnt1 <= 4'b0000;
end
else
begin
cnt1 <= cnt1 + 1;
end
end
always@(negedge cnt1[3] or negedge rst)
begin
if (!rst)
cnt2 <= 8'b0; // Div by 2 to 256 based on sel input