Top Banner
L25 04/16/02 1 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc/
12

L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter [email protected]

Jan 21, 2016

Download

Documents

Bethany Green
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Page 1: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 1

EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26

Professor Ronald L. [email protected]

http://www.uta.edu/ronc/

Page 2: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 2

Fig 5.1* Emitter-follower outputstage with current-mirror bias.

• Q3 is gummel conf• IR~(VCC-Vbe)/(R3+R1)• IQ ~ IR*R1/R2• If Q1 & Q2 FA, thenVi = Vo +

Vt ln((IQ+Vo/RL)/IS)• If RL large, Io << IQ, so• Vi > 0, Vi = Vo + const.,

until Q1 saturates• Vi < 0, the same until

Q2 sat at -VCC +VCE2sat

• RL starts significant conduction at

RL3 = (2VCC + VCE2sat)/IQ

Page 3: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 3

Fig 5.2* Transfer char. of the circuit of Fig 5.1 for low (RL2) and high (RL1) values of RL• For RL = RL1 >

RL3, negl load curr

• For RL = RL2 < RL3, incl load curr

Page 4: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 4

Fig 5.3* (a) Q1 doesn’t cutoff(b) Q1 does cutoff

• (1) low input• (2) input high

enough, or RL low enough to c/o Q1

Page 5: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 5

Fig 5.4* Loadlines for RLs(2VCC + VCE2sat)/IQ RL3

• Gives max power (C) • RL2 < RL3 power (B) • RL1 > RL3

power (A) max =(1-VCEsat/VCC)/4 ~ 1/4

KVL gives:VCC =Vce1 +(IC1-IQ)*RL

IC1 = (VCC-Vce1)/RL+IQ

Page 6: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 6

Fig 5.6*

Max powerLoad, tang.@ mid-point

o.c. load

Short Circuit load

Constant power hyperbolas

2Vcc > BVCEO

Page 7: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 7

Fig 5.7* Low-frequency, small-signal equivalent circuit for the emitter follower

Class A: Drive device has an appreciable current(no-cutoff)

Av = vo/vi = RL/(RL+1/gm+Rs/o)

Ro = 1/gm+Rs/o

(… + RL)

Page 8: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 8

Fig 5.10* Simplified ic Class B output stage• Q1 (npn) and Q2 (pnp),

are a complementary pair 1 = 2

• Q1 off if Vi < VbeOn

• Q2 off if Vi > -VbeOn

Dead zone: IL = 0 if -VbeOn < Vi < VbeOn

IL

Page 9: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 9

Fig 5.11* Transfer Characteristic of the Class B Stage

Page 10: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 10

Fig 5.13* Class AB output stage. The gummel diodes reduce crossover distortion.

Page 11: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 11

Fig 5.20a* Simplified schematic of the 741 output stage

Group Project will be similar

Optimize current, voltage gain, fT

Use Cadence to capture schema- tic, set bias, etc. and gene- rate outputs

Page 12: L25 04/16/021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 26 Professor Ronald L. Carter ronc@uta.edu

L25 04/16/02 12

References

* Analysis and design of analog integrated circuits, 4th ed., by Gray, Hurst, Lewis and

Meyer, Wiley, New York, ©2001.