L2 Silicon Track Trigger All D0 Meeting 11 January 2002 Ulrich Heintz Boston University.

L2 Silicon Track TriggerAll D0 Meeting

11 January 2002

Ulrich Heintz

Boston University

1/11/2002 Ulrich Heintz - ADM 2

People and Institutions• Boston University

– Ulrich Heintz, Meenakshi Narain– Evgeny Popkov, Lars Sonnenschein, Jodi Wittlin– Kevin Black, Sarosh Fatakia, Lorenzo Feligioni, Alex Zabi– Eric Hazen, Bill Earle, Shouxiang Wu

• Columbia University– Hal Evans– Georg Steinbrück– Tulika Bose– An Qi

• Florida State University– Horst Wahl, Sue Blessing, Stephen Linn, Harrison Prosper– Bill Lee, Sylvia Tentinto-Repond– Reginald Perry, Arvindh Lalam, Shweta Lolage

• SUNY Stony Brook– John Hobbs– Wendy Taylor– Huishi Dong– Chuck Pancake, Bonnie Smart, Jane Wu


STT Functionality• Include SMT data in track trigger

– Only available at level 2– Use level 1 tracks as seeds for roads– Search for SMT hits in roads– Perform fit to SMT + CFT hits


Physics Motivation

Improved pT resolution and impact parameter measurement


Physics Motivation• Higgs Search

– ZH bb is almost as important as WH

– For MH = 110 GeV• Without STT: = 35% 14 fb-1 for 3 • With STT: = 80% 10 fb-1 for 3

Process Cross section

Branching fraction

Signal Background

WHl bb 224 fb 8.1% 5.0 57

ZHll bb 128 fb 2.6% 0.9 3.2

ZH bb 128 fb 15.4% 4.6 56

Source: Fermilab SUSY/Higgs study


Physics Motivation• Zbb

– requires two-jet trigger with low threshold

– L2STT gives • factor 13 rejection

• 50% efficiency

– allows unprescaled Zbb trigger

– establish bb lineshape, efficiency

• Hbb search

– b-jet scale to 1/3% stat• Top mass measurement


D0 Trigger System

L2FW:Combined objects (e, , j)

L2FW:Combined objects (e, , j)

L1FW: towers, tracks, correlations L1FW: towers, tracks, correlations

L1CAL

L2STT

Global L2

L2CFT

L2PS

L2Cal

L1CTT

L2Muon

L1Muon

L1FPD

Detector L1 Trigger L2 Trigger7 MHz 5-10 kHz

CAL

FPSCPS

CFT

SMT

Muon

FPD

1000 Hz


Conceptual Design

• L1CTTtracks in CFT– Define road in SMT

• Select SMT hits in roads• Fit trajectory to L1CTT+SMT

hits. Measure – pT, – impact parameter, – azimuth

• Send results to L2• Pass L1CTT information to L2• Send SMT clusters to L3

roaddata

SMTdata

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

FiberRoadCard

SiliconTriggerCard

TrackFit

CardL2CTT


Motherboard9Ux400mm VME board

SCL mezzanine card (FRC)Up to 6 link boardsLogic cardBuffer controller

Dedicated linesSCLlogic cardVTMlogic card

3 PCI busses (32bit/33MHz)Link boardslogic cardBuffer controllerlogic card

Universe II bridgePCI bus to VME bus

Design complete


Motherboard


Link Transmitter/Receiver Boards

• PCMIP standard • 3 LVDS serial links

– 24 bits @ 66 MHz– 16 data bits– Single bit error correction– Multibit error detection– >1012 bits w/o error

• 256k buffer (?)• design complete


Fiber Road Card– SCL

• Receive 128 bits every 132 ns• Fan out L1_QUAL, L1_TURN, L1_BX

– L1CTT data• Receive 1.5 Gbit/s glink VTM• Fan out

– manage L3 buffers• control allocation/deallocation of L3 buffers• send readout requests to VBD • send monitoring requests to CPU

– arbitrate VME bus


FRC


Buffer Controller

Universe II

L3 Data Buffer

Daughterboard

Buffer Controller

L3 Data Memory

Output FIFO

PCI-3

Input FIFO

BM msg Inter-face

L1 msg FIFO

L2 msg FIFO

BX

Evt No.

PCI Interface

PCI Interface

L3 Data Controller

DataJ3 L1_busy

L1_error

message

DB_L3_RDY,BC_BUSY, L1/2_ERROR,L1/2_BUSY

L2_error

PCI Interface


FRC

Buffercontroller

Buffercontroller

FRCFRC


Silicon Trigger Card

Strip reader

Cluster finder

Hit filter

SMTL1CTT

RoadLUT

SCL

L3

L3

TFC via serial link

from FRC via serial link

control logic

31

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12

11

10

9 8 7 6 5 4 3 2 1 0

track dEdx sequencer HDI chip centroid

L3

channel logic (x8)


Processing of SMT Data• bad strip mask

– zero amplitude of flagged strips

• pedestal/gain calibration– chip-by-chip lookup table

• clustering algorithm– similar to offline, use 5

strips for centroid

cluster

centroid

strippuls

e he

ight


STC Prototype 1 (2 channels)

controllogic

controllogic

RoadLUT

RoadLUT

XxxxXxxxxxxx

XxxxXxxxxxxx

channel logic(Altera APEX)

1.5M gates300 kbits RAM652 pin BGA

$1270

accommodates2 channels

need 4/STC

channel logic(Altera APEX)

1.5M gates300 kbits RAM652 pin BGA

$1270

accommodates2 channels

need 4/STC


STC Prototype 2 (8 channels)RoadLUT

RoadLUT

RoadL

UT

RoadL

UT

control logic(8x) channel logic(Xilinx Virtex E)

800k gates1.1 Mbits RAM560 pin BGA

$1200

accommodatesall 8 channelsneed 1/STC

Xilinx donated ¼ 70 FPGAs

control logic(8x) channel logic(Xilinx Virtex E)

800k gates1.1 Mbits RAM560 pin BGA

$1200

accommodatesall 8 channelsneed 1/STC

Xilinx donated ¼ 70 FPGAs


Track Fit Card

roads from FRChits from STC

tracks to L2

TI6202/3 (300 MHz)DSPs


Track Fit Algorithm • require hits in

– at least 3 of the 4 SMT layers– in same 30 degree sector– in at most 2 adjacent barrels

• choose hits – closest to trajectory defined by CFT and origin

• linearized 2 fit (r) = b/r + r + 0

– drop worst hit and refit if 4-hit 2 bad– measured execution time ¼10-15 s for a single

pass road with 3-6 hits


TFC


Hotlink Transmitter

• Transmits data from TFC to MBT in L2CTT– cypress hotlink– 8 bits @ 16 MHz– no errors in 5£1012 bits transferred to MBT using

built-in self test


CPU

1 2

spare

3

VBD

4 5 6 7

STC

8

STC

9

STC

10

STC

11

STC

12

STC

13

FRC

14

STC

15

STC

16

TFC

20

TFC

1918

STC

17 21

spare

spare

spare

terminator

spare

terminator

Sector 1 Sector 2

L2STT Crate

LVDS serial links for communication between boards


Inventory

module FRC STC TFC Crate Total

FRC logic board 1 - - 1 6

STC logic board - 1 - 9 54

TFC logic board - - 1 2 12

motherboard 1 1 1 12 72

SCL mezzanine card 1 - - 1 6

link transmitter 4 1 - 13 78

link receiver - 1 3 15 90

hotlink transmitter - - 1 2 12

buffer controller 1 1 1 12 72

VTM 1 1 - 10 60


MCH2• Passive Splitters in MCH2

– split g-link fiber from sequencer into two paths: STT and VRB

• Racks M202, M203, M204 in MCH2

M202-204


Output• to L2CTT

– all data from L1CTT– for each track

0 1 2 3 4 5 6 7 8 9 10

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12

13

14

15

16

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20

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30

31

pT ± S 2 x x f

b x dE/dx track x x f f f f barrel f

pT transverse momentum encoded in 0.25(3) GeV increments for pT <(>) 25 GeV:

b impact parameter

dE/dx ionization

± sign track track number (0-45)

S impact parameter significance barrel barrel number

azimuth f topology flags

2 goodness of fit x spares


Output• to L3 for each event

– all information sent to L2CTT – for all SMT clusters

– for all SMT clusters associated with a track

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10

9 8 7 6 5 4 3 2 1 0

0 chan typ dEdx sequencer HDI chip centroid

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30

29

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27

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25

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14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

track dEdx sequencer HDI chip centroid


Beam Stability• Need:

– <500 m offset, stable to <30 m– <100 rad tilt

• Vertex package in EXAMINE– Measure beam trajectory during run– Download at beginning of run– Store in accelerator control system– Input to feedback system


System Test• BU

– Test vectors– FRCSTCTFC

• FNAL– Integrate

• FRC and SCL/L1CTT • STC and SMT

– Vertical slice next


Schedule• as of October 2001:

– System Test• mid December 2001 – mid January 2002

– Production • mid January – mid May 2002

– Installation/Commissioning• mid May – mid June 2002....

• about 1 month late due to delays in prototype testing


Run 2b• SMT replacement: 6 axial barrel layers

– more readout units (HDIs)– need more STC boards

no upgrade full upgrademodest upgrade


Run 2bOption

No upgrade

Modest upgrade

Full upgrade

FRC logic board 6 6 6

STC logic board 54 60 72

TFC logic board 12 12 12

motherboard 72 78 90

SCL mezzanine card 6 6 6

link transmitter 78 90 102

link receiver 90 96 108

hotlink transmitter 12 12 12

buffer controller 72 78 90

VTM 60 66 78

Additional cost (no cont.) $34k $81k $231k


Conclusions• All modules prototyped

• Integration tests under way

• Production – started for some boards– rest will follow after more tests (¼ Feb)

• Goal: operational in June 2002

• Documentation– http://www-d0.fnal.gov/~wahl/vtxt.html

L2 Silicon Track Trigger All D0 Meeting 11 January 2002 Ulrich Heintz Boston University.

Documents

track trigger

jet trigger

ulrich heintz adm2 people

hz slide

l1ctt smt hits

unprescaled z bb trigger

smt cft hits

l2 silicon track